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Circuits
• Dynamic circuits
– Charge sharing, charge redistribution
• Domino logic
• np-CMOS (zipper CMOS)
Krish Chakrabarty 1
Dynamic Logic
• Dynamic gates use a clocked pMOS pullup
• Two modes: precharge and evaluate
Krish Chakrabarty 2
1
The Foot
• What if pulldown network is ON during
precharge?
• Use series evaluation transistor to prevent fight.
Krish Chakrabarty 3
Dynamic Logic
D
VD D
VD
Mp Me
t
Ou
CL
1
In
1
In 2
In N
PU
2
In N
PD 3
In
3
In t
Ou
Krish Chakrabarty 4
2
Logical Effort
Krish Chakrabarty 5
Dynamic Logic
• N+2 transistors for N-input function
– Better than 2N transistors for complementary static CMOS
– Comparable to N+1 for ratio-ed logic
• No static power dissipation
– Better than ratio-ed logic
• Careful design, clock signal needed
Krish Chakrabarty 6
3
Dynamic Logic: Principles
D
VD • Precharge
= 0, Out is precharged to VDD by Mp.
Mp
Me is turned off, no dc current flows
t
Ou
(regardless of input values)
CL
1
In • Evaluation
2
In N
PD
3
In = 1, Me is turned on, Mp is turned off.
Output is pulled down to zero depending
Me on the values on the inputs. If not,
precharged value remains on CL.
Krish Chakrabarty 7
Example
D
VD
Mp
t
Ou
•Ra tiole ss
•No Sta tic PowerCo nsumptio n
A •No is e Ma rg in
s small(N
M
L )
C
•Re quir e s Clo ck
B
Me
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4
Dynamic 4 Input NAND Gate
VDD
Out
In1
In2
In3
In4
GND
Krish Chakrabarty 9
Mp Mp
In
Ou t1 Ou t2
Ou t1
In VT n
Ou t2
Me Me t
Internal nodes can only make 0-1 transitions during evaluation period
Krish Chakrabarty 10
5
Monotonicity
• Dynamic gates require monotonically rising inputs
during evaluation
– 0 -> 0
– 0 -> 1
– 1 -> 1
– But not 1 -> 0
Krish Chakrabarty 11
Monotonicity Woes
• But dynamic gates produce monotonically falling
outputs during evaluation
• Illegal for one dynamic gate to drive another!
Krish Chakrabarty 12
6
Reliability Problems — Charge Leakage
D
VD
Mp
Ou t
(1 ) C
L
A t
Vo ut pr e c h
a r g e ev a lu
a t e
(2 )
A = 0
Me
t
(a ) Le a k a g e so u r c e s (b ) Ef f e c ton wa v e f o r m
s
Krish Chakrabarty 13
Leakage
• Dynamic node floats high during evaluation
– Transistors are leaky (IOFF 0)
– Dynamic value will leak away over time
– Formerly miliseconds, now nanoseconds!
• Use keeper to hold dynamic node
– Must be weak enough not to fight evaluation
Krish Chakrabarty 14
7
Charge Sharing (redistribution)
• Assume: during precharge, A and B are 0, Ca is discharged
VDD
• During evaluation, B remains 0 and A rises to 1
• Charge stored on CL is now redistributed over CL and Ca
Mp
Out
Krish Chakrabarty 15
Charge Sharing
• Dynamic gates suffer from charge sharing
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8
Charge Redistribution - Solutions
VDD
VDD
B Mb B Mb
Me Me
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Secondary Precharge
• Solution: add secondary precharge transistors
– Typically need to precharge every other node
• Big load capacitance CY helps as well
Krish Chakrabarty 18
9
Domino Logic
VDD
VDD
VDD
Out2
In1 Stat icInv er ter
In2 PDN In4 PDN withLevelRest ore r
In3
Me Me
Static inverters
between dynamic stages
Krish Chakrabarty 19
Domino Gates
• Follow dynamic stage with inverting static gate
– Dynamic / static pair is called domino gate
– Produces monotonic outputs
Krish Chakrabarty 20
10
Domino Logic - Characteristics
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Domino Optimizations
• Each domino gate triggers next one, like a string of
dominos toppling over
• Gates evaluate sequentially but precharge in parallel
• Thus evaluation is more critical than precharge
• HI-skewed static stages can perform logic
Krish Chakrabarty 22
11
Dual-Rail Domino
• Domino only performs noninverting functions:
– AND, OR but not NAND, NOR, or XOR
• Dual-rail domino solves this problem
– Takes true and complementary inputs
– Produces true and complementary outputs
Krish Chakrabarty 23
Example: AND/NAND
• Given A_h, A_l, B_h, B_l
• Compute Y_h = A * B, Y_l = ~(A * B)
• Pulldown networks are conduction complements
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12
Example: XOR/XNOR
• Sometimes possible to share transistors
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Domino Summary
• Domino logic is attractive for high-speed circuits
– 1.5 – 2x faster than static CMOS
– But many challenges:
• Monotonicity
• Leakage
• Charge sharing
• Noise
• Widely used in high-performance microprocessors
Krish Chakrabarty 26
13
np-CMOS (Zipper CMOS)
VDD
VDD
Mp Me
Out1
In1 PUN
In2 PDN In4
In3 Out2
Me Mp
Krish Chakrabarty 27
np CMOS Adder
Krish Chakrabarty 28
14
CMOS Circuit Styles - Summary
Krish Chakrabarty 29
15