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Compal Confidential
Model Name : AIZY0
1 File Name : LA-B921PR10 1
BOM P/N:43xxxxxxxx
2
Compal Confidential 2
3
2014-09-30 3
REV:1.0
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
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Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B921PR10
Date: Friday, October 17, 2014 Sheet 1 of 36
A B C D E
5 4 3 2 1
Compal Confidential
Model Name: AIZY0
File Name: LA-B921PR10
D
AIZY0 Intel Broadwell Y Block Diagram D
Speaker eCompass
P.15 USB2.0 USB2.0 Connector AK8963C
IO BD
C
Digital Array Mic *2 Audio Codec HDA Intel Broadwell-Y C
G-Sensor
SPI ROM (8MB) SPI Camera 1M HD KIONIX KXTJ2-1009
P.20 P.16
W25Q64FVSSIQ
P.07
Card Reader
Realtek RTS5170 SD Card Connector
Click Pad I2C_1 SATA SD BD SD BD
P.23
A A
LA-B921PR10
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/04/10 Deciphered Date 2017/04/10 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MB Block Diagram
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
sualaptop365.edu.vn
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, October 17, 2014 Sheet 2 of 36
5 4 3 2 1
1 2 3 4 5
S0
O O O O
S3
O O O X
S5 S4/AC
O O X X
S5 S4/ Battery only
X X X X
S5 S4/AC & Battery
B don't exist X X X X USB 2.0 Port Table USB 3.0 Port Table B
SMBUS Control Table HDMI Logo QGGY 1333/0.6G QGGZ 1333/0.8G QGGX 1600/0.8G QH1Y E0 0.8G QH0U E0 1.1G QH33 F0 0.8G QH2V F0 1.1G QH2R F0 1.2G
RO0000003HM SA00007TL00 SA00007TM00 SA00007TK00 SA00007YZ60 SA000084N20 SA00008BP00 SA00008BU00 SA00008BI00
Thermal 08/11, Add HDMI Logo P/N 07/01, Add QS SA00007YZ40 08/11, Add QS SA000084N00
HOST Changer BATT NPCE288 CPU HomeKey sensor
NCT7718W
PCB part DRAM
EC_SMB_CK1
EC_SMB_DA1
NPCE288 V
+3VLP
V
+3VLP
X X +3VALW
V X ZZZ003
+3VLP ZZZ3 H4G@ ZZZ4 M4G2@ ZZZ7 S4G@ ZZZ8 M4G1@ ZZZ9 S8G@ ZZZ10 E8G@ ZZZ5 M8G@ ZZZ6 H8G@
EC_SMB_CK2
EC_SMB_DA2
NPCE288 X X X V
+3VS
X V
+3VS
+3VS
SMBCLK
X X X X X X
PCB 19O LA-B921P REV1 M/B 1
CPU DA80011R110 HYNIX MICRON SAMSUNG MICRON SAMSUNG ELPIDA MICRON HYNIX
SMBDATA +3VALW 09/30, Change PCB P/N to Rev.1.0
X7658138L02 X7658138L03 X7658138L01 X7658138L04 X7658138L05 X7658138L07 X7658138L08 X7658138L06
SML0CLK
X X X X X X
H5TC4G63AFR-PBA MT41K256M16LY-107 K4B4G1646Q-HYK0 MT41K256M16HA-125:E K4B8G1646Q-MYK0 EDJ8416E6MB-GN-F MT41K512M16TNA-125E H5TC8G63AMR-PBA
CPU SA00005AV70 SA000081200 SA00005JC60 SA00005WD60 SA00006AT20 SA00006AU30 SA00006AV20 SA00006WZ20
SML0DATA +3VALW
PCB Rev.1A P/N:
DA80011R11A PCB 19O LA-B921P REV1A M/B 1
SML1CLK
X X V X X V
07/01, SA00005HTB0 change to SA000081200
D CPU D
SML1DATA +3VS +3VS +3VS
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Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-B921PR10
Friday, October 17, 2014 Sheet 3 of 36
1 2 3 4 5
5 4 3 2 1
UCPU1A
AD17
EDP_TXN0 EDP_TXN0 [20]
AD25 DDI AC17
DDI1_TXN_0 EDP_TXP0 EDP_TXP0 [20]
AC25 eDP AG18
DDI1_TXP_0 EDP_TXN1 EDP_TXN1 [20]
AD26 AE18
DDI1_TXN_1 EDP_TXP1 EDP_TXP1 [20]
AC26 AD18
AG25 DDI1_TXP_1 EDP_TXN2 AC18
AE25 DDI1_TXN_2 EDP_TXP2 AA17
AG26 DDI1_TXP_2 EDP_TXN3 W17
AE26 DDI1_TXN_3 EDP_TXP3 eDP
DDI1_TXP_3
D D
CPU_DP2_N0 AD22
[21] CPU_DP2_N0 DDI2_TXN_0
CPU_DP2_P0 AC22
[21] CPU_DP2_P0 DDI2_TXP_0 +VCCIOA_OUT
HDMI CPU_DP2_N1 AG22 AG16 EDP_AUXN [20]
[21] CPU_DP2_N1 DDI2_TXN_1 EDP_AUXN
CPU_DP2_P1 AE22 AE17 EDP_AUXP [20] EDP_COMP:
[21] CPU_DP2_P1 DDI2_TXP_1 EDP_AUXP
CPU_DP2_N2 AD21
[21] CPU_DP2_N2
CPU_DP2_P2 AC21 DDI2_TXN_2 AP41 EDP_COMP RC1 1 2 24.9_0402_1% Trace width = 20 mils, Spacing = 25 mil,
[21] CPU_DP2_P2 DDI2_TXP_2 EDP_RCOMP Max length = 100 mils
CPU_DP2_N3 AG21 Y21 CPU_INV_PW M RC124 1 @ 2 0_0402_5% INVPW M
[21] CPU_DP2_N3 DDI2_TXN_3 EDP_DISP_UTIL
RC2 1 @ 2 100K_0402_5% ENBKL CPU_DP2_P3 AE21 RC125 1 @ 2 0_0402_5%
[21] CPU_DP2_P3 DDI2_TXP_3
ESD @10K,3VS
10K,3VS
[23] CPU_TP_INT_N
[8] PCH_GPIO52
[8] PCH_GPIO54
L30
F35
H33
GPIO55
GPIO52
GPIO54
DDPB_HPD
DDPC_HPD
Y30
Y29
W29
DDI2_HDMI_HPD
EDP_HPD
DDI2_HDMI_HPD [21]
@10K,3VS [8] PCH_GPIO51 GPIO51 EDP_HPD EDP_HPD [20]
H_CPUPW RGD [16,8] SENSOR_HUB_INT# RC149 1 2 0_0402_5% C39
GPIO53
[8] PCH_GPIO53
1
ESD@ 10K,3VS
CC91
100P_0402_50V8J BDW -Y-LPDDR3_BGA1234 9 OF 20
2
CM41
XDP_PREQ_N
CPU_XDP_TCK
T34
T40
PU/PD for JTAG signals
@ESD@ RC8 1 2 10K_0402_5% H_CPUPW RGD CG42 THERMAL CU36 CPU_XDP_TDI T56
CC92 PROCPWRGD PROC_TDI CU38 CPU_XDP_TDO T57 RC126 1 @ 2 1K_0402_5%
PROC_TDO SYS_PW ROK [17,8]
100P_0402_50V8J RC9 1 2 62_0402_5%
+1.05VS_VTT
2
CM39 XDP_BPM_N_0
RC10 1 2 56_0402_5% H_PROCHOT#_R CH41 BPM_N_0 CN38 XDP_BPM_N_1 reserve Via
[17,25] H_PROCHOT# PROCHOT BPM_N_1
PWR JTAG CK36 SYS_PW ROK
RC13: 120 or 121 BPM_N_2 CM37
RC12 1 2 200_0402_1% SM_RCOMP0 CV7 BPM_N_3 CN36
SM_RCOMP0 BPM_N_4
1
RC13 1 2 120_0402_5% SM_RCOMP1 CP7 CR35 ESD@
B +1.35V RC15 1 2 100_0402_1% SM_RCOMP2 CT7 SM_RCOMP1 DDR3 BPM_N_5 CN34 CC102 B
DDR3_DRAMRST# AB2 SM_RCOMP2 BPM_N_6 CR34 100P_0402_50V8J
DDR3 Compensation Signals: [13,14] DDR3_DRAMRST#
2
DDR_PG_CTRL BL14 SM_DRAMRST BPM_N_7
Trace width = 20 mils, Spacing = 25 mil, SM_PG_CNTL1
1
BDW -Y-LPDDR3_BGA1234 2 OF 20
@
DDR3_DRAMRST#
+1.35V
1
CC3
0.1U_0402_16VK7 +3VALW
@
2
1
UC1 RC20
1 5 220K_0402_5%
NC VCC
DDR_PG_CTRL 2
2
A 4
Y DDR_VTT_PG_CTRL [29]
3
GND
A
74AUP1G07GW _TSSOP5 A
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Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B921PR10
Date: Friday, October 17, 2014 Sheet 4 of 36
5 4 3 2 1
5 4 3 2 1
UCPU1C UCPU1D
D D
BDW -Y-LPDDR3_BGA1234 3 OF 20
@
BDW -Y-LPDDR3_BGA1234 4 OF 20
@
A A
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Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B921PR10
Date: Friday, October 17, 2014 Sheet 5 of 36
5 4 3 2 1
5 4 3 2 1
PCH_RTCX1
1 2 PCH_RTCX2 UCPU1E
RC21 10M_0402_5%
+RTCVCC
1
YC1 SATA
1 2 +RTCVCC CC4 PCH_RTCX1 C9 V36
1U_0402_6.3V6K PCH_RTCX2 C7 RTCX1 SATA_RN0_PERN6_L3 V38
32.768KHZ 12.5PF 9H03200031 2 RC23 1 2 1M_0402_5% SM_INTRUDER# J5 RTCX2 RTC SATA_RP0_PERP6_L3 W43
RC22 20K_0402_1% PCH_INTVRMEN H6 INTRUDER SATA_TN0_PETN6_L3 AA43
1 2 PCH_SRTCRST# D6 INTVRMEN SATA_TP0_PETP6_L3
1 2 PCH_RTCRST# A8 SRTCRST T37
D 1 1 RTCRST SATA_RN1_PERN6_L2 SATA_PRX_DTX_N1 [18] D
CC5 CC6 RC24 20K_0402_1% T39 SATA_PRX_DTX_P1 [18]
CMOS SATA_RP1_PERP6_L2 T43
1 SATA_TN1_PETN6_L2 SATA_PTX_DRX_N1 [18] NGFF(SSD)
2
18P_0402_50V8J 15P_0402_50V8J HDA_BIT_CLK L6 Audio V42
2 2 HDA_BCLK_I2S0_SCLK SATA_TP1_PETP6_L2 SATA_PTX_DRX_P1 [18]
CC7 CLRP2 HDA_SYNC L4
1U_0402_6.3V6K HDA_RST# J9 HDA_SYNC_I2S0_SFRM Y38
SHORT PADS
1
2 HDA_SDIN0 L10 HDA_RST_N_I2S_MCLK SATA_RN2_PERN6_L1 W39 INTEL suggest when no use
@ [15] HDA_SDIN0 HDA_SDI0_I2S0_RXD SATA_RP2_PERP6_L1 need PU, if this pin set GPI
L8 T41
HDA_SDI1_I2S1_RXD SATA_TN2_PETN6_L1 +3VS
10/8, CC5 change 15P to 18P for RTC timing HDA_SDOUT N3
HDA_SDO_I2S0_TXD SATA_TP2_PETP6_L1
W41
N5
N7 HDA_DOCK_EN_N_I2S1_TXD W37 PCH_GPIO35 RC25 1 2 10K_0402_5%
To enable the integrated voltage regulator for N9 HDA_DOCK_RST_N__I2S1_SFRM SATA_RN3_PERN6_L0 Y36
+RTCVCC DCPSUS1, DCPSUS2, DCPSUS3 and I2S1_SCLK SATA_RP3_PERP6_L0 AB42 1 2
DCPSUS4 this signal must be pulled to SATA_TN3_PETN6_L0 NGFF_SSD_PEDET [18]
AA41 @ RC28 0_0402_5%
VCCRTC through a weak resistor (for SATA_TP3_PETP6_L0
PCH_INTVRMEN RC26 1 2 330K_0402_5% example, 330 KΩ ±5%). F29 PCH_GPIO34
To disable the integrated voltage regulator, SATA0GP_GPIO34 PCH_GPIO34 [8] 10K,3VS
RC27 1 @ 2 330K_0402_5% reserve Via PCH_JTAG_RST# CM7 H29 PCH_GPIO35
this signal must be pulled down through a PCH_TRST SATA1GP_SATAPHY_PC_GPIO35
weak resistor (for example, 330 KΩ ±5%) PCH_JTAG_TCK CK17 JTAG D33 PCH_GPIO36 10K,3VS
PCH_TCK SATA2GP_GPIO36 PCH_GPIO36 [8] +V1.05S_ASATA3PLL
INTVRMEN (+1.05VA) and the DCPSUS rails must be powered PCH_JTAG_TDI CL20 L26 PCH_GPIO37 PCH_GPIO37 [8] 10K,3VS
* H:Integrated VRM enable
L:Integrated VRM disable
externally. PCH_JTAG_TDO
PCH_JTAG_TMS
CL18
CK15
PCH_TDI
PCH_TDO
SATA3GP_GPIO37
L42 SATA_IREF RC127 1 2 0_0603_5%
P17 PCH_TMS SATA_IREF R34
G26 RSVD_P17 RSVD_R34 R32
PCH_TCK_JTAGX CL16 RSVD_G26 RSVD_R32 L44 SATA_RCOMP RC29 1 2 3.01K_0402_1%
C5 JTAGX SATA_RCOMP C30 PCH_SATALED#
Closed MCP 1000 mils RSVD_C5 SATALED PCH_SATALED# [8] 10K,3VS
SATA_COMP:
BDW -Y-LPDDR3_BGA1234 5 OF 20 Trace width = 15 mils, Spacing = 12 mil,
C @ Max length = 500 mils C
EMI XTAL24_IN
RP39
[15] HDA_RST_AUDIO# 1 8 HDA_RST# XTAL24_OUT RC34 1 2 1M_0402_5%
[15] HDA_BITCLK_AUDIO 2 7 HDA_BIT_CLK
[15] HDA_SDOUT_AUDIO 3 6 HDA_SDOUT RC66 1 2 0_0402_5% ME_EN [17]
4 5 HDA_SYNC YC2
[15] HDA_SYNC_AUDIO
33_8P4R_5% 1 3
EMI@ 1 3
GND GND 1
1 CC8
CC9 15P_0402_50V8J
UCPU1F 15P_0402_50V8J 2 4
2
Clock Signal 2
AD29 24MHZ_12PF_7V24000020
AC29 CLKOUT_PCIE_N0
PCIECLKREQ0_N B33 CLKOUT_PCIE_P0 AR44 XTAL24_IN
10K,3VS [8] PCIECLKREQ0_N PCIECLKRQ0_N_GPIO18 XTAL24_IN AP45 XTAL24_OUT
AD30 XTAL24_OUT
AC30 CLKOUT_PCIE_N1 BK41
PCIECLKREQ1_N H25 CLKOUT_PCIE_P1 RSVD_BK41 BK43
10K,3VS [8] PCIECLKREQ1_N PCIECLKRQ1_N_GPIO19 RSVD_BK43 A38 XCLK_BIASREF RC37 1 2 3.01K_0402_1% +V1.05S_AXCK_LCPLL
AE30 DIFFCLK_BIASREF
B AG30 CLKOUT_PCIE_N2 AC33 TESTLOW 1 1 8 B
PCIECLKREQ2_N P25 CLKOUT_PCIE_P2 TESTLOW_AC33 AD33 TESTLOW 2 2 7
10K,3VS [8] PCIECLKREQ2_N PCIECLKRQ2_N_GPIO20 TESTLOW_AD33 N14 TESTLOW 3 3 6
CLK_PCIE_WLAN# AC34 TESTLOW_N14 M15 TESTLOW 4 4 5
[19] CLK_PCIE_WLAN# CLKOUT_PCIE_N3 TESTLOW_M15
CLK_PCIE_WLAN AD34
[19] CLK_PCIE_WLAN CLKOUT_PCIEP3
WLAN [19,8] WLAN_CLKREQ# P27 K15 RP40 10K_8P4R_5%
PCIECLKRQ3_N_GPIO21 CLKOUT_LPC_0 L14
10K,3VS CLKOUT_LPC_1
AE29 CLKOUT_LPC0 RC38 2 1 22_0402_5%
CLKOUT_PCIE_N4 CK_LPC_KBC [17]
AG29
PCIECLKREQ4_N D35 CLKOUT_PCIE_P4
10K,3VS [8] PCIECLKREQ4_N PCIECLKRQ4_N_GPIO22
AG33 AE34 CLK_BCLK_ITP# T49
AE33 CLKOUT_PCIE_N5 CLKOUT_ITPXDP_P AG34 CLK_BCLK_ITP T50
PCIECLKREQ5_N G30 CLKOUT_PCIE_P5 CLKOUT_ITPXDP
RTC Battery 10K,3VS [8] PCIECLKREQ5_N PCIECLKRQ5_N_GPIO23
RC39 1 2 806_0402_1%
08/21, RC39 change to 806 ohm
1
C5265
1U_0402_6.3V6K
A 2 A
sualaptop365.edu.vn
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B921PR10
Date: Thursday, October 23, 2014 Sheet 6 of 36
5 4 3 2 1
5 4 3 2 1
UCPU1G
2
@ 1 2 +3VS
PCH_SPI_CS0#_R RC128 1 2 0_0402_5% PCH_SPI_CS0#
C C
SML1CLK 6 1
EC_SMB_CK2 [17,23]
2N7002KDWH_SOT363-6
QC1A RC44
2.2K_0402_5%
5
@ 1 2 +3VS
SML1DATA 3 4 EC_SMB_DA2 [17,23]
RP42
SMBCLK 1 8 +3VALW_PCH
CC11 SMBDATA 2 7
22P_0402_50V8J moodule design 499 ohm SML0CLK 3 6
B RP43 @EMI@ SML0DATA 4 5 B
1 8 PCH_SPI_MISO_R CRB 2.2K
[17]
[17]
EC_SPI_MISO
EC_SPI_MOSI
2
3
7
6
PCH_SPI_MOSI_R
PCH_SPI_CLK_R
EMI SML1DATA
2.2K_0804_8P4R_5%
RC49 1 @ 2 2.2K_0402_5%
[17] EC_SPI_CLK
4 5 PCH_SPI_CS0#_R SML1CLK RC50 1 @ 2 2.2K_0402_5%
[17] EC_SPI_CS0#
33_0804_8P4R_5%
A A
1
ESD@
RC52 1 2 330K_0402_5% CC93
+3VS UCPU1H 100P_0402_50V8J
2
RC56 1 @ 2 330K_0402_5% RC53 1 2 0_0402_5%
1 8 PCH_GPIO64 T58 SUSACK#_R D19 System Power Management G14 DSWODVREN
2 7 PCH_GPIO68 SYS_RESET# E26 SUSACK DSWVRMEN J7 DPWROK RC54 1 2 0_0402_5% EC_RSMRST#
10K,3VS SYS_RESET DPWROK
3 6 PCH_GPIO69 @10K,3VS XDP SYS_PWROK A22 F19 PCH_PCIE_WAKE# +3VS 07/07, change to mount
[17,4] SYS_PWROK SYS_PWROK WAKE 1K,+3VALW_PCH
4 5 SYS_RESET# [17] PCH_PWROK PCH_PWROK F9 @
RC55 1 2 0_0402_5% APWROK_R J22 PCH_PWROK B35 PCH_GPIO32 UC3
APWROK GPIO32_CLKRUN 10K,3VS
5
RP65 10K_8P4R_5% H_PLT_RST# M23 D25 PCH_GPIO61 @10K,+3VALW_PCH
+3VALW_PCH RC57 1 2 10K_0402_5% PLTRST SUS_STAT_N_GPIO61 B27 H_PLT_RST# 2
P
D
F7 SUSCLK_GPIO62 A18 PM_SLP_S5# SUSCLK_WLAN [19] B 4
D
[17] EC_RSMRST# EC_RSMRST#
RSMRST SLP_S5_N_GPIO63 PM_SLP_S5# [17] Y PLT_RST# [17,19]
1 8 PCH_GPIO0 10K,+3VALW_PCH PCH_GPIO30 D8 1
SUSWARN_N_SUSPWRDNACK_GPIO30 A
1
2 7 PCH_GPIO1 PBTN_OUT# M21 H19 PM_SLP_S4#
[17] PBTN_OUT# PWRBTN SLP_S4 PM_SLP_S4# [17]
3 6 PCH_GPIO2 RC51 AC_PRESENT M17 N22 PM_SLP_S3# RC59
[17] AC_PRESENT ACPRESENT_GPIO31 SLP_S3 PM_SLP_S3# [17]
3
4 5 PCH_GPIO3 200K_0402_5% 10K,+3VALW_PCH PCH_GPIO72 H17 G18 PM_SLP_A# T52 100K_0402_5%
SLP_S0_N G22 BATLOW_N_GPIO72 SLP_A D27 SLP_SUS_N T54 MC74VHC1G08DFT2G_SC70-5
T53 J18 SLP_S0 SLP_SUS
@ RP64 10K_8P4R_5% @10K,+3VALW_PCH PCH_GPIO29 K19 SLP_LAN_N T55
SLP_WLAN_N_GPIO29 SLP_LAN
2
08/21, change to unpop AC_PRESENT
1 8 PCH_GPIO91
2
3
4
7
6
5
PCH_GPIO92
PCH_GPIO93
PCH_GPIO94 ESD ESD BDW-Y-LPDDR3_BGA1234
@
8 OF 20 ESD
H_THERMTRIP# +3VS
@ RP63 10K_8P4R_5% PCH_PWROK EC_RSMRST# +1.05VS_VTT
1
08/21, change to unpop 1 @ESD@
1
1
1 8 PCH_GPIO84 CC95 1000P_0402_50V7K UCPU1J 100P_0402_50V8J PCH_GPIO86 RC110 1 @ 2 1K_0402_1%
2
2 7 PCH_GPIO85 100P_0402_50V8J ESD@ RC60 RC111 1 2 1K_0402_1%
2
3 6 PCH_GPIO89 2 1K_0402_1%
4 5 PCH_GPIO90
10K,3VS PCH_GPIO76 J30 CPU/MISC
BMBUSY_N_USB3PHY_PC_GPIO76
2
10K,+3VALW_PCH C18 CG40
@ RP62 10K_8P4R_5%
10K,+3VALW_PCH
PCH_GPIO8
GPIO8 THERMTRIP
H_THERMTRIP# GSPI0_MOSI / GPIO86 : Boot BIOS Strap
08/21, change to unpop PCH_GPIO12 J14 C34
1
2
8
7 PCH_GPIO48
PCIECLKREQ4_N [6]
ESD @1K,+3VALW_PCH
10K,3VS
10K,3VS
PCH_GPIO15
PCH_GPIO16
PCH_GPIO17
K25
N26
H31
LAN_PHY_PWR_CTRL_GPIO12
GPIO15
GPIO16
RCIN_N_GPIO82
SERIRQ
PCH_OPI_RCOMP
E34
AB4
AJ14
SERIRQ
PCH_OPIRCOMP
RC61
1 2
KB_RST#
SERIRQ
[17]
[17]
1: LPC BUS
10K,+3VALW_PCH GPIO17 RSVD_AJ14
3 6 SYS_RESET# PCH_GPIO24 C22 AL18 49.9_0402_1% 0: SPI BUS (Have internal PD)
4 5
WLAN_CLKREQ#
PCIECLKREQ2_N
[19,6]
[6]
10K,+3VALW_PCH PCH_GPIO27 K17 GPIO24
GPIO27
RSVD_AL18
*
1
+3VALW_PCH
0 0 1 1 ELPIDA EDJ4216EFBG-GN-F
RC1461 2 10K_0402_5% PCH_GPIO27
1
1
0 1 0 0 SAMSUNG K4B8G1646Q-MYK0
RC67 1 2 10K_0402_5% RC116 RC117 RC118 RC119
PCH_GPIO11 [7]
RC136 1 2 1K_0402_5% PCH_PCIE_WAKE# 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 0 1 0 1 ELPIDA EDJ8416E6MB-GN-F
RC1471 2 10K_0402_5% DDR_ID
X76@ X76@ X76@ X76@ 0 1 1 0 MICRON MT41K512M16TNA-125:E
2
2
RC1481 @ 2 10K_0402_5% DDR_ID RAM_ID3 RAM_ID2 RAM_ID1 RAM_ID0
1 8 PCH_GPIO12 PU 10K to +3VALW_PCH (DDR3L) 0 1 1 1 HYNIX H5TC8G63AMR-PBA
1
1
2 7 PCH_GPIO8 PU down 10K (LP-DDR3)
3 6 PCH_GPIO73 [7] RC120 RC121 RC122 RC123 1 0 0 0 MT41K256M16LY-107
4 5 PCH_GPIO30 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
1 0 0 1 TBD
RP54 10K_8P4R_5% X76@ X76@ X76@ X76@
2
2
+3VS
1 0 1 0 TBD
1 8
2 7 PCH_GPIO61 1 0 1 1 TBD
3 6 RC137 1 @ 2 1K_0402_5% SPKR
4 5 PCH_GPIO29 1 1 0 0 TBD
A A
@ RP55 10K_8P4R_5%
+3VALW_PCH
1 1 0 1 TBD
1 8 SENSOR_HUB_RST# 1 1 1 0 TBD
2 7 PCH_GPIO13
3 6 SENSOR_HUB_INT#_R 1 8 PCH_GPIO44 1 1 1 1 TBD
4 5 PCH_GPIO25 2 7 PCH_GPIO26
3 6 PCH_GPIO45
RP57 10K_8P4R_5% 4 5 PCH_GPIO24
sualaptop365.edu.vn
RP59 10K_8P4R_5% Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B921PR10
Date: Friday, October 17, 2014 Sheet 8 of 36
5 4 3 2 1
5 4 3 2 1
UCPU1K
AF40
AG41 PERN5_L0 W12 USB20_N0
PERP5_L0 USB2N0 USB20_N0 [22]
V12 USB20_P0 USB2.0 IO (Sub Board)
USB2P0 USB20_P0 [22]
AU40
AU42 PETN5_L0 T9 USB20_N1
PETP5_L0 USB2N1 USB20_N1 [19]
V10 USB20_P1 USB3.0 IO (Main Board)(Debug port)
USB2P1 USB20_P1 [19]
AD40
AE41 PERN5_L1 PCIE Y10 USB20_N2
USB
PERP5_L1 USB2N2 USB20_N2 [22]
D Y8 USB20_P2 DCIN USB COMBO D
USB2P2 USB20_P2 [22]
AW40
AW42 PETN5_L1 AB10 USB20_N3
PETP5_L1 USB2N3 USB20_N3 [22]
AA9 USB20_P3 Card Reader
USB2P3 USB20_P3 [22]
AE43
AD42 PERN5_L2 W9 USB20_N4
PERP5_L2 USB2N4 USB20_N4 [22]
W7 USB20_P4 Touch Screen
USB2P4 USB20_P4 [22]
BA42
BA40 PETN5_L2 V8 USB20_N5
PETP5_L2 USB2N5 USB20_N5 [20]
T7 USB20_P5 Camera
USB2P5 USB20_P5 [20]
AF42
AG43 PERN5_L3 V6 USB20_N6
PERP5_L3 USB2N6 USB20_N6 [19]
T5 USB20_P6 Mini Card (WLAN+BT)
USB2P6 USB20_P6 [19]
BB41
BB43 PETN5_L3 Y6 USB20_N7
PETP5_L3 USB2N7 USB20_N7 [16]
W5 USB20_P7 Sensor
USB2P7 USB20_P7 [16]
AD38
AC39 PERN3 V4
PERP3 RSVD_V4 T3
AY41 RSVD_T3
AY43 PETN3 Y4
PETP3 RSVD_Y4 W3
PCIE_PRX_DTX_N4 AH38 RSVD_W3
[19] PCIE_PRX_DTX_N4 PERN4
[19] PCIE_PRX_DTX_P4 PCIE_PRX_DTX_P4 AH40
PERP4 AJ41
CC17 1 2 0.1U_0402_16VK7 PCIE_PTX_DRX_N4 AV41 USB3RN1 AM41
WLAN [19] PCIE_PTX_C_DRX_N4
CC18 1 2 0.1U_0402_16VK7 PCIE_PTX_DRX_P4 AV43 PETN4USB3.0 P3 / PCIE P1 USB3RP1
[19] PCIE_PTX_C_DRX_P4 PETP4 BG42
AF38 USB3TN1 BG40
C AE39 PERN1_USB3RN3 USB3TP1 C
PERP1_USB3RP3 AM43
USB3RN2 USB3_RX2_N [19]
BD41 USB3.0 P4 / PCIE P2 AK42
PETN1_USB3TN3 USB3RP2 USB3_RX2_P [19]
BD43 BF41 USB3.0 (Main Board)
PETP1_USB3TP3 USB3TN2 USB3_TX2_N [19]
BF43
USB3TP2 USB3_TX2_P [19]
AH42
AJ43 PERN2_USB3RN4
PERP2_USB3RP4 CAD note:
B13 USBRBIAS RC68 1 2 22.6_0402_1%
BC40 USBRBIAS D13 Route single-end 50-ohms and max 450-mils length.
BC42 PETN2_USB3TN4 USBRBIAS H13 Avoid routing next to clock pins or under stitching capacitors.
+V1.05S_AUSB3PLL PETP2_USB3TP4 RSVD_H13 F13
RSVD_F13 Recommended minimum spacing to other signal traces is 15 mils
AT41
AT43 RSVD_AT41 E18 USB_OC0#
RSVD_AT43 OC0_N_GPIO40 USB_OC0# [19] For USB Port 0,1
RC69 1 2 3.01K_0402_1% PCIE_RCOMP F41 E22 USB_OC1# USB_OC1# [22] For USB Port 2,3
C41 PCIE_RCOMP OC1_N_GPIO41 H21 USB_OC2#
PCIE_IREF OC2_N_GPIO42 For USB Port 4,5
D21 USB_OC3# For USB Port 6,7
OC3_N_GPIO43
PCIE_RCOMP:
Trace width = 15 mils, Spacing = 15 mil,
Max length = 500 mils BDW -Y-LPDDR3_BGA1234 11 OF 20 closed MCP 2000 mils
@ +3VALW _PCH
RP60
USB_OC0# 1 8
USB_OC1# 2 7
USB_OC2# 3 6
USB_OC3# 4 5
10K_8P4R_5%
B B
UCPU1R
BDW -Y-LPDDR3_BGA1234 18 OF 20
@
A A
sualaptop365.edu.vn
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B921PR10
Date: Friday, October 17, 2014 Sheet 9 of 36
5 4 3 2 1
5 4 3 2 1
+1.35V_CPU
1
+ CC20
220U_D2_2VY_R17M
@
2
2.2U_0402_6.3V6M
CC22
2.2U_0402_6.3V6M
CC24
2.2U_0402_6.3V6M
CC25
10U_0402_6.3V6M
CC26
10U_0603_6.3V6M
CC23
10U_0402_6.3V6M
CC27
10U_0402_6.3V6M
CC28
10U_0603_6.3V6M
CC29
10U_0402_6.3V6M
CC30
@ @ CL1 BF45
CM3 VDDQ_CL1 VCC_BF45 BH45
1 1 1 1 1 1 1 1 1 1 VDDQ_CM3 VCC_BH45
CW1 BT45
AP1 VDDQ_CW1 VCC_BT45 BV45
AV1 VDDQ_AP1 VCC_BV45 BY45
2 2 2 2 2 2 2 2 2 2 BB1 VDDQ_AV1 VCC_BY45 CB45
BC14 VDDQ_BB1 VCC_CB45 CD45
BE14 VDDQ_BC14 VCC_CD45 CF45
BF1 VDDQ_BE14 VCC_CF45 CM45
BK1 VDDQ_BF1 VCC_CM45 CN44
VDDQ_BK1 VCC_CN44
CRB: +CPU_CORE
+CPU_CORE BP1
CR1 VDDQ_BP1 VCC_CR43
CR43
CR45
+1.35V : 470UF/2V/7343 *2 (Un-mount) CAD Note: PD resistor should be close to CPU
VDDQ_CR1 VCC_CR45 CU44
VCC_CU44
10UF/6.3V/0603 * 6 RC70 1 2 100_0402_1%
AV45
CJ28 VCC_AV45 VCC_CV43
CV43
CV45
2.2UF/6.3V/0402 * 4 +1.05VS_VTT RSVD_CJ28 VCC_CV45 CY19
RC71 1 2 0_0402_5% VCCSENSE_R CH45 VCC_CY19 CY21
[32] VCCSENSE VCC_SENSE VCC_CY21
AL16 CY23
RSVD_AL16 VCC_CY23
1
C
+VCCIO_OUT BM43 CY25 C
RC72 AR40 VCCIO_OUT VCC_CY25 CY27
+VCCIOA_OUT VCCIOA_OUT VCC_CY27
10K_0402_5% AL22 CY29
AK33 RSVD_AL22 VCC_CY29 CY31
CL14 RSVD_AK33 VCC_CY31 CY33
2
RC73 1 2 43_0402_1% H_CPU_SVIDALRT# CD43 RSVD_CL14 VCC_CY33 CY36
[32] VR_SVID_ALRT# VIDALERT VCC_CY36
[17] VCCST_PW RGD VCCST_PW RGD RC74 1 2 0_0402_5% H_CPU_SVIDCLK CD41 CY38
[32] VR_SVID_CLK VIDSCLK VCC_CY38
RC75 1 2 0_0402_5% H_CPU_SVIDDAT CE40 CY42
[32] VR_SVID_DAT VIDSOUT VCC_CY42
VCCST_PW RGD BU14 CY44
VCCST_PWRGD VCC_CY44
Define EC OD pin, need double confirm. [32] VR_ON
CE42
VR_EN VCC_BM45
BM45
RC82 1 2 0_0402_5% VR12.6PG_MCP CF43 BP45
[32] VGATE VR_READY VCC_BP45 CA44
VCC_CA44 BV41
CPU_PW R_DEBUG CK40 VCC_BV41 BV43
PWR_DEBUG VCC_BV43 BW44
CJ22 VCC_BW44 CY40
CK23 RSVD_TP_CJ22 VCC_CY40 CY13
CK27 RSVD_TP VCC_CY13 CY15
SVID ALERT +1.05VS_VTT CL26 IVR_ERROR
IST_TRIGGER
VCC_CY15
VCC_BW42
BW42
R253: CPU_PWR_DEBUG CK21
RSVD_CK21 VCC_BY43
BY43
CL22 CA42
+1.05VS_VTT CRB mount CK25 RSVD_CL22 VCC_CA42 CB43
Check list ,XDP use only RSVD VCC_CB43
2
Place the PU CM27
RSVD_CM27
RC77 @ CK19
resistors close to CPU RSVD_CK19
1
150_0402_1% CJ16
RC78 CK31 RSVD_CJ16
75_0402_5% RSVD_CK31
1
+1.05VS_VCCST AJ20
CPU_PW R_DEBUG VCCST_AJ20
2
B B
VR_SVID_ALRT# 2
RC79 @
10K_0402_5%
+1.05VS_VTT
SVID DATA BDW -Y-LPDDR3_BGA1234 12 OF 20
1
Place the PU @
resistors close to CPU
1
RC80
130_0402_5%
+1.05VS_VTT +1.05VS_VCCST +VCCIO_OUT
2
H_CPU_SVIDDAT
RC134 2 1 0_0603_5% 2 @ 1
VIDSOUT: RC135 0_0603_5%
Requires a pull-up to VCCIO through a pull-up resistor of 110 ±5% close to the processor,
and a pull-up to VCCIO through a pull-up resistor of 110 ±5% close to Intel MVP 7. 22U_0603_6.3V6M 1 1
CC31
1U_0402_6.3V6K
CC32
VIDSCLK: @
Required pull-up to VCCIO through 55 ±5% close to Intel IMVP 7.
2 2
A A
sualaptop365.edu.vn
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B921PR10
Date: Friday, October 17, 2014 Sheet 10 of 36
5 4 3 2 1
5 4 3 2 1
+1.05VS_VTT +V1.05S_MPHY_PCIE
RC83 1 2 0_0805_5%
1 1 1
CC33 CC34 CC35
1U_0402_6.3V6K 0.1U_0402_16VK7 0.1U_0402_16VK7
2 2 2
UCPU1M
+1.05VS_VTT +V1.05S_MPHY_SATA
AB38 +RTCVCC
+V1.05S_MPHY_PCIE VCCPCIEPHY_AB38
RC84 1 2 0_0805_5% W45 AC15 +V3.3A_DSW_PRTCSUS
AA45 VCCPCIEPHY_W45 VCCSUS3_3_RTC_AC15 AA15
N45 VCCPCIEPHY MPHY VCCRTC V15 CC36 1 2 0.1U_0402_16VK7
1 1 +V1.05S_MPHY_SATA RTC
D T45 VCCSATAPHY DCPRTC D
VCCSATAPHY_T45 1 1 1
CC37 CC40 AC45 A24 @
+V1.05S_MPHY_USB3 VCCUSB3PHY_AC45 VCCSPI +3VALW_PCH
1U_0402_6.3V6K 0.1U_0402_16VK7 AD36 SPI T25 1 CC41 CC38 CC39
2 2 AE45 VCCUSB3PHY_AD36 VCCSPI_T25
VCCUSB3PHY 1U_0402_6.3V6K 0.1U_0402_16VK7 0.1U_0402_16VK7
RC85 1 2 0_0603_5% +V1.05S_AIDLE T31 AE15 CC42 2 2 2
+1.05VS_VTT VCC1_05_PHY VCCASW +1.05VS_VTT
0.1U_0402_16VK7
T33 Y22 2
1 +V1.05S_ASATA3PLL VCCSATA3PLL VCC1_05_Y22 +V1.05S_CORE_PCH
CC43 +V1.05S_AUSB3PLL T35 W22
+1.05VS_VTT +V1.05S_MPHY_USB3 VCCUSB3PLL USB3 VCC1_05_W22 AJ16
1U_0402_6.3V6K VCC1_05_AJ16
+V1.05S_APLLOPI AK19 AH36 +3V_DSW_P Reserve for inrush
RC86 1 2 0_0805_5% 2 AK29 VCCOPIPLL VCC1_05_AH36 AG45
+V1.05S_APLL 1 current issue
VCCHDAPLL VCC1_05_AG45 AJ45 @ CC44
U30 VCC1_05 T17 0.47U_0402_6.3V6K
1 1 +V1.05A_VCCUSB3SUS DCPSUS3 VCC1_05_T17 RC87 closed to pin Y22, W22, AJ16, AH36, AG45, AJ45, T17
CC45 CC46 W1 AG13 +PCH_VCCDSW 1 2 2 CC47 1 2 1U_0402_6.3V6K
+VCCHDA VCCHDA_W1 HDA DCPSUSBYP
1U_0402_6.3V6K 0.1U_0402_16VK7 AA13 N1 0_0402_5%
2 2 AG14 VCCHDA VCCASW_N1 T1 +V1.05S_CORE_PCH RC88 +1.05VS_VTT
+V1.05A_VCCUSB2SUS DCPSUS2 VCCASW_T1 W14 +1.05VM_VCCASW 0_0805_5%
U18 VCCASW_W14 1 2
+V3.3A_PSUS VCCSUS3_3
+3V_DSW_P AA1 U16 +V1.05A_VCCPCHSUS
+1.05VS_VTT +V1.05S_ASATA3PLL AB14 VCCDSW3_3_AA1 DCPSUS1 CC48 1 2 0.1U_0402_16VK7
VCCDSW3_3_AB14 1 1 1
AJ32
VCCTS1_5 +1.5VS
LC1 1 2 +V3.3S_PCORE A30 AB36 +3VS CC50 CC51 CC52
2.2UH_LQM2MPN2R2NG0L_30% A28 VCC3_3_A30 DSW VCCTS3_3_AB36 10U_0603_6.3V6M
VCC3_3_A28 1U_0402_6.3V6K 0.1U_0402_16VK7
A26 A32 2 2 2
1 1 1 VCC3_3_A26 VCCSDIO +3VS
T27
@ CC53 CC54 CC55 VCC3_3 T21 +V1.05A_AOSCSUS CC56 1 2 0.1U_0402_16VK7
AL37 DCPSUS4
22U_0805_6.3V6M 22U_0805_6.3V6M 1U_0402_6.3V6K +V1.05S_AXCK_DCB VCCCLK4
1
AJ26 ICC @
+1.05VS_VTT +V1.05S_AUSB3PLL +V1.05S_SSCF100 VCCCLK7 2
+V1.05S_SSCF135 AL39 CC58 CC59 CC60
AJ28 VCCCLK5 22U_0603_6.3V6M
+V1.05S_SCLKF135 VCCCLK3 0.1U_0402_16VK7 0.1U_0402_16VK7
LC2 1 2 AK23 2 2 2
+V1.05S_CLKF24NS VCCCLK1
C
2.2UH_LQM2MPN2R2NG0L_30% +V3.3A_PSUS AL14 INTEL suggest CC60 can C
VCCSUS3_3_AL14
@ 1 1 1 be unpop
@ CC1 @ CC2 CC98 closed to pin AE15, N1, T1, W14 for VCCASW
22U_0805_6.3V6M 22U_0805_6.3V6M 1U_0402_6.3V6K
2 2 2
BDW-Y-LPDDR3_BGA1234 13 OF 20
5/20 LC2,CC1,CC2,CC53 unpop @
LC1 , RC150 , CC55,CC98 pop DCPSUS can be NC, if INTVRMEN pull up
to enable Integrated VRM
+1.05VS_VTT +V1.05S_AXCK_DCB
<3/3 BDW SI>Follow Audio codec power rail +3VALW_PCH +3V_DSW_P
LC3 1 2 +1.05VS_VTT +V1.05A_VCCUSB3SUS
RC91
2.2UH_LQM2MPN2R2NG0L_30%
+3VALW_PCH RC90 2 1 0_0603_5% 1 @ 2
1 1 1
INTEL suggest CC77 can be unstuff 1 1
1 1 CC61 @ CC62 CC63 0_0402_5% @
1
1
0.1U_0402_16VK7
CC64
10U_0603_6.3V6M
RC92 CC77 RC151 2 2 2
CC65
1U_0402_6.3V6K
2 2
0_0603_5% +VCCHDA 1U_0402_6.3V6K 0_0402_5% @
2 2
INTEL suggest CC61,CC69 need POP
2
2
+1.05VS_VTT +V1.05S_AXCK_LCPLL
B RC98 B
+V1.05S_APLLOPI
+3VS +V3.3S_PCORE 1 @ 2 +V1.05A_VCCPCHSUS
0_0402_5% 2 1 RC97 1
closed to pin A30, A28, A26, T27 1 0_0402_5% @
RC99 2 1 0_0603_5% CC74
+1.05VS_VTT CC73 1U_0402_6.3V6K
1U_0402_6.3V6K 2
1 1 1 2
@
CC75 CC76 CC99 LC5 1 2
0.1U_0402_16VK7 0.1U_0402_16VK7 0.1U_0402_16VK7 2.2UH_LQM2MPN2R2NG0L_30%
2 2 2 +V1.05S_APLL
INTEL suggest 1pcs 22uF change to 2 pcs 0.1uF +1.05VS_VTT
RC100 1 2 0_0603_5% +V1.05S_APLLOPI_IND 0_0402_5% 2 1 RC101 +V1.05A_AOSCSUS
1
1
@ @ @ 1
1
CC81 CC82 CC83
+V1.05S_AUSB
47U_0805_6.3V6M
47U_0805_6.3V6M
1U_0402_6.3V6K
2
2
0_0402_5% 2 1 RC102 2
1
closed to pin AL30 closed to pin AK31 closed to pin AJ26 CC84
RC103
+3VALW_PCH +V3.3A_PSUS 1U_0402_6.3V6K
+1.05VS_VTT RC140 +V1.05S_F100 +1.05VS_VTT RC141 +V1.05S_SSCFF +1.05VS_VTT RC142 +V1.05S_SSCF100 2 1 @ 2
0_0402_5% 0_0402_5% 0_0402_5% RC139 1 2 0_0603_5%
1 2 1 2 1 2 0_0402_5%
1 1 1 1 1
CC85 CC86 CC87 CC49 CC100
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0402_6.3V6M 10U_0402_6.3V6M
2 2 2 2 2
08/04, CC49(22U) change to 10U*2(CC49,CC100)
A A
LA-B921PR10
Rev
1.0
UCPU1O
UCPU1N
UCPU1S
T65 CFG0 CV27 BJ14 AH29 AY13
RC104 1 2 1K_0402_5% CFG4 T67 CFG1 CT27 CFG_0 RSVD_TP_BJ14 BT15 AM19 VSS VSS AY15
T68 CFG2 CP27 CFG_1 RSVD_TP_BT15 AL32 L24 AH6 VSS VSS AY39
T69 CFG3 CU28 CFG_2 RSVD_TP_AL32 AL34 L16 VSS AH31 VSS VSS BA44
CFG4 CV29 CFG_3 RSVD_TP_AL34 AA18 H10 VSS CW20 AH30 VSS VSS BB3
eDP Strap T66 CFG5 CT29 CFG_4 RSVD_TP_AA18 Y18 H36 VSS VSS AM39 AH33 VSS VSS BB5
T70 CFG6 CM29 CFG_5 RSVD_TP_Y18 CK13 CN26 VSS VSS L32 AH32 VSS VSS BB7
T71 CFG7 CU30 CFG_6 RSVD_TP_CK13 CL34 BP7 VSS VSS CN42 AH34 VSS VSS BB9
1 : Disabled; No Physical Display Port T72 CFG8 CN30 CFG_7 RSVD_CL34 CL28 BP39 VSS VSS CP3 AH44 VSS VSS BB11
D D
attached to Embedded Display Port T73 CFG9 CV31 CFG_8 RSVD_CL28 AJ22 BR44 VSS VSS CP17 AJ39 VSS VSS BB13
T74 CFG10 CP31 CFG_9 RSVD_AJ22 AL20 BT1 VSS VSS CP29 AJ30 VSS VSS BB15
CN32 CFG_10 RSVD_AL20 AB6 BT7 VSS VSS CR8 AJ37 VSS VSS BB39
CFG4 * 0 : Enabled; An external Display
T75
T76
CFG11
CFG12 CV33 CFG_11 PROC_OPI_RCOMP
CFG_12 RSVD_CK6
CK6
PROC_OPI_COMP
BT13 VSS
VSS
VSS
VSS
CR14 AK6 VSS
VSS
VSS
VSS
BC44
T77 CFG13 CU34 CL8 J16 CR18 AJ18 BD1
Port device is connected to the T78 CFG14 CT33 CFG_13 RSVD_CL8 BT39 VSS VSS CR22 AM17 VSS VSS BD7
CP33 CFG_14 RESERVED BU44 VSS VSS CR26 AN6 VSS VSS BD13
Embedded Display Port T79 CFG15
CFG_15 VSS VSS VSS VSS
T80 CFG16 CR28 BV7 CR37 AR42 BD15
T81 CFG18 CN28 CFG_16 AK25 BV13 VSS VSS CT31 AK12 VSS VSS BD39
T82 CFG17 CR32 CFG_17 RSVD_AK25 AL24 BV15 VSS VSS CU8 AK21 VSS VSS BE40
T83 CFG19 CU32 CFG_18 RSVD_AL24 BV39 VSS VSS CU14 AK27 VSS VSS BE42
RC105 2 1 49.9_0402_1% CFG_RCOMP CFG_RCOMP CR30 CFG_19 N18 BY1 VSS VSS CU18 BE44 VSS VSS BF7
CFG_RCOMP RSVD_N18 P33 BY3 VSS VSS CU22 AM13 VSS VSS BF13
RC106 2 1 49.9_0402_1% PROC_OPI_COMP BT41 RSVD_P33 AP3 BY5 VSS VSS CU26 BL8 VSS VSS BF15
BT43 RSVD_BT41 RSVD_AP3 W21 BY7 VSS VSS CU42 CJ18 VSS VSS BF39
RC107 2 1 8.2K_0402_5% TD_IREF BJ40 RSVD_BT43 RSVD_W21 AJ34 BY9 VSS VSS CV35 CJ24 VSS VSS BG14
BJ42 RSVD_BJ40 RSVD_AJ34 Y34 BY11 VSS VSS CV37 AM21 VSS VSS BG44
TD_IREF L40 RSVD_BJ42 RSVD_Y34 Y33 BY13 VSS VSS CW5 AM23 VSS VSS BH1
Trace width = 15mils, Spacing = 15 mil, TD_IREF RSVD_Y33 VSS VSS VSS VSS
W33 BY15 CW8 AM25 BH7
Max length = 500 mils RSVD_W33 BY39 VSS VSS CW22 AM27 VSS VSS BH13
C16 VSS VSS CW24 AM29 VSS VSS BH15
BDW -Y-LPDDR3_BGA1234 19 OF 20 C20 VSS VSS CW26 AM31 VSS VSS BH39
@ C24 VSS VSS CW28 AM35 VSS VSS BH41
UCPU1T C28 VSS VSS CW32 CJ30 VSS VSS BH43
C32 VSS VSS CW34 AM45 VSS VSS BJ44
T23 C36 VSS VSS CY7 CL5 VSS VSS BK7
AR12 VSS AD32 CB7 VSS VSS CY10 AN2 VSS VSS BK13
AU12 VSS VSS AH14 CB13 VSS VSS D10 AN4 VSS VSS BK15
C AV3 VSS VSS AH12 CB15 VSS VSS G28 CL24 VSS VSS BK39 C
AV5 VSS VSS AG37 CB39 VSS VSS J24 AN8 VSS VSS BL2
AV9 VSS VSS AG35 CC40 VSS VSS J28 AN10 VSS VSS BL4
AC1 VSS VSS AG32 CC42 VSS VSS CD9 AN12 VSS VSS BL6
AC24 VSS VSS AG28 UCPU1P UCPU1Q CC44 VSS VSS CD5 AN14 VSS VSS BL10
AC19 VSS VSS AG24 CD1 VSS VSS CD3 AN40 VSS VSS BL12
AH15 VSS VSS AG19 CL32 CD7 VSS VSS CC10 AN42 VSS VSS BL40
AB16 VSS VSS AF44 CH7 J43 VSS CL30 CD13 VSS VSS CA8 AN44 VSS VSS BL42
AB15 VSS VSS AF16 VSS V2 J1 VSS VSS CK33 CD15 VSS VSS AW14 AP7 VSS VSS BL44
AB12 VSS VSS AF14 VSS E16 D42 VSS VSS CK29 CD39 VSS VSS AR14 AP15 VSS VSS BM1
AB8 VSS VSS AF12 VSS U24 A42 VSS VSS CJ34 CE44 VSS VSS AG39 AP43 VSS VSS BM7
AA37 VSS VSS AF6 VSS R30 Y44 VSS VSS CG14 CF7 VSS VSS BU40 CN1 VSS VSS BM13
AA35 VSS VSS AE37 U22 VSS N20 W32 VSS VSS CE14 CF13 VSS VSS BU42 AT1 VSS VSS BM39
AC13 VSS VSS AE35 G20 VSS VSS AK15 W35 VSS VSS BW14 CF15 VSS VSS L2 AT7 VSS VSS BN44
AA34 VSS VSS AE32 E20 VSS VSS AM33 Y2 VSS VSS BR14 CG44 VSS VSS L20 AT15 VSS VSS BP13
AA33 VSS VSS AE28 N24 VSS VSS AK44 Y12 VSS VSS BN14 CH13 VSS VSS L28 AT39 VSS VSS CH1
AA32 VSS VSS AE24 N28 VSS VSS CA14 Y14 VSS VSS AF36 CJ26 VSS VSS CD11 AT45 VSS VSS CH15
AA30 VSS VSS AE19 N32 VSS VSS U28 Y16 VSS VSS AA11 CK3 VSS VSS G32 AU44 VSS VSS CV39
AA29 VSS VSS AE16 P35 VSS VSS U32 W34 VSS VSS Y19 CK10 VSS VSS CW30 AV13 VSS VSS CV41
AA28 VSS VSS AD44 R2 VSS VSS V17 W30 VSS VSS Y24 CK38 VSS VSS J20 AV15 VSS VSS CW12
AB40 VSS VSS AD28 R4 VSS VSS V40 T13 VSS VSS Y28 CK44 VSS VSS J32 AV39 VSS VSS CW14
AA26 VSS VSS AD24 R6 VSS VSS R44 L38 VSS VSS Y32 CL12 VSS VSS AW44 VSS VSS CW16
AA25 VSS VSS AD19 R8 VSS VSS T15 Y42 VSS VSS Y40 CM15 VSS CU1 VSS VSS CW18
AA24 VSS VSS AD16 R10 VSS VSS F5 A6 VSS VSS J3 CM17 VSS AY1 VSS VSS AJ24
AA22 VSS VSS AD12 E24 VSS VSS G16 D4 VSS VSS J45 CM19 VSS AY7 VSS VSS AP39
AA21 VSS VSS AD6 R16 VSS VSS R18 H42 VSS VSS CM21 VSS CV3 VSS VSS
AA19 VSS VSS AC43 R22 VSS VSS U26 VSS CM23 VSS VSS
AA7 VSS VSS AC41 E28 VSS VSS U34 CM25 VSS
AA5 VSS VSS AC37 R24 VSS VSS G24 CM31 VSS
B AA39 VSS VSS AC35 R26 VSS VSS N16 CM35 VSS B
AA3 VSS VSS AC9 R28 VSS VSS AJ13 CM43 VSS BDW -Y-LPDDR3_BGA1234
A40 VSS VSS AC7 AV7 VSS VSS AC32 BDW -Y-LPDDR3_BGA1234 17 OF 20 CN8 VSS 14 OF 20
A36 VSS VSS AC3 E32 VSS VSS @ VSS @
A20 VSS VSS AB44 E36 VSS AL28
A10 VSS VSS AC28 R20 VSS VSS AL26
BM15 VSS VSS AD14 VSS VSS CJ20
VSS VSS VSS
BP15
VSS VSS
AC11
VSS
CF39 RC38 & RC39 close to PCH BDW -Y-LPDDR3_BGA1234
CN5 AC5 15 OF 20
CR5 VSS VSS W18 CH43 VSSSENSE_R RC108 1 2 0_0402_5% @
VSS VSS VSS_SENSE_CH43 VSSSENSE [32]
CU5 W16
VSS VSS V44 RC109 1 2 100_0402_1%
W28 VSS U20 BDW -Y-LPDDR3_BGA1234 16 OF 20
W24 VSS VSS U14 @
W19 VSS VSS T19
AH22 VSS VSS AH28
AH21 VSS VSS AH27
AH20 VSS VSS AH26
AH19 VSS VSS AH25
AH17 VSS VSS AH23
VSS VSS AV11
VSS AH16
VSS H4
VSS A16
VSS T29
VSS
A A
BDW -Y-LPDDR3_BGA1234
20 OF 20
@ Security Classification Compal Secret Data Compal Electronics, Inc.
2014/04/10 2017/04/10 Title
Issued Date Deciphered Date BDW MCP(9/9) RSVD, GND
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
sualaptop365.edu.vn
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B921PR10
Date: Friday, October 17, 2014 Sheet 12 of 36
5 4 3 2 1
A B C D E
On Board A
DDR_A_MA[0..15]
[5] DDR_A_MA[0..15]
DDR_A_DQS#[0..7]
[5] DDR_A_DQS#[0..7]
DDR_A_DQS[0..7]
[5] DDR_A_DQS[0..7]
DDR_A_D[0..63]
[5] DDR_A_D[0..63]
1 1
.047U_0402_16V7K
.047U_0402_16V7K
.047U_0402_16V7K
.047U_0402_16V7K
.047U_0402_16V7K
.047U_0402_16V7K
.047U_0402_16V7K
A2 DQL5 A2 DQL5 A2 DQL5 A2 DQL5
1
1
DDR_A_MA3 N2 G2 DDR_A_D2 DDR_A_MA3 N2 G2 DDR_A_D22 DDR_A_MA3 N2 G2 DDR_A_D56 DDR_A_MA3 N2 G2 DDR_A_D55
DDR_A_MA4 P8 A3 DQL6 H7 DDR_A_D1 DDR_A_MA4 P8 A3 DQL6 H7 DDR_A_D20 DDR_A_MA4 P8 A3 DQL6 H7 DDR_A_D60 DDR_A_MA4 P8 A3 DQL6 H7 DDR_A_D52
DDR_A_MA5 P2 A4 DQL7 DDR_A_MA5 P2 A4 DQL7 DDR_A_MA5 P2 A4 DQL7 DDR_A_MA5 P2 A4 DQL7
2
2
DDR_A_MA6 R8 A5 DDR_A_MA6 R8 A5 DDR_A_MA6 R8 A5 DDR_A_MA6 R8 A5
DDR_A_MA7 R2 A6 D7 DDR_A_D13 DDR_A_MA7 R2 A6 D7 DDR_A_D31 DDR_A_MA7 R2 A6 D7 DDR_A_D43 DDR_A_MA7 R2 A6 D7 DDR_A_D38
DDR_A_MA8 T8 A7 DQU0 C3 DDR_A_D14 DDR_A_MA8 T8 A7 DQU0 C3 DDR_A_D27 DDR_A_MA8 T8 A7 DQU0 C3 DDR_A_D44 DDR_A_MA8 T8 A7 DQU0 C3 DDR_A_D32
DDR_A_MA9 R3 A8 DQU1 C8 DDR_A_D12 DDR_A_MA9 R3 A8 DQU1 C8 DDR_A_D29 DDR_A_MA9 R3 A8 DQU1 C8 DDR_A_D40 DDR_A_MA9 R3 A8 DQU1 C8 DDR_A_D36
DDR_A_MA10 L7 A9 DQU2 C2 DDR_A_D11 DDR_A_MA10 L7 A9 DQU2 C2 DDR_A_D25 DDR_A_MA10 L7 A9 DQU2 C2 DDR_A_D46 DDR_A_MA10 L7 A9 DQU2 C2 DDR_A_D39
DDR_A_MA11 R7 A10/AP DQU3 A7 DDR_A_D8 DDR_A_MA11 R7 A10/AP DQU3 A7 DDR_A_D26 DDR_A_MA11 R7 A10/AP DQU3 A7 DDR_A_D45 DDR_A_MA11 R7 A10/AP DQU3 A7 DDR_A_D33
DDR_A_MA12 N7 A11 DQU4 A2 DDR_A_D10 DDR_A_MA12 N7 A11 DQU4 A2 DDR_A_D28 DDR_A_MA12 N7 A11 DQU4 A2 DDR_A_D42 DDR_A_MA12 N7 A11 DQU4 A2 DDR_A_D37
DDR_A_MA13 T3 A12/BC DQU5 B8 DDR_A_D9 DDR_A_MA13 T3 A12/BC DQU5 B8 DDR_A_D24 DDR_A_MA13 T3 A12/BC DQU5 B8 DDR_A_D41 DDR_A_MA13 T3 A12/BC DQU5 B8 DDR_A_D34
DDR_A_MA14 T7 A13 DQU6 A3 DDR_A_D15 DDR_A_MA14 T7 A13 DQU6 A3 DDR_A_D30 DDR_A_MA14 T7 A13 DQU6 A3 DDR_A_D47 DDR_A_MA14 T7 A13 DQU6 A3 DDR_A_D35
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
+1.35V +1.35V +1.35V +1.35V
E7 A9 E7 A9 E7 A9 E7 A9
D3 DML VSS B3 D3 DML VSS B3 D3 DML VSS B3 D3 DML VSS B3
DMU VSS E1 DMU VSS E1 DMU VSS E1 DMU VSS E1
VSS G8 VSS G8 VSS G8 VSS G8
DDR_A_DQS#0 G3 VSS J2 DDR_A_DQS#2 G3 VSS J2 DDR_A_DQS#7 G3 VSS J2 DDR_A_DQS#6 G3 VSS J2
DDR_A_DQS#1 B7 DQSL VSS J8 DDR_A_DQS#3 B7 DQSL VSS J8 DDR_A_DQS#5 B7 DQSL VSS J8 DDR_A_DQS#4 B7 DQSL VSS J8
DQSU VSS M1 DQSU VSS M1 DQSU VSS M1 DQSU VSS M1
VSS M9 VSS M9 VSS M9 VSS M9
VSS P1 VSS P1 VSS P1 VSS P1
DDR3_DRAMRST# T2 VSS P9 DDR3_DRAMRST# T2 VSS P9 DDR3_DRAMRST# T2 VSS P9 DDR3_DRAMRST# T2 VSS P9
[14,4] DDR3_DRAMRST# RESET VSS RESET VSS RESET VSS RESET VSS
T1 T1 T1 T1
DDR_A_ZQ1 L8 VSS T9 DDR_A_ZQ2 L8 VSS T9 DDR_A_ZQ3 L8 VSS T9 DDR_A_ZQ4 L8 VSS T9
ZQ VSS ZQ VSS ZQ VSS ZQ VSS
96-BALL
VSSQ
VSSQ
G9
96-BALL
VSSQ
VSSQ
G9
96-BALL
VSSQ
VSSQ
G9
@ESD@
CD53
100P_0402_50V8J
2
+1.35V
ESD
DDR3_DRAMRST# MA_ODT RD1 1 2 30_0402_5% RD2 1 2 240_0402_1% DDR_A_ZQ1
1
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
4.7U_0603_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
[5] +V_DDR_VREFCA DDR_A_MA3 RD12 1 2 34.8_0402_1% @ @ @ @
DDR_A_MA4 RD14 1 2 34.8_0402_1% RD15 1 2 240_0402_1% DDR_A_ZQ8
DDR_A_MA5 RD16 1 2 34.8_0402_1%
+V_DDR_VREFDQ0 [5] +1.35V 2 2 2 2 2 2 2
DDR_A_MA6 RD17 1 2 34.8_0402_1%
DDR_A_MA7 RD20 1 2 34.8_0402_1%
DDR_A_MA8 RD21 1 2 34.8_0402_1% +1.35V
1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_16VK7
0.1U_0402_16VK7
0.1U_0402_16VK7
0.1U_0402_16VK7
1.8K_0402_1% 1 2 DDR_A_MA14 RD28 1 2 34.8_0402_1% CD27 @
220U_B2_2.5VM_R15M
RD23 DDR_A_MA15 RD29 1 2 34.8_0402_1%
0_0402_5% DDR_A_WE# RD34 1 2 34.8_0402_1%
2
2 2 2 2 2 2 2 2 2 2 2
1
+1.35V
@ @ @ @ @ @ @ @
1 CD56 1 CD57 1 CD58 1 CD59 1 CD60 1 CD61 1 CD62 1 CD63 1 CD64 1 CD65 1 CD66 1 CD67 1 CD68 1 CD69 1 CD70 1 CD71
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
4 4
10/8, POP CD56, CD58, CD62, CD63, CD64, CD66, CD68, CD70 for RMT
sualaptop365.edu.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B921PR10
Date: Friday, October 17, 2014 Sheet 13 of 36
A B C D E
A B C D E
On Board B
DDR_B_MA[0..15]
[5] DDR_B_MA[0..15]
DDR_B_DQS#[0..7]
[5] DDR_B_DQS#[0..7]
DDR_B_DQS[0..7]
[5] DDR_B_DQS[0..7]
DDR_B_D[0..63]
[5] DDR_B_D[0..63]
.047U_0402_16V7K
.047U_0402_16V7K
.047U_0402_16V7K
.047U_0402_16V7K
.047U_0402_16V7K
.047U_0402_16V7K
.047U_0402_16V7K
A2 DQL5 A2 DQL5 A2 DQL5 A2 DQL5
1
1
DDR_B_MA3 N2 G2 DDR_B_D27 DDR_B_MA3 N2 G2 DDR_B_D19 DDR_B_MA3 N2 G2 DDR_B_D63 DDR_B_MA3 N2 G2 DDR_B_D55
DDR_B_MA4 P8 A3 DQL6 H7 DDR_B_D31 DDR_B_MA4 P8 A3 DQL6 H7 DDR_B_D23 DDR_B_MA4 P8 A3 DQL6 H7 DDR_B_D59 DDR_B_MA4 P8 A3 DQL6 H7 DDR_B_D49
DDR_B_MA5 P2 A4 DQL7 DDR_B_MA5 P2 A4 DQL7 DDR_B_MA5 P2 A4 DQL7 DDR_B_MA5 P2 A4 DQL7
2
2
DDR_B_MA6 R8 A5 DDR_B_MA6 R8 A5 DDR_B_MA6 R8 A5 DDR_B_MA6 R8 A5
DDR_B_MA7 R2 A6 D7 DDR_B_D3 DDR_B_MA7 R2 A6 D7 DDR_B_D9 DDR_B_MA7 R2 A6 D7 DDR_B_D43 DDR_B_MA7 R2 A6 D7 DDR_B_D38
DDR_B_MA8 T8 A7 DQU0 C3 DDR_B_D1 DDR_B_MA8 T8 A7 DQU0 C3 DDR_B_D14 DDR_B_MA8 T8 A7 DQU0 C3 DDR_B_D42 DDR_B_MA8 T8 A7 DQU0 C3 DDR_B_D37
DDR_B_MA9 R3 A8 DQU1 C8 DDR_B_D4 DDR_B_MA9 R3 A8 DQU1 C8 DDR_B_D8 DDR_B_MA9 R3 A8 DQU1 C8 DDR_B_D44 DDR_B_MA9 R3 A8 DQU1 C8 DDR_B_D35
DDR_B_MA10 L7 A9 DQU2 C2 DDR_B_D0 DDR_B_MA10 L7 A9 DQU2 C2 DDR_B_D15 DDR_B_MA10 L7 A9 DQU2 C2 DDR_B_D45 DDR_B_MA10 L7 A9 DQU2 C2 DDR_B_D34
DDR_B_MA11 R7 A10/AP DQU3 A7 DDR_B_D6 DDR_B_MA11 R7 A10/AP DQU3 A7 DDR_B_D12 DDR_B_MA11 R7 A10/AP DQU3 A7 DDR_B_D40 DDR_B_MA11 R7 A10/AP DQU3 A7 DDR_B_D32
DDR_B_MA12 N7 A11 DQU4 A2 DDR_B_D2 DDR_B_MA12 N7 A11 DQU4 A2 DDR_B_D10 DDR_B_MA12 N7 A11 DQU4 A2 DDR_B_D47 DDR_B_MA12 N7 A11 DQU4 A2 DDR_B_D39
DDR_B_MA13 T3 A12/BC DQU5 B8 DDR_B_D7 DDR_B_MA13 T3 A12/BC DQU5 B8 DDR_B_D11 DDR_B_MA13 T3 A12/BC DQU5 B8 DDR_B_D41 DDR_B_MA13 T3 A12/BC DQU5 B8 DDR_B_D36
DDR_B_MA14 T7 A13 DQU6 A3 DDR_B_D5 DDR_B_MA14 T7 A13 DQU6 A3 DDR_B_D13 DDR_B_MA14 T7 A13 DQU6 A3 DDR_B_D46 DDR_B_MA14 T7 A13 DQU6 A3 DDR_B_D33
A14 DQU7 A14 DQU7 A14 DQU7 A14 DQU7
+1.35V +1.35V +1.35V +1.35V
2 E7 A9 E7 A9 E7 A9 E7 A9 2
D3 DML VSS B3 D3 DML VSS B3 D3 DML VSS B3 D3 DML VSS B3
DMU VSS E1 DMU VSS E1 DMU VSS E1 DMU VSS E1
VSS G8 VSS G8 VSS G8 VSS G8
DDR_B_DQS#3 G3 VSS J2 DDR_B_DQS#2 G3 VSS J2 DDR_B_DQS#7 G3 VSS J2 DDR_B_DQS#6 G3 VSS J2
DDR_B_DQS#0 B7 DQSL VSS J8 DDR_B_DQS#1 B7 DQSL VSS J8 DDR_B_DQS#5 B7 DQSL VSS J8 DDR_B_DQS#4 B7 DQSL VSS J8
DQSU VSS M1 DQSU VSS M1 DQSU VSS M1 DQSU VSS M1
VSS M9 VSS M9 VSS M9 VSS M9
VSS P1 VSS P1 VSS P1 VSS P1
DDR3_DRAMRST# T2 VSS P9 DDR3_DRAMRST# T2 VSS P9 DDR3_DRAMRST# T2 VSS P9 DDR3_DRAMRST# T2 VSS P9
[13,4] DDR3_DRAMRST# RESET VSS RESET VSS RESET VSS RESET VSS
T1 T1 T1 T1
DDR_B_ZQ1 L8 VSS T9 DDR_B_ZQ2 L8 VSS T9 DDR_B_ZQ3 L8 VSS T9 DDR_B_ZQ4 L8 VSS T9
ZQ VSS ZQ VSS ZQ VSS ZQ VSS
+0.675VS
08/04, INTEL REQUEST
+1.35V
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
4.7U_0603_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
DDR_B_MA3 RD52 1 2 34.8_0402_1% @ @ @ @
+V_DDR_VREFDQ1 [5]
DDR_B_MA4 RD53 1 2 34.8_0402_1% RD54 1 2 240_0402_1% DDR_B_ZQ3
DDR_B_MA5 RD55 1 2 34.8_0402_1%
3 DDR_B_MA6 RD56 1 2 34.8_0402_1% 2 2 2 2 2 2 2 RD57 1 2 240_0402_1% DDR_B_ZQ4 3
+1.35V +V_DDR_REFB DDR_B_MA7 RD58 1 2 34.8_0402_1%
DDR_B_MA8 RD59 1 2 34.8_0402_1% RD60 1 2 240_0402_1% DDR_B_ZQ5
DDR_B_MA9 RD61 1 2 34.8_0402_1%
1
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.1U_0402_16VK7
0.1U_0402_16VK7
0.1U_0402_16VK7
0.1U_0402_16VK7
24.9_0402_1% DDR_B_CS1# RD82 1 2 34.8_0402_1% CD48 @
2
220U_B2_2.5VM_R15M
DDR_B_CKE0 RD83 1 2 34.8_0402_1%
DDR_B_CKE1 RD84 1 2 34.8_0402_1%
2
+1.35V
@ @ @ @ @ @ @ @ @ @ @ @ @ @
1 CD74
1U_0402_6.3V6K 1 CD75 1 CD76 1 CD77 1 CD78 1 CD79 1 CD80 1 CD81 1 CD82 1 CD83 1 CD84 1 CD85 1 CD86 1 CD87
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
2 2 2 2 2 2 2 2 2 2 2 2 2 2
4 4
sualaptop365.edu.vn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B921PR10
Date: Friday, October 17, 2014 Sheet 14 of 36
A B C D E
A B C D E
1U_0402_6.3V6K
0.1U_0402_16VK7
0.1U_0402_16VK7
1 1
1
CA4
CA5
CA6
+5VS
2
2 2
RA1 1 2 0_0805_5% +5VS_PVDD
Place near Pin1 Place near Pin9
0.1U_0402_16VK7
0.1U_0402_16VK7
4.7U_0603_6.3V6K
2 1 1
+5VDDA_CODEC +5VS
CA2
CA3
CA1
1 1 2 2 1
+IOVDD_CODEC RA4 1 2 0_0603_5%
+1.5VS
1U_0402_6.3V6K
0.1U_0402_16VK7
+3VDD_CODEC
RA5 1 2 0_0402_5%
1 1 Place RA4 on AGND/DGND moat
CA7
CA11
CA8 1 2 1U_0402_6.3V6K 2 2
41
46
26
40
1
9
UA1
PVDD1
PVDD2
AVDD1
AVDD2
DVDD
DVDD-IO
LINE1-L 22
LINE1-R 21 LINE1-L(PORT-C-L) 43 SPK_L1-
LINE1-R(PORT-C-R) SPK-OUT-L- 42 SPK_L2+
RA6
wide 40MIL 24
23 LINE2-L(PORT-E-L)
LINE2-R(PORT-E-R)
SPK-OUT-L+
SPK-OUT-R+
45
44
SPK_R2+
SPK_R1-
1 2 2.2K_0402_5% EXT_MIC_RING2 17 SPK-OUT-R-
+MIC2-VREFO MIC2-L(PORT-F-L) /RING2
1 2 2.2K_0402_5% EXT_MIC_SLEEVE 18
RA7 MIC2-R(PORT-F-R) /SLEEVE 32 HP_OUTL
31 HPOUT-L(PORT-I-L) 33
+LINE1-VREFO-R
30 LINE1-VREFO-L HPOUT-R(PORT-I-R)
HP_OUTR
Headphone
[20] DMIC_DAT 1
EMI
2 BLM15BB221SN1D_2P
2
3
LINE1-VREFO-R
GPIO0/DMIC-DATA
SYNC
BCLK
10
6
HDA_SYNC_AUDIO
HDA_BITCLK_AUDIO
[6]
[6] EMI
External DMIC [20] DMIC_CLK
LA1
RA8 1
EMI@
@ 2 10K_0402_5%
DMIC_CLK_R
GPIO1/DMIC-CLK RA101 @EMI@ 2 33_0402_5% @EMI@ CA12 22P_0402_50V8J
RA11 1 2 0_0402_5% 47 5
08/04, EMI REQUEST [6]
[17] EC_MUTE#
HDA_RST_AUDIO# 11 PDB
RESETB
ALC233-CG SDATA-OUT
SDATA-IN
8 HDA_SDIN0_AUDIO RA12 1 2 33_0402_5%
HDA_SDOUT_AUDIO
HDA_SDIN0 [6]
[6]
+3VS
48
SPDIF-OUT/GPIO2 +MIC2-VREFO
2 DMIC_CLK PC_BEEP 12 2
PCBEEP
2
16
PLUG_IN#_R 13 MONO-OUT CA13 2 1 2.2U_0402_6.3V6M
14 SENSE A RA38
@EMI@ 1
CA35 37
SENSE B
MIC2-VREFO
29 CA14 2 1 2.2U_0402_6.3V6M 100K_0402_5% Combo Jack
1
CBP
2
1000P_0402_50V7K CA15 2 1 1U_0402_6.3V6K 35
CBN LDO3-CAP
LDO2-CAP
7
39
LDO3
LDO2
CA16 2 1 2.2U_0402_6.3V6M
(Normal Open)
27 LDO1 2 1
@ 36 LDO1-CAP RA15 100K_0402_5% PLUG_IN#_R RA13 1 2 200K_0402_5% PLUG_IN#
+3VDD_CODEC CPVDD PLUG_IN# [22]
CA17 2 1 4.7U_0603_6.3V6K
15
CA18 1 2 1U_0402_6.3V6K
EMI
JDREF RA17 1 @ 2 20K_0402_1% W=60mils EXT_MIC_SLEEVE RA19 2 EMI@ 1 FCM1608CF-121T03 0603 EXT_MIC_SLEEVE_R
JDREF EXT_MIC_SLEEVE_R [22]
CA19 2 1 2.2U_0402_6.3V6M 19 34 CPVEE W=60mils EXT_MIC_RING2 RA20 2 EMI@ 1 FCM1608CF-121T03 0603 EXT_MIC_RING2_R
MIC-CAP CPVEE EXT_MIC_RING2_R [22]
HP_OUTL RA22 1 EMI@ 2 47_0402_5% HP_OUTL_R
1 2 HP_OUTL_R [22]
2 HP_OUTR RA23 EMI@ 47_0402_5% HP_OUTR_R
HP_OUTR_R [22]
RA18 1 @ 2 0_0402_5% 4
49 DVSS 25 CA20
Thermal PAD AVSS1 38
AVSS2 1
1U_0402_6.3V6K For Universal Audio Jack
ALC233-VB2-CG MQFN 48P LINE1-L CA21 2 1 1U_0402_6.3V6K
2
SA00007BF10
RA26
RA27
220P_0402_50V7K
220P_0402_50V7K
LINE1-R CA22 2 1 1U_0402_6.3V6K
1
RA29 1 2 4.7K_0402_5%
EMI
+LINE1-VREFO-R
RA41 1 2 0_0402_5% 06/30, CA32 replace to RA21,
CA33 replace to RA24, CA34 RA32 1 2
4.7K_0402_5%
RA42 1 2 0_0402_5%
replace to RA25
GND GNDA
EMI
wide 40MIL JSPK1
SPK_R2+ LA5 1 2 0_0603_5% SPK_R2+_CONN 1
SPK_R1- LA6 1 2 0_0603_5% SPK_R1-_CONN 2 1
PC Beep SPK_L1-
SPK_L2+
LA7
LA8
1
1
2
2
0_0603_5%
0_0603_5%
SPK_L1-_CONN
SPK_L2+_CONN
3
4
2
3
4
5
6 G1
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
G2
EMI@ 1 EMI@1 EMI@1 EMI@1
ESD ACES_50278-00401-001
ME@
CA28
CA29
CA30
CA31
RA39 1 2 0_0402_5% CA25 +5VS
EC Beep [17] BEEP#
1 RA34 2 1 2 PC_BEEP
RA40 1 2 0_0402_5% 2 2 2 2
PCH Beep [8] SPKR
1K_0402_5% 0.1U_0402_16VK7 @ESD@ DA3
SPK_R1-_CONN 6 3 SPK_L2+_CONN
I/O4 I/O2
1
@
RA36 5 2
10K_0402_5% VDD GND
4 4
2
SPK_R2+_CONN 4 1 SPK_L1-_CONN
I/O3 I/O1
AZC099-04S.R7G_SOT23-6
+3VS_SEN +3VS_SEN
1
+3VS_PLL
R5 DS1
1 100K_0402_5% RB751V-40_SOD-323 R15 1 2 0_0402_5% 1
@
+AVCC
2
WRST# R5220 1 @ 2 0_0402_5% SENSOR_HUB_RST# [8] R4 1 2 0_0402_5%
11
IO Vdd
& updating FW
3
2 IO Vdd U2102 +3VS_SEN +3VS_SEN
4 +AVCC 33
1 RSVD AVCC
+3VS ADDR 1
0.1U_0402_16VK7
C16
1
2.2K_0402_5%
2.2K_0402_5%
6
SENSE_SDA 2 GND 8 2
SENSE_SCL 12 SDA GND 9 47 I2C0_SCL_SEN_R R8 R7
SCL GND 7 SMCLK0/GPB3 48 I2C0_SDA_SEN_R
+3VS_PLL VSTBY(PLL) SMDAT0/GPB4 2 SENSOR_DEBUG_CLK
2
SMCLK2/GPF6
SM BUS
KXTJ2-1009_LGA12_2X2 3 SENSOR_DEBUG_DAT
SMDAT2/GPF7 13 SENSE_SCL
1 1 1 SMCLK4/GPE0 SENSE_SCL [20]
1000P_0402_50V7K
C5271
1000P_0402_50V7K
C5272
0.1U_0402_16VK7
@ @ C15 +3VS_SEN 1 12 SENSE_SDA
VSTBY SMDAT4/GPE7 SENSE_SDA [20]
36
23 VSTBY
2 2 2 1 1 VSTBY
0.1U_0402_16VK7
0.1U_0402_16VK7
C11 C12 16
4 VSTBY
VSTBY
2 2 2 2
WRST# 11
WRST#
40 15
41 FSCE#/GPG3 PWM0/GPA0 14
42 FMOSI/GPG4 PWM1/GPA1
FMISO/GPG5 FSPI PWM4/SMCLK5/GPA4
17
44 PWM 19
FSCK/GPG7 PWM5/SMDAT5/GPA5 18
PWM6/SSCK/GPA6
PU 10K 3VS on CPU side
IT8350E
R5222 2 1 0_0402_5% USB20_N7_R
[4,8] SENSOR_HUB_INT#
LQFP-48 UART RXD/SIN0/GPB0
TXD/SOUT0/GPB1
45
46
RXD
TXD
T25
T28
R2110 2 @ 1 0_0402_5%
[9] USB20_N7 Reserved TX/RX for debugging
R2109 2 @ 1 0_0402_5%
[9] USB20_P7
37
1 2 38 GPH5/ID5/DM
+3VS_SEN @ USB20_P7_R
GPH6/ID6/DP USB
27
R45 ADC0/GPI0 28
1.5K_0402_5% ADC1/SMINT0/GPI1 29
6 ADC2/SMINT1/GPI2
PWRSW/GPE4 A/D ADC3/SMINT2/GPI3
30
@ 21 31
R5213 1 2 100K_0402_5% 20 KSI0 ADC4/SMINT3/GPI4 32
5/20 R5213 , R5214 unpop R5214 1 2 100K_0402_5% 26 KSI6 ADC5/GPI5
@ KSI7 GPIO
For Sensor Debug 43
GPG6 R14
39 1 2
3
SSCE0#/GPG2 25 3
KSO17/SMISO/GPC5 100K_0402_5%
SSPI 22
5 KSO16/SMOSI/GPC3
24 VSS
35 VSS
VSS
10 9 CK32KE
VCORE CK32KE/GPJ7 8 CK32K
CK32K/GPJ6
CLOCK
1 Y3 @
0.1U_0402_16VK7
C10 34 2 1
AVSS
32.768KHZ 12.5PF 9H03200031
1
2
IT8350E-128-CX_LQFP48 R2111
SA000076330 0_0402_5% 1 1
C13 @ C1 @
2
22P_0402_50V8J 22P_0402_50V8J
2 2
4 4
Security Classification
2013/07/24
Compal Secret Data
2015/07/24 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
Sensor Fusion
sualaptop365.edu.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B921PR10
Date: Friday, October 17, 2014 Sheet 16 of 36
A B C D E
+3VLP
+3VALW
+3VLP
R188 1 @ 2 0_0603_5% 1@
C179
100P_0402_50V8J
R189 1 2 0_0603_5%
2
L20 +3VALW_EC
FBM-11-160808-601-T_0603 1 1 1 1
+EC_VCCA
0.1U_0402_16VK7
C180
0.1U_0402_16VK7
C181
1000P_0402_50V7K
C182
1000P_0402_50V7K
C183
1 2
+3VALW_EC +EC_VCCA
1 1
C185 @
C184 2 2 @ 2 @ 2
111
125
0.1U_0402_16VK7 1000P_0402_50V7K U11
22
33
96
67
9
1 2 2 ECAGND 2
ESD L21
EC_VDD0
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/AVCC
FBM-11-160808-601-T_0603
PLT_RST# ECAGND
1 21
GATEA20/GPIO00 GPIO0F VCCST_PWRGD [10]
1
ESD@ 2 23 BEEP#
[8] KB_RST# KBRST#/GPIO01 BEEP#/GPIO10 BEEP# [15]
C5268 08/18, change to mount [8] SERIRQ
3
SERIRQ GPIO12
26
100P_0402_50V8J 4 27
[7] LPC_FRAME#
2
EMI
@EMI@ @EMI@
[7] LPC_AD3
[7] LPC_AD2
[7] LPC_AD1
LPC_AD2
LPC_AD1
LPC_AD0
7
8
10
LPC_AD3
LPC_AD2
LPC_AD1
PWM Output
BATT_TEMP/GPIO38
63
64
VCIN1_BATT_TEMP [26]
2 1 R190 2 1 10_0402_1% [7] LPC_AD0 LPC_AD0LPC & MISC GPIO39 65 VCIN1_BATT_DROP [28]
ADP_I/GPIO3A ADP_I [26,27]
C186 22P_0402_50V8J 12 AD Input 66
[6] CK_LPC_KBC 13 CLK_PCI_EC GPIO3B 75
[19,8] PLT_RST# PCIRST#/GPIO05 GPIO42 USB_ID_N [22]
1 2 EC_RST# 37 76 IMON_CPU_R R308 1 @ 2 0_0402_5%
+3VALW_EC R192 47K_0402_5% EC_SCI# 20 EC_RST# IMON/GPIO43 IMON_CPU [32]
[8] EC_SCI# 38 EC_SCII#/GPIO0E
2 [22] DCIN_USB_EN_R GPIO1D 68
DAC_BRIG/GPIO3C
C187 9/30, change net name EN_DFAN1/GPIO3D
70
0.1U_0402_16VK7 DA Output 71 +3VALW
IREF/GPIO3E ROT_BTN# [22]
1
1 @ESD@ KSI0 55 72
56 KSI0/GPIO30 CHGVADJ/GPIO3F EC_WL_OFF# [19]
C188 KSI1
22P_0402_50V8J KSI2 57 KSI1/GPIO31 EC_MUTE# R198 1 @ 2 10K_0402_5% R194
2
42 KSO2/GPIO22 97
R201 KSO3
KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 ENBKL [4] 07/01, Reserve for verify sensor function
1 2 EC_SMB_CK1 KSO4 43 98
44 KSO4/GPIO24 WOL_EN/GPXIOA01 99 VOL_UP# [22]
2.2K_0402_5% KSO5
R202 KSO6 45 KSO5/GPIO25 Int. K/B HDA_SDO/GPXIOA02 109
ME_EN [6]
1 2 EC_SMB_DA1 KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 VCIN0_PH1 [26]
KSO7/GPIO27 SPI Device Interface
2.2K_0402_5% KSO8 47
KSO9 48 KSO8/GPIO28 119 VCIN1_BATT_TEMP 1 2
49 KSO9/GPIO29 SPIDI/GPIO5B 120 EC_SPI_MISO [7]
KSO10 C189 100P_0402_50V8J
KSO10/GPIO2A SPIDO/GPIO5C EC_SPI_MOSI [7]
KSO11 50 SPI Flash ROM 126 VCIN1_AC_IN 1 2
KSO11/GPIO2B SPICLK/GPIO58 EC_SPI_CLK [7]
KSO12 51 128 C190 100P_0402_50V8J
52 KSO12/GPIO2C SPICS#/GPIO5A EC_SPI_CS0# [7] 1 2
KSO13
KSO14 53 KSO13/GPIO2D R203 @ 4.7K_0402_5%
KSO15 54 KSO14/GPIO2E 73 TAB_SW#
KSO15/GPIO2F ENBKL/GPIO40 TAB_SW# [22]
81 74
KSO16/GPIO48 PECI_KB930/GPIO41 SYS_PWROK [4,8]
82 89
KSO17/GPIO49 FSTCHG/GPIO50 90 WLAN_PWR_ON# [19]
BATT_CHG_LED#/GPIO52 BATT_CHG_LED# [22]
91
77 CAPS_LED#/GPIO53 92 CAPS_LED# [23]
EC_SMB_CK1 GPIO
[22,26,27] EC_SMB_CK1 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54 PWR_LED# [22]
TS/ BATTERY/CHARGER EC_SMB_DA1 78 93
[22,26,27] EC_SMB_DA1 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 BATT_LOW_LED# [22]
EC_SMB_CK2 79 SM Bus 95 SYSON
[23,7] EC_SMB_CK2 80 EC_SMB_CK2/GPIO46 SYSON/GPIO56 121 SYSON [24,29]
Thermal IC/ CPU EC_SMB_DA2
[23,7] EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57
PM_SLP_S4#/GPIO59
127
PM_SLP_S5# [8]
ESD
6 100 SYSON
[8] PM_SLP_S3# 14 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 101 EC_RSMRST# [8]
[22] TS_DISABLE# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 HOME_INT# [22]
1
15 102 @ESD@
[28] SPOK 16 EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 103 VCIN1_ADP_PROCHOT [26]
T84 EC_GPIO0A C5269
GPIO0A H_PROCHOT#_EC/GPXIOA06 VCOUT1_PROCHOT# [26] 100P_0402_50V8J
9/25, ATE request add TP to burn in MAC T85 EC_GPIO0B 17 104
VCOUT0_MAIN_PWR_ON [28]
2
18 GPIO0B VCOUT0_PH/GPXIOA07 105 BKOFF#
GPIO0C GPO BKOFF#/GPXIOA08 BKOFF# [20]
19 GPIO 106
[8] AC_PRESENT GPIO0D PBTN_OUT#/GPXIOA09
25 107
[19] PCIE_LAN_WAKE# 28 EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 108
FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11 1.05V_VS_PG_PWR [30]
9/25, ATE request add TP to burn in MAC T86 EC_GPIO15 29
EC_TX 30 EC_PME#/GPIO15
[19] EC_TX 31 EC_TX/GPIO16 110
EC_RX
[19] EC_RX EC_RX/GPIO17 AC_IN/GPXIOD01 VCIN1_AC_IN [24,25,27]
PCH_PWROK 32 112 EC_ON
[8] PCH_PWROK 34 PCH_PWROK/GPIO18 EC_ON/GPXIOD02 114 EC_ON [28]
NOVO# ON/OFF# [22] VCOUT1_PROCHOT# R204 1 2 0_0402_5%
[22] NOVO# SUSP_LED#/GPIO19 ON/OFF/GPXIOD03
36 GPI 115 LID_SW#
NUM_LED#/GPIO1A LID_SW#/GPXIOD04 LID_SW# [22]
1 R207 2 116 SUSP#
SUSP#/GPXIOD05 117 SUSP# [24,29,30,31]
10K_0402_5% NUVOTON_VTT R205 1 2 0_0402_5% H_PROCHOT# [25,4]
GPXIOD06 [32] VR_HOT#
118 PECI 1 2
PECI_KB9012/GPXIOD07 H_PECI [4]
AGND/AGND
1 2 XCLKO/GPIO5E V18R
C192
[8] PM_SLP_S4# 1 1
4.7U_0603_6.3V6K
GND0
R309 @
0_0402_5% C191
47P_0402_50V8J
SA000079Y00 2 2
11
24
35
94
113
69
LID_SW# 1 R206 2
100K_0402_5%
+1.05VS_VTT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BIOS & EC I/O Port
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
sualaptop365.edu.vn
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B921PR10
Date: Friday, October 17, 2014 Sheet 17 of 36
A B C D E F G H
+3VS +3VS_SSD
R17 1 2 0_0805_5%
JSSD1
NGFF_SSD_PRESENT# 1 2
[8] NGFF_SSD_PRESENT# 3 GND VCC 4
5 GND VCC 6
7 GND FULL_CARD_POWER_OFF# 8
9 USB_D+ W_DISABLE# 10
11 USBD- LED1#
GND
12
13 NC 14
15 NC(CONFIG_0) NC 16
17 WAKE_ON_WAN# NC 18
2 DPR W_DISABLE#2 2
19 20
21 GND NC 22
23 NC UIM-RESET 24
25 NC UIM-CLK 26
27 GND UIM-DATA 28
29 NC UIM-PWR 30
NC NC DEVSLP1 [8]
31 32
C1277 1 2 0.01U_0402_16V7K SATA_PRX_DTX_P1_C 33 GND GNSS_SCL 34
[6] SATA_PRX_DTX_P1 NC GNSS_SDA
[6] SATA_PRX_DTX_N1 C1280 1 2 0.01U_0402_16V7K SATA_PRX_DTX_N1_C 35 36
37 NC GNSS_IRQ 38
C1275 1 2 0.01U_0402_16V7K SATA_PTX_DRX_N1_C 39 GND SYS_CLK(GNSS0) 40
[6] SATA_PTX_DRX_N1 NC SYS_CLK(GNSS1)
C1276 1 2 0.01U_0402_16V7K SATA_PTX_DRX_P1_C 41 42
[6] SATA_PTX_DRX_P1 43 NC NC 44
45 GND NC 46
47 NC NC 48
49 NC NC 50
51 GND NC 52
53 ANTCTRL0 COEX3 54
55 ANTCTRL1 COEX2 56
57 ANTCTRL2 COEX1 58
59 ANTCTRL3 SIM DETECT 60
NGFF_SSD_PEDET 61 RESET# NC 62
[6] NGFF_SSD_PEDET GND(CONFIG_1) VCC
63 64
+3VS_SSD 65 GND VCC 66
3 3
67 GND VCC
GND(CONFIG_2)
69 68
GND GND
1 1 1 1
@ LOTES_AP-APCI0133
C1176 C1177 C1178 C1179 ME@
0.01U_0402_16V7K 0.1U_0402_16VK7 10U_0603_6.3V6M 10U_0603_6.3V6M
2 2 2 2
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SSD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B921PR10
Date: Friday, October 17, 2014 Sheet 18 of 36
A B C D E F G H
sualaptop365.edu.vn
A B C D E
+5VALW
L43 EMI@
C1308 U52 W=80mils 1 2 U2DP1
[9] USB20_P1 1 2
0.1U_0402_16VK7 1
1 2 5 OUT
IN 2 [9] USB20_N1 4 3 U2DN1
4 GND 4 3
[17] USB_EN#_R EN 1
3 LPF0805F2SF-900T04_4P
OCB USB_OC0# [9] +
1
C5264 06/30, C5274,C5275 replace to C5264 1
R176 1 @ 2 0_0402_5%
150U_B2_6.3VM_R35M
SY6288D20AAC_SOT23-5
2
08/11, C5264 replace to C5274,C5275 R182 1 @ 2 0_0402_5%
L44 EMI@
1 2 U3RXDN2 +USB_VCCA
[9] USB3_RX2_N 1 2
W=80mils
4 3 U3RXDP2 JUSB1
[9] USB3_RX2_P 4 3 1
DLW21HN900SQ2L_4P U2DN1 2 VBUS
U2DP1 3 D-
R183 1 @ 2 0_0402_5% 4 D+
U3RXDN2 5 GND
@ESD@ D44 R184 1 @ 2 0_0402_5% U3RXDP2 6 StdA-SSRX- 10
U3RXDN2 9 10 StdA-SSRX+ GND
1 1U3RXDN2 D45 @ESD@ 7 11
U2DP1 3 6 C1309 U3TXDN2 8 GND-DRAIN GND 12
I/O2 I/O4 StdA-SSTX- GND
U3RXDP2 8 9 2 2U3RXDP2 0.1U_0402_16VK7 L45 EMI@ U3TXDP2 9 13
+USB_VCCA 1 2 U3TXDN2_L 1 2 U3TXDN2 StdA-SSTX+ GND
[9] USB3_TX2_N 1 2
U3TXDN2 7 7 4 4U3TXDN2 SANTA_375065-1
2 5 ME@
GND VDD
U3TXDP2 6 6 5 5U3TXDP2
[9] USB3_TX2_P
1 2 U3TXDP2_L 4
4 3
3 U3TXDP2
3 3 C1310 DLW21HN900SQ2L_4P
1 4 U2DN1 0.1U_0402_16VK7
8 I/O1 I/O3 R186 1 @ 2 0_0402_5%
AZC099-04S.R7G_SOT23-6
YSCLAMP0524P_SLP2510P8-10-9 Place TX AC coupling Cap (C843~C850). Close to connector
2 2
R1518 1 2 0_0805_5%
ISCT@
+3VS_WLAN +3VALW Q4
AO3413_SOT23-3
JWLAN1 ME@
D
1 2 3 1
USB20_P6 3 GND 3.3VAUX 4
[9] USB20_P6 USB_D+ 3.3VAUX 1 1
USB20_N6 5 6 C1171 C533
[9] USB20_N6 USB_D- LED1#
7 8
G
2
9 GND PCM_CLK 10 4.7U_0603_6.3V6K @ 0.1U_0402_16VK7
SDIO_CLK PCM_SYNC [17] WLAN_PWR_ON# 2 2
11 12 1
13 SDIO_CMD PCM_IN 14 ISCT@ ISCT@
15 SDIO_DAT0 PCM_OUT 16 R436 C526
17 SDIO_DAT1 LED2# 18 150K_0402_5% 0.1U_0402_16VK7
SDIO_DAT2 GND
1
19 20 2
21 SDIO_DAT3 UART_WAKE# 22 R5215
23 SDIO_WAKE# UART_RX
SDIO_RST# 100K_0402_5%
24
2
25 UART_TX 26
27 GND UART_CTS 28
[9] PCIE_PTX_C_DRX_P4 PET_P0 UART_RTS
29 30 R1498 1 2 0_0402_5%
[9] PCIE_PTX_C_DRX_N4 31 PET_N0 RSVD 32 EC_TX [17]
R1499 1 2 0_0402_5%
GND RSVD EC_RX [17]
33 34
[9] PCIE_PRX_DTX_P4 35 PER_P0 RSVD 36
[9] PCIE_PRX_DTX_N4 PER_N0 COEX3
37 38
3
R110 1 2 10K_0402_5% 39 GND COEX2 40 3
+3VALW [6] CLK_PCIE_WLAN REFCLK_P0 COEX1
41 42 SUSCLK_R R1494 1 2 0_0402_5%
[6] CLK_PCIE_WLAN# REFCLK_N0 SUSCLK SUSCLK_WLAN [8]
43 44 WL_RST#
WLAN_CLKREQ# 45 GND PERST0# 46 BT_DISABLE_R R1490 1 2 0_0402_5%
[6,8] WLAN_CLKREQ# CLKREQ0# W_DISABLE2# BT_OFF# [4,8]
[17] PCIE_LAN_WAKE# R57 1 2 0_0402_5% WL_WAKE#_R 47 48 R1492 1 2 0_0402_5%
PEWAKE0# W_DISABLE1# EC_WL_OFF# [17]
49 50
51 GND I2C_DAT 52
RSVD/PET_P1 I2C_CLK
53
RSVD/PET_N1 ALERT
54 Note: The real behavior of BT_DISABLE are
55 56 BT_DISABLE=LOW, BT=OFF
57 GND RSVD 58
59 RSVD/PER_P1 RSVD 60 BT_DISABLE=HIGH, BT=ON
61 RSVD/PER_N1 RSVD 62
63 GND RSVD 64
65 RSVD 3.3VAUX 66
67 RSVD 3.3VAUX +3VS
GND 69
68 GND2 +3VS_WLAN
GND1 BT_DISABLE_R R5227 1 @ 2 10K_0402_5%
LOTES_APCI0114-P001A
1
DC04000IG00 ISCT@ +3VS
07/01, reserve for verify BT function R3822
08/11, JWLAN1 change symbol 100K_0402_5% ISCT@
2
Q2
2N7002K_SOT23-3
G
2
WL_RST# 1 3 PLT_RST# PLT_RST# [17,8]
S
R1493 1 2 0_0402_5%
PLT_RST#
1
4 ESD@ 4
C5274
08/18, ESD REQUEST 100P_0402_50V8J
2
Security Classification
2014/04/10
Compal Secret Data
2017/04/10 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
USB3.0/WLAN
sualaptop365.edu.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B921PR10
Date: Friday, October 17, 2014 Sheet 19 of 36
A B C D E
5 4 3 2 1
+3VS
W=60mils W=60mils R5216 +LCDVDD_CONN R1468 1 2 0_0402_5% DISPOFF# +LEDVDD B+
[17] BKOFF#
U46 0_0603_5%
5 1 +LCDVDD_CONN_R 1 2
IN OUT R1460 1 2 0_0805_5%
4.7U_0603_6.3V6K
2
2 1 1
GND R1467 C1158
C613
1 1
D 4 3 100K_0402_1% 680P_0402_50V7K C1159 D
C614 EN OC @ 4.7U_0805_25V6-K
1500P_0402_50V7K SY6288C20AAC_SOT23-5 2 2
1
2 2
1
3
4 3
R939 R1473 5 4
[16] SENSE_SDA 5
100K_0402_5% 100K_0402_5% Sensor BD 6
[16] SENSE_SCL 6
+3VS 7
2
2
8 7
+3VS_CMOS 8
USB20_P5_R 9
USB20_N5_R 10 9
CMOS 11 10
DMIC_CLK 12 11
[15] DMIC_CLK 12
DMIC [15] DMIC_DAT DMIC_DAT 13
14 13
+3VS 14
1 15
[4] INVPWM 15
DISPOFF# 16
680P_0402_50V7K 17 16
C1160 @ EDP_HPD_R 18 17
2 19 18
+LCDVDD_CONN 19
(60 MIL) 20
21 20
CTL2 1 2 0.1U_0402_16VK7 EDP_AUXN_C 22 21
[4] EDP_AUXN 22
CTL1 1 2 0.1U_0402_16VK7 EDP_AUXP_C 23
[4] EDP_AUXP 23
(20 MIL) +3VS_CMOS 24
+3VS CTL3 1 2 0.1U_0402_16VK7 25 24
EMI eDP [4]
[4]
EDP_TXP0
EDP_TXN0
CTL4 1 2 0.1U_0402_16VK7
EDP_TXP0_C
EDP_TXN0_C 26 25
26
Q70 27
C
CMOS Camera LP2301ALT1G_SOT23-3
R180 1 2 0_0402_5%
[4] EDP_TXP1
CTL10 1
CTL9 1
2 0.1U_0402_16VK7
2 0.1U_0402_16VK7
EDP_TXP1_C
EDP_TXN1_C
28
29
27
28 C
(20 MIL) [4] EDP_TXN1 29
3 1 R1456 1 2 0_0603_5% 10U 30
S
30
1 1
31
C1152 C1153 @ L55 @EMI@ 32 GND
G
2
H_2P4X2P1N
H_3P3 H_3P3 H_3P3 H_2P4X2P1 H_4P0 H_4P0
@ @ @ @
1
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
eDP /DMIC/COMS/HOLE
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
LA-B921PR10
sualaptop365.edu.vn
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, October 17, 2014 Sheet 20 of 36
5 4 3 2 1
5 4 3 2 1
+3VS
2
R1469
+5VS +5VS_HDMI 1M_0402_5% Q74
2
G
2N7002H_SOT23-3
1
UH1
3 1 HDMI_DET
3 [4] DDI2_HDMI_HPD
D
OUT
1 1
IN
1
C1161
D 2 R1472 D
GND 0.1U_0402_16VK7 20K_0402_1%
2
AP2330W-7_SC59-3
2
JHDMI1
19
+5VS_HDMI +5V
HDMIDAT_R 18
HDMICLK_R 17 SDA
16 SCL
15 DDC/CEC_GND
HDMI_CLK-_CK R153 1 @ 2 0_0402_5% HDMI_CLK-_CONN 14 CEC
13 CK-
CPU_DP2_N0 0.1U_0402_16VK7 2 1 C46 HDMI_TX2-_CK HDMI_CLK+_CKR154 1 @ 2 0_0402_5% HDMI_CLK+_CONN 12 CK_Shield
[4] CPU_DP2_N0 CK+
CPU_DP2_P0 0.1U_0402_16VK7 2 1 C47 HDMI_TX2+_CK HDMI_TX0-_CK R167 1 @ 2 0_0402_5% HDMI_TX0-_CONN 11 23
[4] CPU_DP2_P0 D0- GND3
CPU_DP2_N1 0.1U_0402_16VK7 2 1 C48 HDMI_TX1-_CK 10 22
[4] CPU_DP2_N1 D0_Shield GND2
CPU_DP2_P1 0.1U_0402_16VK7 2 1 C55 HDMI_TX1+_CK HDMI_TX0+_CKR168 1 @ 2 0_0402_5% HDMI_TX0+_CONN 9 21
[4] CPU_DP2_P1 D0+ GND1
CPU_DP2_N2 0.1U_0402_16VK7 2 1 C56 HDMI_TX0-_CK HDMI_TX1-_CK R169 1 @ 2 0_0402_5% HDMI_TX1-_CONN 8 20
[4] CPU_DP2_N2 D1- GND0
CPU_DP2_P2 0.1U_0402_16VK7 2 1 C68 HDMI_TX0+_CK 7
[4] CPU_DP2_P2 D1_Shield
CPU_DP2_N3 0.1U_0402_16VK7 2 1 C72 HDMI_CLK-_CK HDMI_TX1+_CKR170 1 @ 2 0_0402_5% HDMI_TX1+_CONN 6
[4] CPU_DP2_N3 D1+
CPU_DP2_P3 0.1U_0402_16VK7 2 1 C74 HDMI_CLK+_CK HDMI_TX2-_CK R171 1 @ 2 0_0402_5% HDMI_TX2-_CONN 5
[4] CPU_DP2_P3 D2-
4
HDMI_TX2+_CK R172 1 @ 2 0_0402_5% HDMI_TX2+_CONN 3 D2_Shield
2 D2+
HDMI_DET 1 Utility
HP_DET
BELLW_SD-WK2013-0168
ME@
C C
+3VS +5VS_HDMI
HDMI_TX2-_CONN 2 8 HDMI_TX2-_CONN
2N7002DW-T/R7_SOT363-6 HDMI_TX1-_CK 7 2
HDMI_TX1+_CK 8 1
DDI2_CTRL_CK 1 6 HDMICLK_R
[4] DDI2_CTRL_CK RP1
3
5
1
HDMI_TX1-_CONN 2 8 HDMI_TX1-_CONN 2
G
HDMI_CLK+_CONN 4 7 HDMI_CLK+_CONN S Q76
3
B L30 EMI@ HDMI_CLK-_CONN 5 6 HDMI_CLK-_CONN 2N7002H_SOT23-3 B
HDMI_CLK+_CK 1 2 HDMI_CLK+_CONN
1 2
HDMI_CLK-_CK 4 3 HDMI_CLK-_CONN 3
4 3
DLW21HN900SQ2L_4P TVWDF1004AD0_DFN9
L31 EMI@
HDMI_TX0+_CK 1 2 HDMI_TX0+_CONN
1 2
HDMI_TX0-_CK 4 3 HDMI_TX0-_CONN
4 3
DLW21HN900SQ2L_4P
D69 @ESD@
L32 EMI@ 6 3 HDMICLK_R
+5VS_HDMI I/O4 I/O2
HDMI_TX1+_CK 1 2 HDMI_TX1+_CONN
1 2
HDMI_TX1-_CK 4 3 HDMI_TX1-_CONN 5 2
4 3 +5VALW VDD GND
DLW21HN900SQ2L_4P
HDMI_TX2-_CK 4 3 HDMI_TX2-_CONN
4 3
Main: SC300001400
DLW21HN900SQ2L_4P 2nd: SC300001G00
A A
sualaptop365.edu.vn
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B921PR10
Date: Friday, October 17, 2014 Sheet 21 of 36
5 4 3 2 1
Lid SW(Tablet Mode)
+3VALW
+3VALW
Touch Panel
1
R47
100K_0402_5%
2
2
3
C1156 1 2 0.1U_0402_16VK7
TAB_SW# JTCH1
VCC
VOUT
TAB_SW# [17]
1 2 +3VS R5207 1 2 0_0402_5% 1
USB20_N4 2 1
[9] USB20_N4 2
C551 C550 [9] USB20_P4 USB20_P4 3
GND
0.1U_0402_16VK7 10P_0402_50V8J R97 1 @ 2 10K_0402_5% 4 3
2 1 +3VS 4
R721 1 2 0_0402_5% TS_DISABLE#_R 5
[17] TS_DISABLE# 6 5
U2904 +3VALW
1
TCS20DLR_SOT23F-3 C1154 1 2 0.1U_0402_16VK7 ECSMB_CK1 7 6
ECSMB_DA1 8 7
9 8
[17] HOME_INT# 9
10
10
+3VALW
11
12 GND
R135 2.2K_0402_5% GND
SD Board
2
1 @ 2 ACES_50208-01001-001
+3VALW
ME@
6 1 ECSMB_CK1
[17,26,27] EC_SMB_CK1
2N7002KDWH_SOT363-6
Q2419A R136 2.2K_0402_5%
5
1 @ 2
+3VALW
TS side have PU 10K 3.3V
+3VS 3 4 ECSMB_DA1
[17,26,27] EC_SMB_DA1
JSD1 ME@
R5208 1 2 0_0402_5% +3VS_SD 6 8 2N7002KDWH_SOT363-6
5 6 GND 7 Q2419B
4 5 GND
[9] USB20_N3 3 4
[9] USB20_P3 3
2
1 2
1
JXT_FP241AH-006GAAM
08/11, JSD1 change to 6pin, add one power and gnd pin
EMI
1
1 2 USB20_N0_R
[9] USB20_N0 1 2
USB_ID_N USB_ID_N [17]
4 3 USB20_P0_R
[9] USB20_P0 4 3
D
1
LPF0805F2SF-900T04_4P
R5221 1 2 0_0402_5% 2 Q2421
[25] USB_ID
G 2N7002K_SOT23-3 R174 1 @ 2 0_0402_5%
S
3
+USB_VCCA
C1306
0.1U_0402_16VK7
1 1
For DCIN-USB Combo port only 1 8 ON/OFF# @ W=120mils
2 7 ROT_BTN# C5273
2A/Active High 3 6 VOL_UP# @ 47U_0805_6.3V6M JIO1
+5VALW 4 5 VOL_DOWN#_R 2 2 24
+VUSB 24
08/21, C5273 change to unpop 23
C5266 100K_0804_8P4R_5% USB20_N0_R 22 23
USB20_P0_R 21 22
0.1U_0402_16VK7 U2905 W=80mils 21
1 2 5 1 20 26
IN OUT +3VLP 20 GND2
06/30, C5276,C5277 replace to C5267 19
19 GND1
25
2 [17] PWR_LED# 18
GND 17 18
1 [17] BATT_CHG_LED# 17
2
R5218 1 2 0_0402_5% VUSB_OPEN_R 4 3
USB_OC1# [9]
16
[25] VUSB_OPEN EN OC + [17] BATT_LOW_LED# 16
C5267 R1592 NOVO# 15
[17] NOVO# 15
R5228 1 @ 2 0_0402_5% SY6288C20AAC_SOT23-5 100K_0402_5% ROT_BTN# 14
[17] DCIN_USB_EN_R [17] ROT_BTN# 14
150U_B2_6.3VM_R35M
VOL_UP# 13
2 [17] VOL_UP# 13
R5229 1 2 0_0402_5%
DCIN_USB_EN [25] R5226 1 2 0_0402_5% VOL_DOWN#_R 12
[17] VOL_DOWN#
1
12
08/11, C5267 replace to C5276,C5277 [17] ON/OFF#
ON/OFF# 11
11
1
NOVO# LID_SW# 10
[17] LID_SW# 9 10
R5230 VL 9
@ 07/01, Reserve for verify sensor function +5VALW 8
100K_0402_5% 7 8
+3VALW 7
9/30, Reserve for EC control path [15] PLUG_IN# PLUG_IN# 6
2
5 6
[15] HP_OUTR_R 5
06/30, Add L56(COM choke), R5223, 4
4
R5224 to connect JDCIN1 3
[15] HP_OUTL_R 40 mils 3
2
[15] EXT_MIC_RING2_R 2
40 mils 1
[15] EXT_MIC_SLEEVE_R 1
E-T_6718K-Y24N-20L
R5223 1 @ 2 0_0402_5% ME@
L56 EMI@
1 4
1 4
[9] USB20_P2 USB20_P2_R [25]
2 3
2 3
[9] USB20_N2 USB20_N2_R [25]
TAIYO_MCF12102G900-T_4P
R5224 1 @ 2 0_0402_5%
AC to DC S0
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/04/10 Deciphered Date 2017/04/10 Title
When EC get USB_ID_N L--> H, then
DCIN_USB_EN need delay 2's then L-->H THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
IO BD/ SD BD/TOUCH/LED/LID
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
sualaptop365.edu.vn
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B921PR10
Date: Thursday, October 23, 2014 Sheet 22 of 36
5 4 3 2 1
JKB1
KSI[0..7] R94 1 2 470_0402_5% +3VS_CAPLED 1
KSI[0..7] [17] +3VS 1
CAPS_LED# 2
D KSO[0..15] [17] CAPS_LED# 2 D
KSO[0..15] [17] KSI7 3
+3VS KSI6 4 3
KSI5 5 4
Close to U99 KSI4 6 5
U99 KSI3 7 6
1 8 EC_SMB_CK2 KSI2 8 7
1 VDD SCL EC_SMB_CK2 [17,7] 8
KSI1 9
C587
2200P_0402_50V7K
2
REMOTE1+
REMOTE1-
2
3
D+ SDA
7
6
EC_SMB_DA2
EC_SMB_DA2 [17,7] ESD KSI0
KSO15
KSO14
10
11
12
9
10
11
D- ALERT# CAPS_LED# 12
KSO13 13
1 @ 2 4 5 KSO12 14 13
+3VS T_CRIT# GND
1
R335 @ESD@ KSO11 15 14
4.7K_0402_5% C5270 KSO10 16 15
NCT7718W_MSOP8 100P_0402_50V8J KSO9 17 16
2
KSO8 18 17
KSO7 19 18
SMBus address: 1001100x 19
REMOTE1+/-: KSO6
KSO5
20
21 20
21
Trace width/space:10/10 mil KSO4 22
23 22
KSO3
Trace length:<8" KSO2 24 23
24 GND0
28
KSO1 25 27
KSO0 26 25 GND1
26
ACES_50519-02601-001
REMOTE1+
Close to DDR ME@
C 1 C
1
C
@ C1210 2 Q79
100P_0402_50V8J B MMST3904-7-F_SOT323-3
2 E
3
REMOTE1-
Click Pad
C1301
0.1U_0402_16VK7
+3VS
JTP1 ME@
B B
1
R1600 1 2 0_0402_5% TP_CLK 2 1
[8] I2C1_SCL_TP 2
R1601 1 2 0_0402_5% TP_DATA 3
[8] I2C1_SDA_TP 3
1 1 TP_INT_N 4
5 4
@ C1302 C1303 @ 6 5
10P_0402_50V8J 10P_0402_50V8J 6
+3VS 2 2 7
GND
3
8
D42 GND
1
AZ5125-02S.R7G_SOT23-3 ACES_88514-00601-071
R5209 @ESD@ SP010014M00
10K_0402_5%
SCA00001A00
1
2
A A
sualaptop365.edu.vn
A B C D E
+5VALW TO +5VS
+3VALW TO +3VS
1 1
5/20 Change to SA00006FD00 +3VALW +3VS
C2307
10U_0603_6.3V6M
C2308
0.1U_0402_16VK7
C2322 @ JUMP_43X79 R435 1 2 0_0805_5%
3 12 1 2 470P_0402_50V7K 1 1
[17,29,30,31] SUSP# ON1 CT1
+5VALW 4 11 @
VBIAS GND C2309
5 10 1 2 220P_0402_50V7K 2 2
06/30, U2301.4 change power rail ON2 CT2
from VL to +5VALW 6 9 5VS
+5VALW 7 VIN2 VOUT2 8
VIN2 VOUT2
15 +5VS
GPAD
APE8990GN3B DFN 14P J511
2 1
2 1
C2324
10U_0603_6.3V6M
C2323
0.1U_0402_16VK7
@ JUMP_43X79
1 1
+3VALW +5VALW
@
2 2
C2318
10U_0603_6.3V6M
C2305
10U_0603_6.3V6M
0.1U_0402_16VK7
0.1U_0402_16VK7
1 1 1 1
C2316
C2306
2 2
@ @
2 2 2 2
+0.675VS +1.05VS_VTT
+5VALW
1
1
R627 R628
@ @
1
470_0402_5% 470_0402_5%
2
@ R620 2
100K_0402_5% Use for panel sequence
2
SUSP
D
1
3 3
SUSP# 2
G
Q45
SSM3K7002BFU_SC70-3
B+ dischager
1
Q47 D Q48 D
S
3
1
@ SUSP 2 @ SUSP 2 @
R622 G G
10K_0402_5% S S
3
SSM3K7002BFU_SC70-3 SSM3K7002BFU_SC70-3
@
2
+RTCBATT
B+
1
+5VALW +3VS
1
+1.35V R1519 @
470_0805_5%
@ R624
1
100K_0402_5%
2
1
R629
2
1
@ VCIN1_AC_IN#
@ R619 470_0402_5% R5206 @
3
100K_0402_5% 10_0603_5% Q2420B
2
Q2420A @
2
SYSON# @ 2N7002DW-T/R7_SOT363-6
2
2 VCIN1_AC_IN# 5
[17,25,27] VCIN1_AC_IN
6
Q44B
Q44A @ 2N7002DW-T/R7_SOT363-6
4
@ 2N7002DW-T/R7_SOT363-6
2 SYSON# 5
[17,29] SYSON D
1
Q49
2N7002DW-T/R7_SOT363-6 SUSP 2 @
1
4
1
4 G 4
R621 S
3
10K_0402_5% @ SSM3K7002BFU_SC70-3
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC V TO VS INTERFACE
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B921PR10
Date: Friday, October 17, 2014 Sheet 24 of 36
A B C D E
sualaptop365.edu.vn
5 4 3 2 1
JDCIN1
1
2 1
3 2
4 3
5 4
6 5
7 GND
GND CONN@ PF101
7A_24VDC_429007.WRML EMI@ PL101
ACES_50278-00501-001 HCB2012KF-121T50_0805
APDIN 1 2 APDIN1 1 2
10U_0603_25V6M 2.2_0603_5%
2
D D
USB_ID EMI
1000P_0402_50V7K
1000P_0402_50V7K
USB_ID [22]
100P_0402_50V8J
100P_0402_50V8J
PR110
USB20_P2_R [22]
470K_0402_5%
1
2
EMI@ PC101
EMI@ PC102
EMI@ PC103
EMI@ PC104
@
USB20_N2_R [22]
PR111
2
1
PC111
1
2
@
VIN PQ101
AON7405_DFN8-5
PQ102
AON7405_DFN8-5
PQ103
AON7405_DFN8-5 +VUSB
1 1 1
2 2 2
5 3 3 5 3 5
200K_0402_1%
0.1U_0402_25V6
2
4
4
1
PR102
PC106
470K_0402_1%
0.47U_0402_25V5K
2
2
1
PC107
PR103
1
1
200K_0402_1%
2
C C
PR104
+3VALW
100K_0402_1%
1
2
PR105
VUSB_OPEN1
200K_0402_1%
1
6
2
PR106
2N7002KDW-2N_SOT363-6
PQ104A
USB_ID 2 2N7002KDW-2N_SOT363-6
PQ104B
0.1U_0402_25V6
DCIN_USB_EN
1
200K_0402_1%
1
3
1
PC108
PJDLC05C 3P C/A SOT23
PD105
PR107
5 VUSB_OPEN
0.1U_0402_25V6
4
ESD@
1
PC112
PD103
1
SCA00001100
3 VUSB_OPEN1
2
[22] VUSB_OPEN 1
2 DCIN_USB_EN [22]
BAT54AW-L_SOT323-3
B B
+5VS
+3VALW
1 2
+RTCBATT +3VLP
47K_0402_1%
2
@9012@
[17,4] H_PROCHOT#
10K_0402_1%
PR108
@9012@ PR109
PD102
RB751V-40_SOD323-2
8
@9012@ PC109
1
D
1
0.022U_0402_16V7K 5
P
@9012@ PQ105 2 2 1 7 +
O
2
+5VS VCIN1_AC_IN [17,24,27]
100K_0402_1%
100P_0402_50V8J
6
1N4148WS-7-F_SOD323-2
2N7002KW_SOT323-3 G
-
1
S
3
1.5M_0402_5%
@9012@ PR112
@9012@ PU101B
@9012@ PC110
AS393MTR-E1 SO 8P OP
2
@9012@ PD104
@9012@ PR113
1
8
3
P
1
1 +
O 2
-
G
@9012@ PU101A
4
AS393MTR-E1 SO 8P OP
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-DCIN / Vin Detector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
sualaptop365.edu.vn
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
YOGA Paganini
Date: Friday, October 17, 2014 Sheet 25 of 36
5 4 3 2 1
5 4 3 2 1
PR209 PH201 under CPU botten side : 65W(UMA): 85W active W recovery
100_0402_1%
EC_SMDA 1 2 CPU thermal protection at 93 +-3 degree C 20120314
EC_SMB_DA1 [17,22,27]
PR208 Recovery at 56 +-3 degree C Change to +EC_VCCA from +3VLP
100_0402_1%
EC_SMCA 1 2
EC_SMB_CK1 [17,22,27] A/D
TS 1 2
PR201 +3VLP
6.49K_0402_1%
D D
1 2
PR206 +3VALW
@ 6.49K_0402_1%
1 2
ACES_50458-00801-001 VCIN1_BATT_TEMP [17] [17,27] ADP_I
1
PR207
10K_0402_5%
+EC_VCCA
1 2
2
2 3
3 4
VMB
16.5K_0402_1%
PF201 PR202
4 5 7A_24VDC_429007.WRML EMI@ PL201 8.45K_0402_1%
5 6
PR203
HCB2012KF-121T50_0805
+RTCBATT
1
6 7
7 8
1 2 1 2 BATT+ [17] VCIN1_ADP_PROCHOT
EMI@ PL202
2
8 9 HCB2012KF-121T50_0805
GND 10 1 2
GND
2
[17] VCIN0_PH1
VMB2
100K_0402_1%_TSM0B104F4251RZ
JBATT1 PR204
2
CONN@ @ 100K_0402_1%
1
PC201 EMI@ PC202 EMI@ PR205
1
1000P_0402_50V7K 0.01U_0402_25V7K 100K_0402_1%
2
[17] VCOUT1_PROCHOT#
PH201
1
2
C C
ECAGND
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-BATTERY CONN/OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
sualaptop365.edu.vn
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
YOGA Paganini
Date: Friday, October 17, 2014 Sheet 26 of 36
5 4 3 2 1
5 4 3 2 1
D D
BATT+ BAT_B+
VIN PQ301
P1 P2 P3
AON7430L_DFN8-5 PQ305 PR301 EMI@ PL301
1 AON7430L_DFN8-5 0.01_1206_1% 1UH_PHI25201B-1R0MS_1.8A_20% PQ302
2 1 1 4 1 2 H/MOS AON7405_DFN8-5
2200P_0402_50V7K
5 3 2 1
Rds(on)= 24m ohm(typ), 30m ohm(Max.)
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
3 5 2 3 5 2
0.1U_0402_25V6
2200P_0402_50V7K
3
1
1
0_0402_5%
0.1U_0402_25V6
PC323
PC322
PC304
PC305
L/MOS
4
1
@EMI@ PC302
EMI@ PC303
PC306
PR302
PC301
4
PC307 power loss= 0.3396W
2
2
2
0.1U_0402_25V6 Pd of Choke = 0.9892W
2
1
@ 1 2
PD301 PR303
0.1U_0402_25V6
0.1U_0402_25V6
RB751V-40_SOD323-2 4.12K_0603_1%
1
B+
CHGR_BATDRV2
1
1
PC308
PC309
PC310
2 0.047U_0402_25V7K
2
1 2
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
2.2_0402_1%
4.12K_0603_1%
4.12K_0603_1%
1
5
PD302
10_1206_1%
1
1
PC311
PC312
PC324
PC325
PR307
RB751V-40_SOD323-2
PR305
PR304
PR306
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
1
1
@EMI@ PC330
@EMI@ PC329
@EMI@ PC328
2
2
C @ @ C
PR308
2
2
CHGR_DH 1 2 4
2
0_0402_5%
CHGR_BST
1 2 PQ303
CHG_REGN
CHGR_DH
CHGR_LX
AON7408L 1N_DFN8-5
PC313 PC314 PL302 PR309
3
2
1
1U_0603_25V6K 1 2 2.2UH_PCMB061H-2R2MS_6A_20% 0.01_1206_1%
CHGR_LX 1 2 1 4
1U_0603_25V6K
1
2 3
20
19
18
17
16
PR310 @EMI@
VCC
PHASE
HIDRV
BTST
REGN
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
10U_0603_25V6M
21 4.7_1206_5%
PAD
1CHGR_SNB 2
1
PC315
PC316
PC326
PC327
CHGR_ACN 1 15 CHGR_DL 4
ACN LODRV
PU301 PQ304
2
CHGR_ACP 2 BQ24715RGRR_QFN20_3P5x3P5 14 AON7752_DFN8-5 @ @
ACP GND
3
2
1
CHGR_CMSRC 3 13 CHGR_SRP
CMSRC SRP PC317 @EMI@
680P_0402_50V7K
2
CHGR_ACDRV 4 12 CHGR_SRN
ACDRV SRN
5 11 CHGR_BATDRV
[17,24,25] VCIN1_AC_IN ACOK /BATDRV
ACDET
PR311 CELL
IOUT
SDA
SCL
1 2
CHG_REGN
1
100K_0402_5%
1
B PC318 B
6
10
PR312 0.1U_0402_25V6
2
120K_0402_5%
CHGR_CELL
CHGR_ACDET
0.1U_0402_25V6
CHGR_IOUT
CHGR_SDA
CHGR_SCL
2
1
Cell PIN
PC319
@ PR313
Vin Dectector 10K_0402_5%
Float: 2cell
VIN 1 2
+3VALW High:3cell
2
GND: disable LEARN
Min. Typ Max. @ PR315
1
0_0402_5%
L-->H 17.578V 17.755V 17.933V 1 2
EC_SMB_CK1 [17,22,26]
1
PR314
H-->L 17.023V 17.349V 17.674V 270K +-1% 0402 @ PR317
0_0402_5%
2
1 2
EC_SMB_DA1 [17,22,26]
@ PR316
1
0_0402_5%
1
PC320 PR318
.047U 16V K X7R 0402 42.2K +-1% 0402 ADP_I [17,26]
2
1
2
PC321
100P 25V J NPO 0402
2
pacement near EC
A A
sualaptop365.edu.vn
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
YOGA Paganini 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, October 17, 2014 Sheet 27 of 36
5 4 3 2 1
A B C D E
56.2K_0402_1%
1
PR401
PR412
499K_0402_1%
ENLDO_3V5V 1 2
3.3V LDO 150mA~300mA B+
1
150K_0402_1%
PU401 PC401 PR403
B+
2
1
PR402
EMI@ PL401 7 1 3V5V_EN 0.01U_0402_25V7K 1K_0402_5% EMI@
HCB2012KF-121T50_0805 EN2 EN1 1 2 1 2 PC429
2200P_0402_50V7K
1 2 3V_VIN 8 3 3V_FB 1000P_0402_50V7K VCIN1_BATT_DROP [17]
2
IN FB PR404 PC404
2
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
6 1
BST_3V 2 1 2
BS
1
10K_0402_1%
PC406
C406
2.2_0603_5%
1
@EMI@ PC402
PC403
PC405
0.1U_0402_25V6
0.1U_0603_25V7K PL404
PR413
@
@P 1.5UH_FDSD0518H-1R5M_6.2A_20%
2
2
EMI@
PC427
10 LX_3V 1 2
LX +3VALWP
2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
9 4
2
GND OUT
1
@EMI@ PR405
4.7_0805_5%
@
1
PC407
PC408
PC409
PC410
2 5
[17] SPOK PG LDO +3VLP
1
SYX196BQNC_QFN10_3X3
2
2
PC411
1 3V_SN2
PR414 4.7U_0603_6.3V6M
2
Check pull up resistor of SPOK at HW side 100K_0402_5%
680P_0603_50V7K
+3VLP 1
@EMI@ PC412
2
2 2
PR406
2.2K_0402_5%
Vout is 3.234V~3.366V
1 2
[17] EC_ON PR407 TDC=6A
0_0402_5%
1 2
[17] VCOUT0_MAIN_PWR_ON @ PJ401
+3VALWP 1 2 +3VALW
1 2
JUMP_43X118
3V5V_EN
1M_0402_1%
4.7U_0402_6.3V6M
1
1
PR408
PC413
EMI@
PC428
1000P_0402_50V7K EN1 and EN2 dont't floating
2
2
2
B+ EMI@ PL402
HCB2012KF-121T50_0805
1 2 5V_VIN
Vout is 4.998V~5.202V
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
8
PU402
1 3V5V_EN
PC414
PR409
6800P_0402_25V7K 1K_0402_5%
TDC=6A
IN EN 1 2 1 2
1
1
PC416
PC417
C417
EMI@ PC418
@EMI@ PC415
BS
PL403
1.5UH_FDSD0518H-1R5M_6.2A_20%
9 10 LX_5V 1 2 +5VALWP
GND LX
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
VCC_3.3V 5 4
VCC OUT
1
@EMI@ PR411
680P_0603_50V7K 4.7_0805_5%
1
PC421
PC422
PC423
PC424
2 7
PG LDO VL
1
PC420
4.7U_0603_6.3V6M
SYX196C1QNC_QFN10_3X3
2
1 5V_SN
@ PJ402
2
2
1
PC425
1 2
4.7U_0603_6.3V6M
+5VALWP 1 2 +5VALW
JUMP_43X118
2
@EMI@ PC426
2
SYX196C_V4.mdd
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-3VALW/5VALW
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D YOGA Paganini
sualaptop365.edu.vn DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, October 17, 2014 Sheet 28 of 36
A B C D E
5 4 3 2 1
D D
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
+1.35VP
1
1
@EMI@ PC501
EMI@ PC502
PC503
PC504
DH_1.35V +0.675VSP
2
2 SW _1.35V
10U_0805_6.3V6K
10U_0805_6.3V6K
1
1
PC505
PC506
PC507
0.1U_0603_25V7K
16
17
18
19
20
2
C PU501 C
2
PHASE
VLDOIN
UGATE
BOOT
VTT
21
PAD
DL_1.35V 15 1
PQ501 LGATE VTTGND
4
1
AON7934_DFN3X3A8-10
14 2
D1
D1
D1
G1
PL502 PR502 PGND VTTSNS
1UH_FDSD0518H-1R0M_5.2A_20% 8.45K_0402_1%
+1.35VP 1 2 10
D1 D2/S1
9 1 2 CS_1.35V 13
CS GND
3
PC508 RT8207PGQW _W QFN20_3X3
1
1U_0603_10V6K
1 2 12 4 VTTREF_1.35V
G2
S2
S2
S2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1 2 VDD_1.35V 11 5
+5VALW +1.35VP
1 2
VDD VDDQ
1
1
PGOOD
PC519
PC515
PC516
PC517
PC518
PC520
PC509
TON
1
@EMI@ PC511 0.033U_0402_16V7K
FB
S5
S3
2
2
@ @ 680P_0402_50V7K PC512
+5VALW
2
1U_0603_10V6K
10
6
FB_1.35V
EN_0.675VSP
TON_1.35V
EN_1.35V
PR506
8.06K_0402_1%
PR507 1 2 +1.35VP
470K_0402_1%
B 1.35V_B+ 1 2 B
1
H/S Rds(on): 12.4mohm(Typ), 15.8mohm(Max)
Idsm: 13A@Ta=25C, 7.8A@Ta=70C PR509 PR508
0_0402_5% 10K_0402_1%
1 2
[17,24] SYSON
2
L/S Rds(on): 9.1mohm(Typ), 11.6mohm(Max)
Idsm: 15A@Ta=25C, 9A@Ta=70C
1
@ PC513
0.1U_0402_10V7K
Choke: 5x5x1.8
2
Rdc=16mohm(Typ), 19mohm(Max)
PR510
0_0402_5%
Switching Frequency: 520kHz 1 2 @ PJ501
Ipeak=2.52A [4] DDR_VTT_PG_CTRL +1.35VP 1 2 +1.35V
@ PR511 1 2
Iocp~7.5A 0_0402_5% JUMP_43X118
OVP: 110%~120% 1 2
VFB=0.75V, Vout=1.35V [17,24,30,31] SUSP#
1
MOSFET footprint:AON7934_DFN3X3A8-10 @ PC514
0.1U_0402_10V7K
2
@ PJ502
1 2
+0.675VSP 1 2 +0.675VS
A
JUMP_43X39 A
D D
1
@ PC601
1M_0402_1%
0.22U_0402_10V6K
2
PR602
2
@EMI@ PR603 @EMI@ PC602
4.7_0805_5% 680P_0603_50V7K
EMI@ PL601 1 2 SNB_1.05V
1 2 +1.05VSP PJ601
HCB2012KF-121T50_0805 PU601 1 2
1 2 +1.05VS_VTT
B+ 1 2 B+_1.05V 8
IN EN
1 PR604 PC603
2.2_0603_5% 0.1U_0603_25V7K JUMP_43X118 @
10U_0805_25V6K
10U_0805_25V6K
6 1
BST_1.05V 2 1 2 PL602
0.1U_0402_25V6
2200P_0402_50V7K
BS
1
1UH_FDSD0518H-1R0M_5.2A_20%
PC605
PC606
PC607
LDO_3V 9 10 LX_1.05V 1 2
+1.05VSP
PC604
GND LX
@EMI@
2
2
EMI@
15K_0402_1%
47U_0805_6.3V6M
47U_0805_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1
330P_0402_50V7K
1
1
4
PR606
PC612
FB
PR605
Rup
PC608
PC609
PC610
PC611
0_0402_5% ILMT_1.05V 3 7
+3VALW
2
ILMT BYP
2
2
4.7U_0603_6.3V6K
ILMT_1.05V
+3VS 1 2 +1.05V_PGOOD 2 5 LDO_3V
4.7U_0603_6.3V6K
PG LDO
1
PR607
PC614
1
10K_0402_5% SYX196DQNC_QFN10_3X3
PC613
FB = 0.6V
2
1
PR608 @
2
0_0402_5% PR609
Rdown
2
20K_0402_1%
2
[17] 1.05V_VS_PG_PWR
Pin 7 BYP is for CS.
B
The current limit is set to 6A, 9A or 12A when this pin Common NB can delete +3VALW and PC15 B
is pull low, floating or pull high
VFB=0.6V
Vout=0.6V* (1+Rup/Rdown)
Vout=1.05V
A A
sualaptop365.edu.vn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C YOGA Paganini 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, October 17, 2014 Sheet 30 of 36
5 4 3 2 1
5 4 3 2 1
D D
+3VALW +5VALW
2
JUMP_43X39
1
PJ703
PC701
2
1U_0402_6.3V6K
2
1
@
1
PU701
APL5930KAI-TRG_SO8
1
C PC702 6 C
4.7U_0603_6.3V6K 5 VCNTL 3
PR701 9 VIN VOUT 4 @ PJ702
+1.5VSP
2
100K_0402_5% VIN VOUT 1 2
+1.5VSP 1 2 +1.5VS
1
1 2 8
1.54K_0402_1%
0.01U_0402_25V7K
[17,24,29,30] SUSP# 7 EN
1
1 2 2 JUMP_43X39
+3VS
GND
POK FB
PR703
PC703
22U_0603_6.3V6M
1
1
@ PR702 Rup
0.1U_0402_16V7K
1
PC704
PR704 100K_0402_5%
PC705
47K_0402_5%
2
2
1.74K_0402_1%
PR705
Rdown
2
Vout=0.8V* (1+Rup/Rdown)
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-1.5VS
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom YOGA Paganini 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, October 17, 2014 Sheet 31 of 36
5 4 3 2 1
sualaptop365.edu.vn
5 4 3 2 1
Loadline=-2.0mv/A Note
Choke: 0.22UH (Size:7*7*1.8)
PR820 1.27K Ohm OCP Rdc=4.3m ohm +-5%
Heat Rating Current=14A
+1.05VS_VTT Follow intel guideline
PR801 130_0402_1% PR816 909 Ohm Droop
1 2
PC817 @ RC Filter
[10] VR_SVID_DAT
Note:
VR_SVID_ALRT# Pull high on HW side
[10] VR_SVID_ALRT# CPU_B+
EMI@ PL801 B+
HCB2012KF-121T50_0805
CPU_B+ 1 2
2200P_0402_50V7K
10U_0603_25V6M
0.1U_0402_25V6
[10] VR_SVID_CLK PR803 Note:
10U_0603_25V6M
73.2K_0402_1%
PR803=73.2K
100U_D2_16VM_R50M
@EMI@ PC804
EMI@ PC805
1 2 1
1
C C
=>Icc(max)=18A
PC802
PC803
PC806
VR_SVID_ALRT#
+
fsw=700KHz
VR_SVID_DAT
VR_SVID_CLK
[10] VR_ON
2
2
PRGM1
PR804
1.5K_0402_1% PR805
1 2 0_0603_5%
PQ801
1 2
6
21
20
19
18
17
PU801 7 G2
[10] VGATE S1/D2 5
SCLK
SDA
PAD
ALERT#
PRGM1
1 S2
[17] IMON_CPU G1 4
PC807 VR_ON 1 16 LAGTE 2 S2
1000P_0402_50V7K VR_ON LGATE D1 3
1 2 S2
2 15 PHASE
PR806 PGOOD PHASE AON6932A_DFN5X6-8-7
Note: 102K_0402_1%
1 2 IMON_CPU 3 14 UAGTE
VR_HOT# Pull high on HW side IMON UGATE PR807 PC808 PL802
ISL95813HRZ-T_QFN20_3X4 2.2_0603_5% 0.22U_0603_16V7K 0.22UH_PCMB061H-R22MS4R305_14A_20%
[17] VR_HOT# 4 13 BOOT 1 2 1 2 1 2
PH801 VR_HOT# BOOT
+CPU_CORE
47P_0402_50V8J
3.83K_0402_1%
680P_0603_50V7K 4.7_0805_5%
@EMI@ PC811 @EMI@ PR810
PR809 COMP 6 11 PRGM2
2
COMP PRGM2
1
27.4K_0402_1%
ISUMN
ISUMP
1
124K_0402_1% 0.1U_0402_25V6
FB
2
1 PR812
Pin5 (NTC) voltage <0.88V, Protect
PR811
B 3.65K_0603_1% B
7
10
2
Pin5 (NTC) voltage >0.92v, recovery
3.65K_0402_1%
2
1
1
2
FB Note:
ISUMN
ISUMP
PR813
PR512=124K
2
33P_0402_50V8J
1
6800P_0402_25V7K
PC812
10_0402_1%
=>Slew rate=53mV/us
2
PR815
Vboot = 1.7V
2
1
909_0402_1%
PC813
@
PR816
2
1
390P_0402_50V7K
4.99M_0402_1%
1
PR818
2
PC815
PR817
2.61K_0402_1%
RC Match
2
Droop
2
@ @
2
1
PC816 PC817 @ PR819
0.047U_0402_25V7K 0.1U_0402_16V4Z 11K_0402_1%
2
1
[10] VCCSENSE
PH802
10K_0402_5%_B25/50 4250K
@ PC818
2
0.082U_0402_16V7K
1 2 OCP Setting
PC819
330P_0402_50V7K
1
PR820
1 2
A A
@
2
PC820 1.27K_0402_1%
1 2
0.01U_0402_50V7K
@ PC821 @ PR821
1 2 1 2
[12] VSSSENSE Compal Electronics, Inc.
4700P_0402_25V7K 1.5K_0402_1% Title
5 4 3 2 1
5 4 3 2 1
D 30 X 22uF 0805 D
2012/10/23
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
check the output cap Qty!!!
1
2012/10/24
1
PC901
PC902
PC903
PC904
PC905
PC906
PC907
PC908
PC909
PC910
23 pcs 22uF and reserve 7 pcs
2013/01/14
2
2
22uF*15; reserve 22uF*5
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
PC911
PC912
PC913
PC914
PC915
PC916
PC917
PC918
PC919
PC920
2
2
C C
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
PC921
PC922
PC923
PC924
PC925
PC926
PC927
PC928
PC929
2
B B
A A
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DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS YOGA Paganini 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Friday, October 17, 2014 Sheet 33 of 36
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-PIR
sualaptop365.edu.vn AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
YOGA Paganini
Date: Friday, October 17, 2014 Sheet 34 of 36
5 4 3 2 1
5 4 3 2 1
ME Request P.20 H1,H2,H3 footprint change to H_3P3, Delete H6 2014-06-30 EVT-DVT Pass
1
EMI request, for DCIN-USB port USB signal P.22 Add L56(COM choke), R5223, R5224 to connect JDCIN1 2014-06-30 EVT-DVT EA Pass
D
2 D
EMI request P.15 CA32 replace to RA21, CA33 replace to RA24, CA34 replace to RA25 2014-06-30 EVT-DVT Pass
3
4 EMI request P.10 Reserve RC152 connect to JC1 2014-06-30 EVT-DVT Pass
5 For fine tune I2C interface driving P.8 RC130~RC133 change value to 2.2K ohm 2014-06-30 EVT-DVT EA Pass
P.19 C5274,C5275 replace to C5264 2014-06-30 EVT-DVT EA Pass
6 For ME Z-height limitation
For ME Z-height limitation P.22 C5276,C5277 replace to C5267, C5273 change to mount 2014-06-30 EVT-DVT EA Pass
7
For S5 power saving P.24 U2301.4 change power rail from VL to +5VALW 2014-06-30 EVT-DVT Pass
8
Reserve path for verify sensor function P.22 Add 0 ohm R5226 to connect JIO1.12 and U11.85 2014-07-01 EVT-DVT
9 Pass
Reserve path for verify sensor function P.17 Add 0 ohm R5225 to connect U52.4 and U11.84 2014-07-01 EVT-DVT
10 Pass
Reserve path for verify BT function P.19 Add PU R5227 to connect BT_DISABLE_R and +3VS 2014-07-01 EVT-DVT
C
11 Pass C
Follow Intel design guide layout Voiding the GND plane underneath the SATA signals pad of JSSD1 2014-07-01 EVT-DVT EA Pass
12
Item Reason for change PG# Modify List Date Phase Verify
Z-high impact for thermal plate P.11 CC49(22U)(0603) change to 10U*2(CC49,CC100)(0402) 2014-08-13 DVT-PVT Pass
1
Z-high impact for thermal plate P.10 CC26, CC27, CC28, CC30 change to 0402 type 2014-08-13 DVT-PVT Pass
2
Reserve for Intel request P.13 ADD CD54, CD55, CD72, CD73 connect to +0.675VS 2014-08-13 DVT-PVT
3 P.14
P.13
4 Reserve for Intel request P.14 ADD CD56~CD71,CD74~CD87 connect to +1.35V 2014-08-13 DVT-PVT
5 Reserve For EMI request P.15 ADD CA35 connect to DMIC_CLK 2014-08-13 DVT-PVT
P.19
C5264 replace to C5274,C5275; C5267 replace to C5276,C5277 2014-08-13 DVT-PVT Pass
6 solve plug in/out USB device auto shutdown issue P.22
For EMI/Audio request, solve audio noise issue P.15 CA32, CA33, CA34 change to RA41, RA42, RA43 2014-08-13 DVT-PVT Pass
7
B B
ME request, for FFC 夾夾夾 issue P.22 JSD1 connector change symbol 4pin to 6pin 2014-08-13 DVT-PVT
8 Pass
For DFB request P.19 JWLAN1 change symbol 2014-08-13 DVT-PVT
9 Pass
Reserve For ESD request Add C5274, CC101, CC102, CD88, PC328, PC329, PC330, PC428,PC429 2014-08-18 DVT-PVT
10
For ME request P.20 Fix hole H9 Change to H_4P0, Add H12 2014-08-18 DVT-PVT
11
For ME request layout JEDP1 change location placement 2014-08-18 DVT-PVT Pass
12
Item Reason for change PG# Modify List Date Phase Verify
+3VLP/+RTCVCC
?s(>9ms)
(PCH input) PCH_RTCRST#
?s(>0ms)
+5VALW/+3VALW
?s(>10ms)
(EC P100 to PCH) EC_RSMRST#
?s(>10ms)
(PCH output) SUSCLK
?s(<90ms)
AC_PRESENT Monitor +3VALW
?s(>30us)
(PCH to EC P123) PM_SLP_S5#
?s(>30us) ?s(>30us)
(PCH to EC P121) PM_SLP_S4#
C C
?s(>30us)
(PCH to EC P6 ) PM_SLP_S3#
?s(=10ms)
(EC P95 output) SYSON
?s(>5us)
?s
+1.35V ?s(>40ns)
?s(=10ms)
(EC P116 output) SUSP#
?s
+5VS
?s
+3VS
?s
+1.5VS_VTT
?s
+1.05VS
?s
(EC P108 input) 1.05V_VS_PG_PWR(Follow +3VS)
?s
(EC P21 input) VCCST_PWRGD(Follow +1.5VS_VTT)
B B
+CPU_CORE
(PCH input) VGATE
?s(>5ms) ?s(>0s)
(EC P32 to PCH) PCH_PWROK
?s(>0s) ?s(<100ns) Could be before SLP_S4#
(PCH output) DDR3_DRAMRST#
?s(5ms~650ms) ?s(>30us)
(PCH output) H_CPUPWRGD
?s(5ms~99ms) ?s(>0s)
(EC P74 to PCH) SYS_PWROK
?s(>1.06ms)
(PCH to EC P13) PLT_RST#
A A
Title
POWER SEQUENCE
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CustomLA-B921PR10 1.0