EM316 DIGITAL ELECTRONICS

LABORATORY 5

NMOS Inverters (Resistor Loaded, Saturated Enhancement

Only Loaded, Linear Enhancement Only Loaded)
In this laboratory, inverter characteristics are described in details for various MOSFET cases
with different loads.

Resistor Loaded NMOS Inverter

Figure 19 Shows the NMOS inverter with resistive load, RL. The input to the inverter is at the
gate of the N-channel output transistor NO and VIN = VGS. The output is at the drain and VOUT
= VDS = VDD – IRL RL. For VIN < Vt, NO is cut off and does not conduct drain current. Since
the resistor current is equal to the drain current, with VIN Vt IRL = ID(OFF) = 0 and the output
is VOUT = VDD. As the input is increased slightly above the threshold voltage NO begins to
conduct. At this point only a small current flows and the drain voltage is lightly less than
VDD. As long as VDS >= VGS – Vt, NO is operating in the saturation region. With further
increase of the input, a larger drain current conducts and the output voltage continues to fall.
In summary, for a low input the output is high. Conversely for a high input the output is low.

Figure 19 Resistor Loaded NMOS Inverter

Saturated Enhancement Only Loaded NMOS Inverter
Figure 20 shows the NMOS inverter with an enhancement-only N-channel MOSFET as a load
device. With the gate and drain of the load transistor NL connected, we have
V DS , L = VGS , L > VGS , L − VT , L
and thus the load transistor NL operates in saturation only. The input to this inverter is at the
gate of the output transistor NO and VIN = VGS,O. the output is at the drain of NO and VOUT =
VDS,O = VDD – VDS,L.
For VIN < VT,O, transistor NO is cutoff and does not conduct drain current.
As the input is increased above VT,O, transistor NO, and NL begin to conduct with equal drain
currents. Since VDS,O >= VGS,O –VT,O, transistor NO is operating in the saturation region of
operation.

Figure 20 Saturated Enhancement Only Loaded NMOS Inverter (a) Source-body connected load, (b) load
with body-bias
Linear Enhancement Only Loaded NMOS Inverter
The output high voltage of an enhancement-only loaded NMOS inverter can be raised to
VDD by using a load that operates in the linear region. This is accomplished by applying a
separate, larger voltage source to the gate of NL, as shown in Figure 21

Figure 21 Linear Enhancement Only Loaded NMOS Inverter:(a) Source-body connected load, (b) Load
with body-bias, (c) Graphical determination Voltage transfer characteristic, (d) Voltage transfer
characteristic obtained from curve intersections of (c)

Simulation1
Setup SPICE model of circuit shown in Figure 22. Plot Voltage transfer characteristic
obtained from DC sweep and transient response of output.
Show rise time, fall time for each simulation result. And also calculate maximum frequency
using rise-fall times.
 V2
5Vdc

0
R1
50k

M1 V

V1 = 0 V1 Mbreakn
V C1
V2 = 5 1P
TD = 0
TR = 2n
TF = 2n
PW = 500n
PER = 1u

0 0 0

Figure 22 Resistor Loaded NMOS Inverter

Simulation2
Setup SPICE model of circuit shown in Figure 23. Plot Voltage transfer characteristic
obtained from DC sweep and transient response of output.

V2
10Vdc

M3
0

Mbreakn

M4
V

VMbreakn

V1 = 0 V1 C1
V2 = 10 1p
TD = 0
TR = 2n
TF = 2n
PW = 500n
PER = 1u
0 0 0

Figure 23 Saturated Enhancement Only Loaded NMOS Inverter

Simulation3
Setup SPICE model of circuit shown in Figure 24. Plot Voltage transfer characteristic
obtained from DC sweep and transient response of output.

V3
10Vdc V2
5Vdc

M3
0 0

Mbreakn

M5
V

MbreakN
V

V1 = 0 V1 C1
V2 = 5 1p
TD = 0n
TR = 2n
TF = 2n
PW = 500n
PER = 1u
0 0 0

Figure 24 Linear Enhancement Only Loaded NMOS Inverter