Bus Synchronization Synchronous Bus

Recall the simple bus we discussed a few weeks ago:

A simplified read transaction: CLK

1. The bus master (e.g. the CPU) simultaneously: ADDR ?? A1 ?? A2 ??

1. drives the address it wants to read on the address bus
2. drives the RD/WR control signal high
3. asserts the ENABLE control signal DATA ?? D1 ?? D2 ??

2. The slave (e.g. memory or I/O device) recognizes its

address on the address bus and puts its value on the data RD/WR ?? ?? ??

bus.
ENABLE
3. The master reads the data from the data bus.

A simplified write transaction:

• Everything synchronized to bus clock, every transaction
takes one clock cycle
1. The bus master simultaneously:
1. drives the address it wants to write on the address bus
• All master outputs valid on rising edge of CLK, stay valid
2. drives the data value it wants to write on the data bus
through falling edge of CLK; slave output (for read) valid
3. drives the RD/WR control signal low
by falling edge of CLK
4. asserts the ENABLE control signal
• Setup & hold times part of bus specification
2. The slave recognizes its address on the address bus, reads
the new value from the data bus, and stores it.
• Advantage:
Question: How do master & slave agree on when data is valid,
or when transaction is over?
• Disadvantages:
1. Synchronous (“true” synchronous)
2. Asynchronous
3. Semi-synchronous

EECS 373 F98 Notes 8-1 © 1998 Steven K. Reinhardt

 Asynchronous Bus Asynchronous Bus (cont’d)

• partially interlocked:
ADDR ?? A1 ?? A2 ??

• bus specifies minimum, maximum pulse widths for

DATA ?? D1 ?? D2 ?? STROBE & ACK

• relies on devices to meet spec, breaks if pulses too short

RD/WR ?? ?? ??
or too long

STROBE

• Advantage:
ACK

• No clock: all timing based on control signal edges: • Disadvantages:

• STROBE: master to slave valid signal (slave reads on

falling edge)

• ACK: slave to master valid signal (master reads on

falling edge)

• fully interlocked: no device timing dependencies

1. master asserts STROBE until it sees ACK

2. slave asserts ACK until it sees STROBE deasserted

EECS 373 F98 Notes 8-2 © 1998 Steven K. Reinhardt

 Semisynchronous Bus Semisync Bus (cont’d)

• Variation: replace ACK with WAIT; assume minimum

CLK
transaction time unless device asserts WAIT

ADDR ?? A1 ?? A2 ?? • ACK or WAIT can be driven by:

• device itself (if it provides such a thing)

DATA ?? D1 ?? D2 ??

• “wait state generator”: dedicated counter/FSM logic,

RD/WR ?? ?? ?? delays ENABLE by fixed number of cycles to generate
ACK (based on device response time)

ENABLE

ACK

• Everything synchronized to bus clock, but transactions take

variable number of cycles

• Slave asserts ACK to indicate that data is valid at clock

edge (must be synchronized to clock)

• Control signal edges convey no timing information

• Minimum transaction usually multiple cycles (2 in example,

on MPC823; 4 on 8086)

• Extra clock cycles between start and end (due to late ACK)
are called wait states

EECS 373 F98 Notes 8-3 © 1998 Steven K. Reinhardt