316 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 28, NO.
3, MARCH 2009
Application-Driven Voltage-Island Partitioning
for Low-Power System-on-Chip Design
Dipanjan Sengupta, Student Member, IEEE, and Resve A. Saleh, Fellow, IEEE
Abstract—Among the different methods of reducing power for
core-based system-on-chip (SoC) designs, the voltage-island tech-
nique has gained in popularity. Assigning cores to the different
supply voltages and floorplanning to create contiguous voltage
islands are two important steps in the design process. We propose
a new application-driven approach to voltage partitioning and
island creation with the objective of reducing overall SoC power,
area, and floorplanner runtime. Given an application power-state
machine (PSM), we first identify the suitable range of supply
voltages for each core. Then, we generate the discrete voltage
assignment table using a heuristic technique. Next, we describe
a methodology of reducing the large number of available choices
from the voltage assignment table down to a useful set using
the application PSM. We partition the cores into islands, using a
cost function that gradually shifts from a power-based assignment
to a connectivity-based one. Compared with previously reported
techniques, a 9.4% reduction in power and 8.7% reduction in
area are achieved using our approach, with an average runtime
improvement of 2.4 times.
Index Terms—Low-power design, power-state machine (PSM),
voltage-island optimization.
I. I NTRODUCTION
W ITH THE advent of deep submicrometer technology,
it is now possible to integrate hundreds of millions of
transistors on the same chip. This enables applications to be im-
plemented using system-on-chip (SoC) design methodologies
that utilize predesigned blocks called IP cores. Unfortunately,
this scaling trend has caused the overall power consumption
to increase beyond acceptable limits. High power consumption
not only causes shorter battery life for handheld devices but can
also lead to on-chip thermal and reliability problems [1].
The total power consumption of conventional CMOS cir-
cuitry is composed of two sources: dynamic and static powers.
Dynamic power (Pdyn ), which is still dominant today, is the
power consumed during active periods when gates are switch-
ing. It can be represented as
2
Pdyn = αCVDD f
where α is the switching activity, C is the load capacitance,
f is the clock frequency, and VDD is the supply voltage. Static
Manuscript received November 30, 2007; revised March 12, 2008, July 9,
2008, and September 10, 2008. Current version published February 19, 2009.
This work was supported in part by the NSERC and in part by PMC Sierra.
This paper was recommended by Associate Editor N. Chang.
The authors are with the System-on-Chip Laboratory, Electrical and Com-
puter Engineering Department, University of British Columbia, Vancouver, BC
V6T 1Z4, Canada (e-mail: dipanjan@ece.ubc.ca; res@ece.ubc.ca).
Digital Object Identifier 10.1109/TCAD.2009.2013270
0278-0070/$25.00 © 2009 IEEE
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power (Pleak ) in CMOS designs is primarily due to subthresh-
old leakage [2] and can be expressed compactly as
−VT
Pleak = I0 e nVth VDD (2)
where I0 is the leakage current coefficient that embodies a num-
ber of factors, VT is the threshold voltage, Vth is the thermal
voltage, and n is the subthreshold swing parameter. Projections
for the off-state current indicate an increase of approximately
five times per generation [3]. Thus, leakage power is now a
critical design concern for many very large scale integration
systems.
The overall goal of any design is to meet a certain perfor-
mance goal while consuming the minimum possible energy.
The energy of a digital design is given by
E = (Pdyn + Pleak ) × Dcrit
where Dcrit is the critical-path delay of the design of the form
 Ki VDD
Dcrit =
i
(VDD − VT )α
which is the sum of all gate delays in the path, with Ki and α
as fitting parameters similar to the approaches in [4] and [5].
Some of the popular approaches for reducing dynamic and
static power consumption are the use of clock gating [6], power
gating using multithreshold transistors [7], multisupply and
multivoltage (MSMV) [8], substrate biasing [9], dynamic volt-
age and frequency scaling [10], and power shutoff (PSO) [11].
The use of MSMV to form voltage islands [8] is one of
the most attractive solutions in core-based SoC design [12].
Reducing the supply voltage provides a quadratic improvement
in dynamic power and linear improvement in leakage power,
based on (1) and (2). The technique requires the availability of
multiple supplies on the same chip and design of several power
grids to deliver current to the IP blocks. Performance-critical
(1) blocks, such as processor cores, usually require the highest
supply voltage level, while other functions, such as memories or
control logic, can operate on lower supply voltages [13]. While
it is possible to have a large number of supply voltages on the
same chip, only a few supply voltages are practical [14].
Given a finite number of supply voltages, the task at hand
is to partition a given set of IP blocks into subsets associated
with each voltage level and then to apply a floorplanner to form
contiguous voltage islands to facilitate the layout of multiple
power grids. For the voltage-island design, we define a feasible
floorplan as the one where cores with the same supply voltage
are contiguous to one another and satisfy the overall area budget
SENGUPTA AND SALEH: APPLICATION-DRIVEN VOLTAGE-ISLAND PARTITIONING FOR SYSTEM-ON-CHIP DESIGN
Fig.1. SoC with (a) single voltage island and with (b) three voltage islands.
for the design. Fig. 1 shows a SoC having 15 IP blocks before
and after applying voltage islands. In Fig. 1(a), all the blocks are
assigned to 1.5 V, while in Fig. 1(b), the performance-critical
blocks are assigned to 1.5 V, and the other blocks are assigned
to either 0.9 or 1.2 V, depending on their design requirements.
The overall power dissipation of the design in Fig. 1(b) is far
less than that in Fig. 1(a) due to reduced dynamic and static
powers.
In general, the cores in a SoC can operate over a range of
supply voltages. This range must somehow be converted to a
discrete set of fixed supply voltages that are used to define the
voltage islands. Further, it is imperative that the assignment of
cores to voltage islands meet the individual timing requirements
and satisfy the overall power budget. Additional consideration
must be given to the area overhead of this technique stemming
from the use of level shifters, on-chip or off-chip power supply
for each island, and the routing of multiple power grids.
In the past, the starting point for voltage-island creation was
a voltage assignment table [15], [16]; however, information
was not provided as to the generation of such a table. In this
paper, we show that the application power-state machine (PSM)
contains the needed information to create the voltage assign-
ment table. Partitioning strategies of the past used floorplanning
in the inner loop of the optimization process, which can be
expensive as the number of IP blocks increases. We apply it at
the end of the process on high-quality partitioning candidates.
The key contributions of this paper are as follows.
1) Given an application PSM, we extract the activity levels
to establish the supply voltage ranges that satisfy tim-
ing constraints and choose optimal supply voltages for
each core.
2) A method of constructing the voltage assignment table is
presented to select a discrete number of voltages for the
SoC using a heuristic technique.
3) A new floorplan-aware partitioning approach is described
using a mixture of deterministic and heuristic techniques
to select attractive solutions for floorplanning to reduce
the power, area, and runtime.
The remainder of this paper is organized as follows. In
Section II, we provide the background for this work and identify
certain drawbacks of previous approaches. Section III describes
the method of establishing suitable supply voltage ranges for
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317
Fig. 2. Voltage-island generation algorithms in [15] and [16].
each IP core and the power optimization framework used in
the voltage assignment process. In Section IV, a maximum of
three supply voltages are chosen for each core. In Section V, we
present a heuristic technique to convert a relatively large set of
supply voltages to a smaller subset for implementation on the
SoC. In Section VI, we describe our methodology to identify
the most attractive solutions for floorplanning from the large
number of partitioning options that are available. Results are
provided in Section VII. Conclusions are given in Section VIII.
II. B ACKGROUND
One of the crucial steps of MSMV is to group cores with
similar supply voltages into a small number of islands. In [13],
[17], and [18], voltage islands were created starting with a fixed
floorplan, as shown in Fig. 1, with the critical path spanning
more than one block. Optimization techniques considering
the thermal distribution during voltage-island design has been
proposed in [15] and [19]. A power-network-aware voltage-
island design is described in [20] and [21]. Methodologies to
establish voltage-island boundaries for optimal power versus
design cost for a given performance requirement was proposed
in [17], [18], [22], and [23]. In [24], a logic and layout-aware
approach for voltage assignment and voltage-island generation
was introduced.
Different methods of assigning voltages to cores in a SoC
have been addressed in [15] and [16]. An approach based on
simulated annealing is used in [16] for partitioning the cores
into several islands during floorplanning both at the chip and
island levels. A similar approach is taken in [15], with the
additional optimization of achieving a thermally balanced SoC
design. Partitioning based on genetic algorithms and simulated
annealing during floorplanning was used to reduce hotspots and
achieve more uniform temperatures across the chip.
The algorithms for MSMV implementation in [15] and [16]
are shown in Fig. 2. In both cases, floorplanning is attempted
in the inner loop of a heuristic-based voltage assignment algo-
rithm. Unfortunately, as the number of IP blocks in a single chip
increases with technology scaling [25], runtimes associated
318 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 28, NO. 3, MARCH 2009
Fig. 3. Runtime versus number of cores versus number of islands using [15].
with floorplanning can increase significantly [26]. Both [15]
and [16] note that their approaches require multiple floorplan-
ning steps and that the execution time is only acceptable for a
small number of cores.
The number of IP blocks for future technologies is expected
to grow exponentially [27]. In comparison to a 130-nm tech-
nology node, where the number of IP blocks was about 100, the
projected number of IP blocks in 32 nm is around 10 000. Fig. 3
shows the runtime for floorplanning with increasing numbers
of cores and voltage islands using the HotSpot Floorplanner
[15]. The cores and their connections were generated using a
technique similar to that in [26]. With twice as many cores
and islands, we observe that the time required for floorplanning
increases three times. Thus, performing floorplanning at each
step of a heuristic-based approach will be very costly.
As the number of cores in a SoC increases, the set of possible
voltage assignments can also become quite large. The options
would grow even further if more supply voltages are permitted.
Many of the possible partitions do not lead to an acceptable
solution. Attempting to floorplan assignments that do not meet
power or area constraints wastes a lot of valuable time. More
efficient methods are needed to partition and floorplan a large
set of IP blocks into voltage islands.
An increase in the number of cores also poses another chal-
lenge. The number of supply voltages required may be greater
than the number of supplies that are realizable on a single chip.
Although more supply voltages could reduce the overall chip
power, the additional design complexity may offset the power
and area savings [8]. Defining α as the ratio of maximum to
minimum supply voltage, an α2 -approximation algorithm [28]
and an optimal voltage-selection algorithm [29] can be used
to choose a small number of supply voltages from a large
voltage set. In terms of time complexity, the result reported in
[28] is more efficient than that in [29]. However, the algorithm
proposed in [28] is an approximation algorithm, where the final
solution can be α times worse than the optimal solution. In this
paper, we first transform the voltage-selection problem into an
energy-minimization problem with certain constraints and pro-
pose a heuristic technique that has time complexity comparable
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with that in [28] and provides a set of supply voltages, which is
close to optimal. Then, floorplanning is carried out to minimize
the design specifications of power and area.
At several stages in the design process, the power-grid in-
tegrity for each island should be verified to ensure that the
voltage drops are within the supply noise budget. Power-grid
solutions for multiple supply voltages have been addressed in
[14]. However, the problem is more complex for voltage islands
since the voltage drops will vary on each power grid, depending
on the specific assignment of blocks to islands. Providing early
solutions to supply integrity issues will reduce the likelihood
that problems will arise late in the design process, long after
the floorplanning stage is completed.
III. P OWER O PTIMIZATION F RAMEWORK
SoC power dissipation can be optimized through the use of
multiple VDD ’s and VT ’s based on the PSM, as described in this
section. Based on timing constraints, every core Ci in a SoC
i
has the lowest supply voltage at which it can operate, VDDL .
∗
The maximum on-chip supply voltage VDDH , also termed as the
chip-level supply voltage, is the minimum voltage at which the
timing constraints of all the cores are satisfied. Thus, any core
i ∗
Ci can operate with a supply voltage between VDDL and VDDH .
i
Our first objective is to find VDDL for each core to establish
the range of possible supply voltages. Here, similar to [15] and
[16], we assume that the inputs and the outputs of the cores are
registered so that no critical path will span across two different
i
cores. Therefore, for a given core Ci , the VDDL must satisfy the
timing constraints of that particular core.
With technology scaling below 90 nm, the use of multiple-VT
libraries is standard for reducing leakage power. Many libraries
today offer three versions of their cells: low VT (LVT), standard
VT (SVT), and high VT (HVT) [30]. Each one has a different
delay–leakage tradeoff, as follows. HVT cells typically have
higher delay but lower leakage power, while the converse
is true for LVT cells. For SVT cells, the delay and power
numbers lie between the HVT and LVT cells. A dual-VT design
technique selectively places LVT devices only on the speed-
critical paths of a circuit and HVT devices on noncritical paths
to reduce power [31]. A practical limitation of such an approach
is that there can be many critical paths in a circuit, which
reduce the effectiveness of the approach [32]. Process variations
can also convert noncritical paths to critical paths, and vice
versa. Another multiple-VT technique is to use multithreshold
CMOS (MTCMOS) [11] to reduce effective leakage current. In
MTCMOS design, the cores with LVT and SVT are power
gated using HVT sleep transistors. In our approach, we assume
the use of the MTCMOS technique.
i
We now explain how we find VDDL to set the range of possi-
ble supply voltages for each core using the VT libraries. Fig. 4
shows HSPICE simulation results in the 90-nm technology of
delay versus supply voltage for a variable activity circuit, based
on the ring oscillator [33], using the HVT, LVT, and SVT
i
libraries. If the target critical-path delay is 1 ns, then the VDDL ’s
for LVT, SVT, and HVT are 0.67, 0.82, and 0.98 V, respectively,
as shown in Fig. 4. It is clear that the choice of VT controls the
i
value of VDDL .
SENGUPTA AND SALEH: APPLICATION-DRIVEN VOLTAGE-ISLAND PARTITIONING FOR SYSTEM-ON-CHIP DESIGN
Fig. 4. Delay comparison of HVT, SVT, and LVT.
Fig. 5. Power consumption for 1% activity.
To choose VT , we consider the power consumption for
different activity levels, as shown in Fig. 5 (1% activity) and
Fig. 6 (100% activity). With a critical-path delay of 1 ns,
i
1% of activity, and the VDDL results from Fig. 4, HVT cells
consume 70% less power than LVT cells. On the other hand,
for 100% activity and 1-ns critical-path delay, LVT is a better
choice than HVT, as there is 58% power reduction. Hence,
based on delay and activity, cores should be assigned either
LVT or SVT cells (with power gating) or HVT cells (without
power gating). However, if the required supply voltage for HVT
∗
implementation is greater than VDDH , the maximum allowable
supply voltage, SVT cells should be used instead. For example,
∗
in Fig. 5, if the VDDH is 0.9 V, the timing cannot be met, and
thus, SVT should be chosen instead of HVT.
Thus, the range of supply voltages that can be assigned
to each core will depend upon the type of VT cell used for
implementation and its overall activity. In general, the cores
with high activity must be realized using LVT cells, while
cores having low activity should use HVT cells. Based on delay
specification and the maximum allowable supply voltage, the
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319
Fig. 6. Power consumption for 100% activity.
Fig. 7. PSM of SoC.
designer may have to choose SVT instead of the HVT. The
power and delay variation due to change in supply and threshold
voltage can be derived for any arbitrary core using power and
delay macromodels [34], [35].
A. PSM
In order to apply the aforementioned results, we first assume
that each core has a known activity level as a stand-alone block.
Then, to obtain the activity factors of the cores within the chip,
a state-based power representation of the application is used.
Fig. 7 shows an example of the PSM [36] of a SoC. It represents
the overall states in which a chip can operate and the legal
transitions between the states. Such a representation is under
development as part of the common [37] and the unified [38]
power formats. Given that we have enough information about
the intended application, we can extract the activity factors of
a SoC using the PSM, assign the different VT libraries to the
cores, and then select the suitable VDD .
The PSM is usually represented as a directed graph of the
form G = (Π, E, Φ, Γ), where Π is the set of all states; E is
320 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 28, NO. 3, MARCH 2009

the set of edges; Φ is the set of edge weights; and Γ is the set
of state weights. Each state Si ∈ Π describes the state of the
cores of a SoC at any given time instant, and each edge ai,j ∈
E represents a valid transition from state Si to Sj . We further
assume that such transitions are controlled by inputs from the
power manager as well as by external inputs [39]. In Fig. 7, Init
is the initial state of the system, from which the chip can change
to S1 , S2 , or S3 . Each state in the PSM describes the operating
mode of the cores in the SoC. For example, the cores can be in
any of the three operating modes: Active state (full operational
mode), Idle state (no activity state) and Sleep state (power shut
off). In every state Si , each core is in one of these three states.
As shown in Fig. 7, C1 is in Idle state in S1 and in Active state
in S4 . We assign weights w(ai,j ) ∈ Φ to the edges from state
Si to states Sj (Si , Sj ∈ Π and i = j) such that

w(ai,j ) = 1 (3)
j Fig. 8. Power, delay, and EDP versus VDD for a core.

with w(ai,j ) = 0 when no edge exists between Si and Sj . performance IC’s, there are a few blocks with high activity
To represent the relative time period, the SoC remains in while others have relatively low activity. Cores having low
a particular state; we also assign weights W (Si ) ∈ Γ to the activity (hence, higher leakage power) should be implemented
individual states. The larger the weight, the greater is the using HVT with no power gating. Cores having high activity
likelihood that the SoC will be in that state within a certain (and, thus, higher dynamic power) should be designed using
time window. Thus, the PSM provides an application-driven SVT or LVT [30], and lower supply voltages should be de-
abstraction of the different power modes, in which the cores signed with HVT power-gating transistors. Additionally, (5)
might operate, and of their respective probabilities. will be used later to distinguish between high and low power
Since the choice of SVT, LVT, and HVT depends upon the consuming cores in the method described in Section V.
activity of the circuit, we must extract activity information from
the PSM. In order to do so, we compute the overall activity IV. C HOICE OF S UPPLY V OLTAGES
factor of each core (Ci ) as αi and the overall idle factor as βi
The next step in the design process is to choose a finite

n 
n
number of supply voltages from the range of supply voltages
[w(aj,k ) × W (Sk ) × mi,k ]
j=1 k=1 for each core and generate the voltage assignment table. As an
α1 = 
n example, consider a SoC with eight cores (C1 , C2 , . . . , C8 ).
W (Sr ) Assume the chip-level supply voltage to be VDDH ∗
= 1.2 V.
r=1

n 
n We first determine the threshold voltage for each core with the
[w(aj,k ) × W (Sk ) × ni,k ] technique described in the previous section. With a target delay
j=1 k=1 i
β1 = for each core Ci , we can calculate VDDL . It should be noted

n
i ∗
W (Sr ) that the minimum value of VDDL is restricted to be VDDH /2 in
r=1 order to ensure proper operation of the gates. Next, we identify
where  a useful intermediate operating point VDDM i
by selecting the
1, if Ci is Active in state Sk optimal value of one of the various products of power and
mi,k =
0, otherwise delay, such as the power–delay product (PDP, or energy),

1, if Ci is Idle in state Sk energy–delay product (EDP) [40], or the power–energy product
ni,k = (4)
0, if Ci is Sleep or Active state Sk . [41]. Each of these quantities gives rise to a different optimal
i
VDDM value for the core. For the purposes of this paper, the one
We then use αi and βi to select the suitable threshold voltages we use is the optimal PDP value, as shown in Fig. 8. These types
for each core. The power Pi can be computed using the overall of graphs can be generated for a core if an initial calibration
activity, idle, and sleep factors of the core Ci as point is available with the delay, dynamic power, and leakage
Pi = αi PA,i + βi PI,i + (1 − αi − βi )PS,i (5) power for a given (VDD , VT ) pair. The accuracy has been shown
to be within 10%–20% of the actual values across process and
where PA,i , PI,i , and PS,i are the average power consump- temperature ranges [35].
i
tions of stand-alone core Ci in Active, Idle, and Sleep modes, The optimum energy point can be located between VDDL
∗
respectively. Therefore, power Pi represents the actual power and VDDH , depending on how leaky the core is, the degree of
contribution of core Ci to the total chip power for the given activity, and the target critical-path delay. The actual position
i
PSM. After using (4) to calculate the activity of each core, of VDDM for three different ring oscillator circuits with two
we decide the suitable VT and the range of supply voltages different activity factors is shown in Fig. 9. In general, with in-
i i
over which the core is permitted to operate. In typical high- crease in activity, VDDM is closer to VDDL . For example, when

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SENGUPTA AND SALEH: APPLICATION-DRIVEN VOLTAGE-ISLAND PARTITIONING FOR SYSTEM-ON-CHIP DESIGN 321

V. V OLTAGE A SSIGNMENT T ABLE G ENERATION

To generate the voltage assignment table, we first solve the
voltage-selection problem. Given n possible supply voltages,
choose m voltages (where m ≤ n) that minimize chip energy.
In our example, n = 5, and we set m = 3. Of the possible
∗
set of supply voltages, one automatic choice is VDDH = 1.2 V
since C8 requires it. Next, we choose m − 1 = 2 other voltages
ranging between 0.6 and 0.9 V. One possibility is to pick the two
lowest supply voltages. However, cores that cannot be assigned
to these two supply voltages are forced to operate at the
highest voltage, thus reducing their achievable energy savings.
Therefore, the solution requires consideration of many other
possibilities to determine the other two voltages. Formally, the
problem for choosing m supply voltages from n voltage choices
of a SoC having N cores can be defined as

N 
n
minimize Ei subject to xj = m − 1
Fig. 9. Energy versus VDD for variable activity and delay.
i=1 j=2

TABLE I 1, if jth voltage is chosen
OPTIMAL VOLTAGES TABLE where xj = (6)
0, otherwise

where Ei is the energy consumption of the ith core and the

first voltage (ν1 ) is the chip-level supply voltage in the list of
ordered supply voltages (ν1 > ν2 > ν3 > · · · > νn−1 > νn ).
This type of problem has been address in [28] and [29].
However, their energy function considers only dynamic power
that makes it a monotonic function. Since our energy function
(comprised of both dynamic and leakage powers) is not always
a monotonically increasing function of the supply voltage in
∗
i
the VDDL − VDDH i
range, we force this by setting VDDL to be
i i i ∗
comparing any of the circuits for 10% and 1% activities, we equal to VDDM for the cases where (VDDL < VDDM < VDDH ).
i
observe that VDDM i
decreases with higher activity. Moreover, a For example, as shown in Fig. 8, the VDDL of the core is moved
slower operating frequency and, hence, larger leakage leads to from 0.6 to 0.7 V. By doing so, the problem now has similar
i
a larger VDDM . As shown in Fig. 9, the VDDMi
of a circuit shifts characteristics to that in [28] and [29], and we solve it using
∗
toward VDDH as one moves from 101-stage to 301-stage to an improved heuristic method, shown in Fig. 10, using the
501-stage oscillators, each of which has a lower frequency than following notation:
the previous one. V array of supply voltages chosen for
The resulting values of VDDL i i
, VDDM ∗
, and VDDH can be used implementation;
to construct the optimal voltages table. Table I shows this for min {Ei (V (j))} selects minimum energy of Ci for the
j=1 to m
i
the eight cores of our example. Note that if VDDM is less than m-permissible supply voltages in the
i i ∗
VDDL or VDDM is greater than VDDH , then only two voltages V array.
i ∗
VDDL and VDDH are used. Some cores may satisfy timing with Our algorithm is greedy by nature. It begins by choosing the m
∗
only VDDH ; hence, only one voltage level is used. The voltage highest supply voltages and progressively replaces them with
values are rounded to the nearest 0.1 V since minor variations the n−m lower supply voltages. If one of the higher supply
do not greatly affect the results. For every core, the energy at voltages is replaced by a lower one, then the higher VDD is
each selected supply is also stated in the table. not considered in the rest of the algorithm, rendering this
In this table, a total of five different supply voltages are used, technique to be greedy. In the algorithm, L2–L4 are used for
implying that up to five islands could be created; the larger the initialization. Next, the n−m remaining lower supply voltages
number of islands, the greater the power savings. However, the (loop of variable “p”) are considered from high to low. When
optimal power solution may create problems when attempting each new voltage νp is introduced, we consider each island in
to generate the feasible floorplan. The floorplanner attempts to array V , ranging from two to m (loop of variable “k”). In order
reduce wire length by placing highly connected blocks close to compute the energy for new voltage choices, we first copy the
together; however, the voltage islands prefer blocks with the array V in a new array V  in line L10. Next, L11 replaces the
same supply to be placed contiguously. Even if floorplanning is kth entry of V  with νp . In L12, we do a complete reassignment
successful, the design complexity of delivering a large number of the cores to the supply voltages in V  and then recompute
of supply voltages to different parts of the chip may still be the total energy. If, by introducing νp , the new energy value
problematic. Thus, fewer supply voltages are usually selected. is less than the previous minimum energy value, we store that

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322 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 28, NO. 3, MARCH 2009
Fig. 10. Outline for supply voltage selection algorithm.
TABLE II
VOLTAGE–ENERGY TABLE
energy and the corresponding supply voltage in lines L13–L15.
To explore other solutions, each of the m − 1 supply voltages
in V is replaced by νp . If νp gives a better solution, we update
array V and the energy value esum(m, p) in lines L16–L18.
The final solution using our heuristic technique for choosing
m voltages from a set of n possible supply voltages is e∗min
in line L19. Although the approach in [28] and our approach
require the same time complexity, the space complexities of
our technique and in [28] are, respectively, quadratic and linear.
To implement this algorithm, we need to know the energy
values of the cores at all the n supply voltages. At this stage,
any core may be assigned to any of these voltages, as long
as the timing constraints are satisfied. Hence, we generate the
voltage–energy table as shown in Table II from Table I. How-
i VI. V OLTAGE A SSIGNMENT FOR F LOORPLANNING
ever, due to the additional constraint on VDDL , not all possible
supply voltages are considered for all cores. For example, in the
case of C3 , we omit the energy at VDD = 0.6 V as the minimum
i i
energy is reached at VDDM = 0.7 V. Thus, VDDL is reset to this
value. Similar effects are seen on C2 and C4 .
Fig. 11 shows the step-by-step results of applying the pro-
posed technique to the example in Table II. The supply voltages
for the voltage islands are included with each energy value. We
have shown the results from our approach for three different
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Fig. 11. Energy-based voltage choice.
TABLE III
VOLTAGE ASSIGNMENT TABLE
cases: m = 1, 2, and 3. For example, in the first square, 54 nJ is
the total energy, assuming only one island with VDD = 1.2 V.
The square with the lowest chip energy is 37.2 nJ, and the
resulting supply voltages are 0.6, 0.8, and 1.2 V. We now
refer to these as permissible voltages. As discussed before, the
lowest two supply voltages were not the best choice to minimize
power.
We have found, after running a large number of cases, that
the error incurred by the greedy algorithm, as well as setting
i i
VDDL to VDDM (for the nonmonotonic cores to make them
monotonic), is relatively small. On average, our solution is
greater than the globally optimal energy by 1% when three
islands are chosen and is indistinguishable from the globally
optimal solution when the number of islands is four or more.
In the aforementioned example, the greedy heuristic technique
actually gives the correct globally optimal solution.
Using these permissible voltages, we can now construct the
voltage assignment table from Table II to produce Table III.
Note that if a core’s lowest supply voltage is not permissible, it
must be replaced by a higher voltage that is on the permissible
list. The highest voltage is always available in this case and
is included in the table. Moreover, note that, during voltage
assignment, cores can be assigned to only the values listed in
Table III.
So far, only the voltage assignment table has been generated
but the actual assignment of voltages to cores has yet to be
performed. In typical high-performance ICs, there are many
blocks; however, only a few blocks have high activity while
others have relatively low activity [42]. Based on the power
consumption of cores in a few industrial chips, the number of
high power consuming blocks is 10%–20% of the total number
of blocks in the SoC. Using (5), we compute the power for each
SENGUPTA AND SALEH: APPLICATION-DRIVEN VOLTAGE-ISLAND PARTITIONING FOR SYSTEM-ON-CHIP DESIGN 323

core and order them from the highest to lowest power. Starting TABLE IV
POWER VERSUS LEVEL SHIFTERS
with N cores, the VDD assignment is carried out in two phases.
1) High-Power Blocks (Phase I): Select k out of N cores
that have the largest contribution to the total chip power.
Assign the lowest available VDD from Table III to each
of the high-power cores and go to Phase II. On the
next iteration of Phase I, move the core that results in
the lowest increase in power to its next highest VDD .
Repeat on subsequent iterations until all voltage options
are exhausted (deterministic approach).
2) Low-Power Blocks (Phase II): Voltage assignment for
the remaining N−k cores that have a relatively smaller
contribution to the overall power is performed using a
cost function (described in the next section) that considers
both connectivity and power (heuristic approach).

A. Voltage Assignment and Cost Function

For the k highest-power cores, which should be 10%–20% of
the blocks but comprise 70%–90% of the total power, we define
the initial islands based on their lowest permissible voltages
in Table III. For the remaining N−k cores that have smaller
activity and lower power, voltage assignment is done using
a cost function that progressively chooses better connectivity
over lower power. From a floorplanning area perspective, we
prefer solutions that produce the highest connectivity within
voltage islands and fewest connections between them (i.e., re-
quiring the fewest level shifters). Our cost function is designed
to prioritize power for the initial cores and then place more and
more emphasis on connectivity for the rest of the cores to ensure
that a feasible floorplan can be generated.
We sequence through the remaining N−k cores in a sorted
order, with the highest-power core assigned first followed by
the lower power cores. We attempt to place a given core into all
the permissible islands (three islands based on Table III) and
calculate the incremental chip power increase for each possible
assignment. We also calculate the ratio of wires connected to
the core from a permissible island to the total number of wires Fig. 12. Proposed design flow.
connected to the core. Given certain weighting factors to these
power and connectivity terms, we calculate the cost of each By adjusting χ1 and χ2 , the assignment of the N−k lower
option. The block is assigned to the island with the lowest power blocks can be entirely power based (χ1 = 1 and χ2 = 0)
cost. Formally, if “s” blocks have been preassigned to different or connectivity based (χ1 = 0 and χ2 = 1), or any combination
islands (including the first k cores) and C is the next core to in between. The resulting chip power, area, and required num-
be placed, then the assignment problem with cost estimate (Ei ) ber of level shifters depend on the choice of χ1 and χ2 . To
can be represented as illustrate this for a chip comprised of 1000 cores, the chip power
and the number of level shifters is shown in Table IV.
PC (i) WC i For the purposes of this paper, equal values of χ1 and
min Ei = χ1 
s − χ2 , i = 1 to m (7)
WCtotal χ2 (= 0.5) were used. However, other values could also be used,
PCj
j=1 depending upon the relative importance of power, area, and
number of level shifters in the design.
where the block can be placed only in the islands permissible
in Table III, PC (i) is the power consumption of the block when
B. Overall Design Flow
placed in the ith island, PCj is the power consumption of a
previous jth block that has already been assigned, WCi is the Fig. 12 shows the complete flow for voltage-island design.
number of wires from core C to island i, and WCtotal is the total Steps L1–L9 have been described in the previous sections.
number of wires of core C. As we assign more cores to islands, Step L10 attempts to estimate the worst-case IR drop and
the denominator of the power term will grow, and therefore, the the corresponding decoupling capacitance requirements in each
second term will dominate the first term in (7). Eventually, island prior to floorplanning. This step tries to ensure that when
connectivity will take control of the assignment over power. islands are formed, there is enough white space allocated for

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324 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 28, NO. 3, MARCH 2009
TABLE V
SIMULATION RESULTS ON BENCHMARK CIRCUITS
decap placement to meet the power-grid noise budget. Since
there is no floorplan available during this step, we use a simple
1-D power grid that satisfies the worst-case IR drop for each
island [43]. For each voltage assignment, dynamic IR-drop
simulation is carried out, and the decap is adjusted until the
voltage drop satisfies the allotted budget (5%–10%) for each
grid. The total amount of decap is then translated to the amount
of white space using
Cdecap
Adecap = . (8)
Cox
Finally, we attempt floorplanning with the partitioned cores
to create voltage islands. In each island, we reserve additional
white space based on (8) for decap placement after completing
the floorplanning operation. If a feasible floorplan is obtained,
then we consider it as the desirable solution. If not, we go
back to Phase I and repeat the process. A 2-D power-grid noise
analysis, as described in [44], can be performed on the final
floorplan to ensure that IR-drop violation does not exist in each
island.
VII. E XPERIMENTAL R ESULTS
This section presents the results of our proposed approach.
We have applied our methodology on a number of MCNC and
GSRC benchmark circuits. For all the circuits, a 90-nm CMOS
design kit was used in order to model dynamic power, leakage
power, threshold voltage, power, and area of level shifters.
As the designs in the benchmarks were not originally in-
tended for voltage islands, additional information was added.
A representative (but artificial) PSM was generated for each
benchmark using an approach similar to that in [45]. The power
consumption and delay of each core at 1.2 V was randomly as-
signed between 2 W and 1 mW, similar to the approach used in
[46]. The activity of each core was derived from the PSM using
the techniques described in Section III. Appropriate threshold
voltages (LVT, SVT, and HVT) were assigned to the cores
based on their activity factors, and the optimal voltage table was
generated. The possible number of supply voltages allowed on
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chip was assumed to be proportional to the number of cores.
Next, we used the heuristic technique (as in Section IV) for
choosing the permissible supply voltages that could be used for
realizing voltage islands on the chip. This produced the voltage
assignment table.
We applied our technique on 11 benchmark circuits using the
HotSpot Floorplan Tool that included the LAPACK package
[47]. The experiments were run using an Intel Pentium 4
2.4-GHz machine with 2-GB RAM running on Debian Linux
(version 2.6.18).
The flow presented in [15] is our main comparison point
due to the availability of the floorplanning tool and on their
use of the same benchmark circuits. As the voltage assignment
table is the starting point in [15], we use our table, generated in
Section IV, as a starting point for their design flow. Based on the
relative importance of power and area, a number of coefficients
must be assigned to the fitness function in [15]. In our approach,
we have given equal importance to both power and area by
assigning χ1 = χ2 = 0.5. Similar priorities were given to the
coefficients in the fitness function of the genetic algorithm in
their technique.
Table V compares the runtime and the quality of results
(number of voltage islands, area, and power) of our approach
with [15]. Both methods were required to use the same number
of islands. Columns 10–12 compare the savings of our proposed
technique against that in [15]. Our power and area values are
significantly better than those obtained using the flow in [15],
with an average improvement of 8%–10%. The runtime is
2.4 times better. This is due to the reduced number of floorplan
iterations required to generate a feasible floorplan. Note that
voltage assignments far from the optimal are often attempted
in the genetic algorithm. Our approach is specifically targeted
to avoid such floorplan attempts, as it only adds to the runtime
[48]. The incremental cost is relatively small for ordering the
cores and finding the preferable voltage assignments for which
floorplanning should be attempted. In the case of xerox, the
two techniques produced the same power and area solutions,
although our technique was much faster than that in [15]. For
the circuit n10, the power consumption was slightly higher for
SENGUPTA AND SALEH: APPLICATION-DRIVEN VOLTAGE-ISLAND PARTITIONING FOR SYSTEM-ON-CHIP DESIGN
Fig. 13. Floorplan of n50 using (a) technique in [15] and the (b) proposed
approach.
our result. Such anomalies are possible for the smaller circuits.
In Fig. 13, we compare the floorplans of n50 obtained using
the technique in [15] and our approach. Both floorplans use six
islands; however, the power consumption and cores assigned to
the islands were different. Our solution shown in Fig. 13(b) has
an area that is 5.8% less and a power that is 9.7% less than their
corresponding result of Fig. 13(a).
Investigating the thermal effect on the floorplan of each
benchmark, we found that the average temperature in our case
is approximately 9%–10% lower than that in [15]. Additionally,
the peak temperature was approximately 13% lower. The reason
is that our approach assigns more cores to islands with lower
supply voltages. This leads to an overall reduction in the
dynamic and leakage powers, which, in turn, lowers the on-chip
average and peak temperature [49].
We also inspected the floorplan solutions of all the bench-
marks and noticed that, in some cases, there were blocks that
belonged to one island but were surrounded on three sides
by other islands. This problem can be seen in circuit (n100),
as shown in Fig. 14(a). The voltage-island design not only
requires placement of blocks belonging to similar islands in
a contiguous fashion but also must ensure that there are no
power-grid design problems due to the final placement. Such
floorplans may produce an IR-drop problem when a 2-D power-
grid analysis is performed. To avoid such potential problems,
we attempt to move this block to other adjacent islands and
assess the incremental cost in power, level shifters, and power-
grid design. The lowest cost solution is used, as long as only two
sides are adjacent to other islands. The solution selected for this
case is shown in Fig. 14(b) and indicates the final adjustment to
a different island.
VIII. C ONCLUSION
In this paper, we have proposed a comprehensive,
application-driven, and floorplan-aware methodology for
voltage-island design. First, we identified meaningful supply
voltages for each core and constructed a voltage assignment
table using a greedy heuristic technique. Next, the voltage
assignment to the cores was attempted in a two-stage approach.
By observing that cores in a SoC can be categorized as high
and low power blocks, a deterministic sequence of options is
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325
Fig. 14. Detailed floorplan of n100 illustrating final adjustments. (a) Floor-
plan of n100 with potential IR-drop problem. (b) Floorplan of n100 without
IR-drop problem.
explored using power as the priority, and then, a heuristic
approach is used for remaining cores based on a power and con-
nectivity cost function. We then attempt floorplanning for each
assignment solution. We compared our results with existing
work on a number of benchmark circuits and obtained improve-
ments of 9.4% in power, 8.7% in area, and 2.4 times in runtime.
ACKNOWLEDGMENT
The authors would like to thank the reviewers for many
valuable suggestions and comments that have significantly en-
hanced the quality of this paper.
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Dipanjan Sengupta (S’05) received the B.Sc. and
B.Tech. degrees from University of Kolkata, Kolkata,
India, and the M.A.Sc. degree from University of
British Columbia, Vancouver, BC, Canada, where
he is currently working toward the Ph.D. degree in
the System-on-Chip (SoC) Laboratory, Department
of Electrical and Computer Engineering.
His research interest includes low-power SoC de-
sign, with particular emphasis on voltage-island de-
sign and power-gating techniques.
Resve A. Saleh (S’78–M’79–SM’03–F’06) received
the B.S. degree in electrical engineering from
Carleton University, Ottawa, ON, Canada, and the
M.S. and Ph.D. degrees in electrical engineering
from the University of California, Berkeley.
He was a Founder of Simplex Solutions which de-
veloped computer-aided design (CAD) software for
deep submicrometer digital design verification. Prior
to starting Simplex, he spent nine years as a Professor
with the Department of Electrical and Computer
Engineering, University of Illinois, Urbana. He also
taught for one year at Stanford University, Stanford, CA. He was with Mitel
Corporation, Ottawa, ON, Canada; Toshiba Corporation, Japan; Tektronix,
Beaverton, OR; and Nortel, Ottawa. He is currently a Professor and the Natural
Sciences and Engineering Research Council/PMC Sierra Chairholder with the
System-on-Chip (SoC) Laboratory, Department of Electrical and Computer
Engineering, The University of British Columbia, Vancouver, BC, Canada, in
the field of SoC design and test. He has published over 100 journal articles
and conference papers. He coauthored a book entitled “Design and Analysis of
Digital Integrated Circuit Design: In deep submicrometer technology.”
Dr. Saleh received the Presidential Young Investigator Award in 1990 from
the National Science Foundation in the U.S. He is a Professional Engineer
of British Columbia. He served as General Chair (1995), Conference Chair
(1994), and Technical Program Chair (1993) for the Custom Integrated Circuits
Conference. He held the positions of Technical Program Chair, Conference
Chair, and Vice-General Chair of the International Symposium on Quality in
Electronic Design (2001), and has served as Associate Editor of the IEEE
TRANSACTIONS ON CAD.