Sopc Builder + Nios Ii PDF

DO AN TOT NGHIEP GVHD: Th.
S HUYNH HUU THUAN
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CHONG Done... eeescsccceccceeeseececceeeesseececceeaesseeecesseaeseeeeceeeeaageeeeceeees 3
Gidi Thiéu Vé Phan MO@M....000..0....... cece ccccccccccccceceeeeeeeeceeeeeaeeeaeeaeeas 3
L1. Phan Mem QUATtUS TT....sscccsrccccsssccssssccssssccsssscscsscccssscsssssesscssscssssesscsccscssscssssccsssscesscsccsscseees 3
1.2. SOPC BUILDER.......scsscssssssssscssssossssesssssssesscnssesscesssssesecnssecsssesscnecessoeucooescsssvssceorscsseesasesess 11
1.2.1 Khdi nidm vé SOPCS..sccsscssssssscssssssssssvsssssssssssessscssssssssssssssssessescesessessesecssessasssssssesseeees 11
1.2.2 Thiét Ké SOPC Builder Ditng MG Verilog....s.cccscsssssssssssssssssssssssssssssssesssssssssesasssssesees 15
1.3 Phan Mém NIOSIL IDE.......ccssssssssssssssecsssscsesssssssvssssessssscsecsssscessssevsessecsesscsessvsessessossssecses 21
1.3.1 Téng quan cdc tinh nding cia bG vi xiv lf NIOS Ls.cscssssssssssssssscssssssscssssssacsssscsscssssee 22
1.3.2 Ca Tritc Thanh Gii vesssssscsssssssssssssssssscscsscsasscsscscssssscscssssssessssessssscessscssesssacsesscssesessees 23
1.3.3. Truy Xudt BG NAG Va Thiet By W/O.ssccsssesssscsssssssssssssssssssssssssssssssessscssssssacscsssacssesees 26
T.3.4, Did Chicccssssssrsscsssssscesssssssscsssscsscesscssssesscecssssesousscossecsssusssasasousscessussssnsocsesseesscossseseeesens 27
T.3.5, Tip L@nh wesssssscsssssssesssssssscssssesscesscssssessecssssesousseessecsssusssassasosucecsusessnsecseesseesasoesseseeesecs 28
1.4 Board DEZ.......cccccssscccccscccsssssesssscsssscssssscessssceeeeseeeeneesssssssssscessssceoeeseoecssessesssssssscesssscosessoooees 29
L.4.1. Tinh nang cla Mgch DE2 w..csssrsessrsersrserssescessssesessasesesssescessssscssssssseesasseesseees 29
1.4.2. ThONG 86 KY thuGt....sssresssssereecssersessssesaresssecsssessssseesesecsssesessssssasesssseseesseseessessseesaseees 30
1.4.3. Nhitng Vi Du Ve Nhieng tong Dung Cao Cap vesssssssssssssssssssssssssssssssscscssssacscsacsscssssees 34
Chung ID... ccesccceccceeccecccecccccececeeeeeeeseceseesecaeeaaeauseaeasaesaeesssseseeensess 36
Audio Codec W873 1/Liuw. wee cceccccssecccsscecsscecccceccccscceessceeessceeesceeseseess 36
IL.1 Gidi Thigu Ve AUDIO CODEC W8731/L.....ssssssssssssssssssssssssessssessessssvsessecsvsscsecsossseessoes 36
T.1.1 Duong Dain Line [nputccccccccccssscccsssscssssssssssssscsssssssessesssscssssssssscesesscssssssssssssessssesssees 38
TT 1.2 Ng6 V@o0 Microphone ...ccccsscccccsssssccsssssrsccccsssssscccccssssccccsssssscssscssssccssssssssccsssssssacesessees 4]
HI.1.3 MICROPHONEBIASiscscsssscsssssssssssssscsssssscsscscscssssesscsssssscsacscssesssesacsessesesseeasscaacessesess 41
TI.1.4 BG L9C ADCvissssssssssssssssscscssssssssssscssssesscscsssscscssssesscsssssscsasscssesscesassacsesesassessesssesaceassesess 41
TT, 1.5 BG LQC DACvasssccsssssssccsssssssccsssscsssscsssssssssssessscesssssessscccssssssecscessscsccsssssossacssssssssasscessees 43
TT, 1.6 Litte NGO Ra, iscsccsccssssccsssssrsccsssscsssscssssssssscscessssesssssessssccssssssenscessssscessssssssacssssssssasscessees 44
H1.1.7 HEADPHONE AMPLIFIER\ussssssssssssssssvssssvsssscesssssscssssssesssseesssssesessssersossseoesseasesesass 45
11.2 Cdc Ché DO Hoat DONg.......scccscssscsssssssssssscsesscsssesessssssessecsssvsessesscsssscessesscssscesssssosessceoees 47
TI.2.1 SYPASS MODEvissssssssvsssssssssssssssscssssssssssssssescssssesssssssssassessscesssessssansssessssassesssesassaseesees 47
HI.2.2 SIDETONE MODE.uesssssssssssssssssssssssssscscsssscssssssesscsssssscsasscssesssesscsacsesesasssssesssesasessesess 49
11.3 Hoat Dong Cita Thiet Bj .........cccssssscsssscessssessesscessssecsssscsecsssecsessssesessessesesseseessssecsssscsecsees 50
TI.3.1 Cai DGt Lai Thiet Bj .ccsssesscsssssssssssssscsssssssssssessssssssssssssssssssesssscesesssesesecssesseesseessseeseeees 50
T1.3.2 Lege D6 CLOCKINGwisessssssssssssssssssssssssssessssessscssssssssssssssscesssscesessscseseessesssaussessssesseeees 50
HT.3.3 LOTXUNG CLOCK, wissecssscssssscscssscscecscscssscscssssscsssssessssscsnsnscssssscssssscssssscsssssssssssessensess 51
IT,3.4 May Tao Dao DOng CRYSTAL.wcsccccssssccccsssssrscccssssssccccssssscccscssssccssssssssccsssssssacsssssees 51
TI.3.5 CLOCKOUTvesesssssssssssssscscsssscsssssscsscssssscssscscssssesscssssssssaescssesssesassacsesesavsassesasesaceassesecs 52
I1.3.6 Gido Dig PHAN MEM.cescsccssssssssssssssssscscsscsasscsscscssssscsssssssssssssssessscsesscssssssacsesscssessssees 53
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1.3.10 Sw Hoat Déng O Ché D6 Master/Slave...cssccccsccssscssssssssssssssssssssssssssesssssssseessvssssesees 61
IL.4 MG té tong qudt vé SD CARD wisscssssssscsscssssssssscsscscssssscscssssssesssssessssssessscssssssacsessessessssees 62
UD, 4.1 Titth NG1g..ccssccccssscssccccsssscsccssssssscccssscssccsscssesscccsssssssccccssssssccscssscsacsecsssesacesesscsasescssees 63
TH4.2 Ung dung visccrscsscsrsssssscssssssssssssscsscsssscssscsssssscssscsssssscsssscessssecssscsesscecsssesensvsseceseessesseseess 63
1.4.3 M6 TG Port Cita SD Cardseccssscsscssssvsssscsssssscsssscssessssssssessscssseesssscsssssessssseesssossesseesens 63
IL.5 Dinh Dang FAT.....ccssssssssscssssssssssssssessecessesscessecsssssssssscessecsssvsscessecsesscsesscscsesscesssssosssncesees 64
11.6 Khai Niém Ve Tap Tin Wave .....ccccccsssssssssssssssssssssssssssssecssssessesscsssssessesscsvsscesssssosvssceoees 68
SVTH: NGUYEN MINH HIEU —- HUYNH CONG PHU Trang 1

DO AN TOT NGHIEP GVHD: Th.S HUYNH HUU THUAN
Chuong 3 Hé Thong Tong Quat oo... cccccccceeceeeceeeeeeeeaeneeeeees 70

IIL.1 Thiét KE M6 Hinh SD Music Player,......s.ccccsssssssssssssssssssssssssesscsssscessesscsvsscesssssosessceoees 70
TIL.2 Chirong Trinh Demo........sssssssrsssssseresseseesssssevsssseesssssseesssnssesnsensessecsnsscsscsvssssessoensseesess 71
TIL. 2.1 Cac Dinh Nghia Thiet LGp .....ccscccccscssssccccsssssssccssssssccccssssssccscssscssccsesssesaccesssessscessssees 71
HIT, 2.2 Cac Chirong Trinh Con Va Cac Ham Con...ccsccccccsccccsssccssccscccscccccssccccscscceessccceeeees 73
TIT, 2.3 Chivong Tritth CHINN,...cscccsscccsssssscsssssccsssscccessssccssscscscsssscsssssscccsssscssssessscsssssessscssecees 85
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PRU LUC 0c ccccceccceccceccceeeeeeeeeeeeeseseseaaeauenaaeaaaaaaasaaeseessseesesessees 90

pO AN TOT NGHIEP GVHD : Th.S HUYNH HOU THUAN
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Chuong I
Giéi Thigu Vé Phan Mém

L1. Phin Mém Quartus IT
Héthéng Quartus II bao gdm day du tat ca céng thirc théng thudng dé mé ta
yéu cau mach vao trong mét hé théng CAD, Ngwéi ding cé thé chi dinh yéu cau mach
vao trong ngén ngit mé ta phan cimg Verilog hoic VHDL. Vacai khac 1a dya trén ndi
dung yéu cau mach trong mau cia mét so dé biéu dé. Bude cudi cing trong qué trinh
thiét ké can phai cau hinh mach thiét ké trong thiét bj Nios II that.
Méi machlogic, hay mach phy, thiét ké bang phan mém Quartus II duge goi la mét
Project. Phan mém lam viée trén mét project tai m$t thoi diém va gitt théng tin cho
project trong mét thu muctrén file hé thang. Dé bat ddu thiét ké mét mach logic mdi,
trude tién phai tao mét thu myc dé chita cdcfile cha nd.
reyTa Ta)
File Edit View Project Assignments Processing Tools Window Hel
jo cele.oR 7ee|o)> o>|»
ProjectNavigator —_______=|x|
Entity
B Compilation Hierarchy)
Q U A RT U S I I
fe
Status i
Module. [Progress % | Tine &
Version 5.0
tp: ‘fw. altera.com
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1E)\ Spstem{Frocessng JEntalnfoJIne,Waming JL GittealWaring J Eror [

2 Messe: &| $| [Gen T=] Lssate
For Help, press FL ea Tale [ [ Z|
Hinh1.1.1, Hién thi chinh QuartusII.
SVTH: NGUYEN MINH HIEU - HUYNH CONG PHU Trang 3

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Hauhét cdc lénh cung cap boi Quartus II cé thé duge truy xpat bing cach ding
métthiét lap cua menu duge xdc dinh dudi dang thanh tiéu dé.
File Edit View Project Assignment

D dew... culn
(& Open... creo
lose Cnlere
New Project Wizard...
i Open Project... crl+J
Convert MAX+PLUS II Project...
save Project
Glase Project
l\save nl+s
Save AS,
Save GUITEK: Report Sesion As...
file Properties.
Create (Update ¥
Export...
Convert Programming Files...
MPage Setup...
[E& Print Preview
= Print, Cale
Recent Ales Yi
Recent Projects ¥
Exit AlT+F4
Hinh 1.1.2. vi du file menu
Débat dau mét thiét ké moi trudc tién phai dinh nghia métthiét ké project mdi.
Tao mét project méi nhu sau:
> Chon File > New Project Wizard dé dugc cita sé nhv hinh 1.1.3. Co thé
bé qua cita sé nay trong project sau bang céch dinh d4u check vao hop

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thoai Don’t show methis introduction again. Nhan next sé thay cura sé
ohhinh 1.1.4.
[ere re eee oad
The New Project Wizard helps you create a new projest and prelminay project settings,
including thefollwing:
@ Project name and directo
@ Name of the toplevel design entity
@ Project tiles and libranes
# Target device family and device
# EDAtool settings
You can change the cetlings for an existing project and specify additional projectawide
settings with the Settings commend [Assignments menu, You can use the various
pages of the Seltings dialog box to add functionality to the project.
[7 Don't show me this introduction again
Hinh 1.1.3, Thao tac thye hién bing Wizard Tasks

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New Project Wizard
\what is the working drectory forthis projec!?

[D ntrotutail sl
\whatis the name of this project?
[ich sl
What is the name of the top-level design ertity fer this project? This name is case senstive
and must exactly match the entiy name in the design file
[light we
Use Exisiing Project Settings
s Back Next> Finish Cancel
Hinh 1.1.4. Tao mt project mdi.
> Nhin next, Tir day chung ta da tao ra m6t thu mycintrotutorial hay chua, phan
mém Quartus II hién ra mOt hp trong hinh 1.1.5 héin6 sé tao ra m6t thu myc
mong muén.click Yes, hién ra cra sé trong hinh 1.1.6
ene EI
ay Directory "D: Antrotutonal" does mot exist. De ycu want to create Ite
Yes No |
Hinh 1.1.5, Phan mém Quartus II sé tao ra mét thu muc cho project

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New Project Wizard: Add Files [page 2 of 5]
Select the desiqn files you want to include in the project. Click Acd All to add sll design files
in the project directary to the project. Note: you can always add design files ia the project
later
File name: Bi
File name Type Add All
ao
Basie
as
[tein
Specty the path names of any non-default fbraries UserLibraries..
< Beck Finish Cancel
Hinh1.1.6. Wizard cé thé bao gémfile thiét ké ly thuyét.

> Néu khongcéfile nao tin tai, Click next, sé thdy cira sé trong hinh 7.

New Project Wizard: Family & Device Settings [p..
Select the family and device you wantto taiget for compilation.
Family: CycloneIl 2
Target device
Auto device selected by the Fitler from the “Available devices’ list
Specific device selected in ‘Available devices'list
Available devices:
Filters
EP2C20F256C6
Package: Any r
Pin count Ary 2
Speed grade: [Ary *
EP2C20F4848 Core voltage: 1.2

EP2C35F4S4C6
I ShowAdvenced Devices
EP2CSOFIS4CE (Advanced)
|
Finish Cancel
Hinh 1.1.7. Chon mét hothiét bi va mét thiét bi cu thé

> Chingta cd kiéu thiét bj cy thé, ma mach dugc thiét ké s€ duge thyc thi day du.
Chon Cyclone II lam ho thiét bi myc tiéu. Ching ta cé thé cho phép phan mém
Quartus II chon hothiét bj cu thé, hay ching ta cé thé chon thiét bj r5 rang. Tir
danh sich thiét bi cho phép chon thiét bi EP2C35F672C6, ma duge SOPC
Builder ding trén board DE2. nhdn next mé cita sé trong hinh 1.1.8.

a
New Project Wizard: EDA Tool Settings [page 4 of...
Specify the other EDA tools - in additionto bre Quartus Il software -- used with the project
[7 EDA designenty # nr
synthesis tool: r
[~ EDA, simulation tool:
[EDA timing snabsistoct [SSC
< Back Finish Cancel
Hinh 1.1.8. Céng cu EDA khac
> Nauwdi ding co thé chi dinh bat ky céng cy EDA nao. Phd bién la ding phan
mém CAD cho mach dién la cdc céng cy EDA. Thuat ngit nay duge dingtrong
théng béo Quartus II dé cap dén ba céng cy. tir day ching ta sé dia vao cdc
céng cy cla QuartusII, khéng chon céng cy nao khac.
> Nhdn next. Tom tat cha nhimg chon lya trén 1a xudt hign man hinh nhy hinh
1.1.9. nhdn finish, tré vé cira sé chinh Quartus II, nhung véi light duge dinh
nghta nhw project méitrong thanh tiéu dé nhw hinh 1.1.10

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d: Summary [page 5 of 5]
\Wwhen youclick Finish, the project will be created with the following settings:
Project directony
D:dintrotutonal’
Project name: light
Toprlewel design entity: light
Number of files addect Q
Number of user ibraries addec: 0
Device assignments
Family name Cyclone il
Device: EP2C35F672C6
EDAtools:
Design enty/suntresis: <Mone>
Sirsulation: <None>
Timing analysis: <None>
< Back Concel
Hinh 1.1.9, Tom tat cia viée cai dit project.

a
€ QuartusII - D:/introtutorial/light - light

[File Editview Project AssignmentsProcessingTools Window. Help
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Project Navigator =]xj
Enlly
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>light
©Aybicisichy EBFiee |g Design Units

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Hinh 1,1,10. Quartus I sau _khi project duge tao
BUILDER
1.2.1 Khai nigm vé SOPC:
System on Programmable chip (SOC) la mét ¥ tuéng vé sv tich hgp tat ca moi
thanh phan cia mét hé théng vao mét mach tich hop (IC). Mach nay cé thé bao gm
ca cdc chite nang s6, trong ty, hodc ca hai- tat ca trén mét chip. Ung dung dién hinh
cho ¥ tong nay1a cdc hé théng nhing. Cac SOC cé wu diém 1a gid thanh thdp va don
gian. Thiét bi logic kha trinh (PLD: Programmable logic device) 14 m@tthiét bi dug
tao ra tir cdc céng logic, cé kha nang lap trinh duge dé tao cdc img dung khdc nhau. Tir
¥ tong trén, thudt ngit SOPC-system on programmable chip ra déi. Toan bé thiét ké
hé théng sé dugc tao trén métthiét bi logic kha trinh (PLD), Linh vyc nay thudng img
dung dé thir nghiém cdc hé théng trudc khi ché tao cdc IC. Mét so dé vi dy vé hé
théng SOPC duge dugetrinh bay trong hinh 1.1.

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System Module User

Logic
PCLctrl Area
je PCI »
< PCLaddrrm Bridge SM PIO
PC|_data 3
: a
Signals to [Data a Signals to
Off-Chip \ Nios c Custom ‘~ On-Chip
Devices ~ CPU instr] § [7] Peripheral [User Logic
és LI
Off-Chip
Memory
Custom
Peripheral [~
Altera PLD 4
Hinh1.2.1: So dé vi du vé hé thong SOPCtich hop trén PLD cia Altera

Céc thu vién cia SOPC builder thuémg bao gdm cac thanh phan sau:
> Vixt ly
> Cac IP va cdc két néingoai vi

> Cac giao dién véi bé nhé
> Cac thiét bi lién lac ngoaivi
> Cac giao dién va cdc bus, bao gém ca giao dign Avalon
> Cac léi DSP
Ta cé thé sir dung SOPCbuilder dé xay cdc hé théng nhing bao gém CPU,giao
tiép bé nhé, va cdc module /O. Ta cing cé thé ding n6 chi dé tao ra m6t hé théng tao
luéng dit 1igu ma khéng bao gdm CPU.
SOPCstr dung mét giao dién nguwdi ding gdm cdc nhan dan (Tab). Cac tac vu
duge phan chia theo chite ning va cdc tac vy cé lién quan véi nhau sé duge trinh bay
trén cimg m6t nhn. Nhan system contents duge hién thi khi ta mé SOPC Builder.
Hinh 1.2.2 trinh bay giao dién cha nhin nay (va ciing 1a giao dién mac dinh cha SOPC
Builder). Véi nhan systemm contentsta cé thé:

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> Thém vao hoiloai ra céc componenttrong hé thing.
> Cdu hinh cdc component.
> Chi dinh cdc dudng két néi giita cic component.
Tabs Board Settings Glock Settings Table
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botadress pointsto xcltlememory. Executionof bndefinedcode may acour upon reset
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ComponentFilters Connection Panel Messages Window Table ofActive Components
Hinh Cac thanh phan trong nhin system contents
Bang 1.1: Cac thanh phan giao dign ngwéi ding trén nhan system contents
Thanh phan Chir ning
C&c nhan (Tabs) Phan loai cic didu khién giao dién ngudi ding dya trén tic vu
Danh séch cdc thanh Liét ké thu vién cdc thanh phn sin cé theo timg loai. Mai
phan sin cé (List of thanh phan xudt hién kém mét chim mau ngay bén tén cia

Available Component) no. Cham mau nay co y nghia sau:
e Cham xanh 1a: cdc thanh phan day dir va co ban quyén
da duoc cai dat
e Cham vang: thanh phan khong day du, chi la ban danh
gia (evaluation version).
e Cham trang: thanh phan chwacai dat
Loc cac thanh phan Loc cac thanh phan theo loai
(componentfilters)
Bang cac thanh phan Liét ké cdc thanh phan da duoc cai dat trén hé thong, cho
da kich hoat (Table of phép ta chi dinh:
Active Components)
e Tén cua timg thanh phan
e Dia chico ban cho mdicéng slave
e Nguon xung clock cho mdi thanh phan
e Uutién ngat (néu cd) cho mi céng slave
Bang két noi Trinh bay cdc lién két gitra nhiing thanh phan,cho phépta:
(Connection Panel) Chi dinh lién két gitta céng master va cong slave
Chi dinh cac chia sé théa higp cho cac cong slave duge nhiéu
cong master truy cap.
Cac thiét lap bo mach Cho phépta chi dinh chi tiét nén phan ctmg:
(Board Settings)
Vi du ta c6 thé chi dinh board cy thé str dung cho thiét ké
nay, nho dé SOPC Builder sé tw déng hé tro két ndi cdc chan
ra cac thiét bi ngoai chip (nhung van trén board). Diéu nay
giam dang ké thoi gian phai néi chan cho thiét ké.
SVTH: NGUYEN MINH HIEU — HUYNH CONG PHU Trang 14

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Bang thiét lap xung Cho phép dinh nghia cdc tin higu clock duge st dyng trong
clock (Clock Settings hé thong bao gdm: tén, ngudn, tin s6, va tay chon pipeline
Table) chocc thiét ké cé téc d6 cao
Cia sé théng bdo Hién thi cdc cdnh bdo, 15i hay théng tin lién quan dén hé
(Messages Window) thinghién tai.
1.2.2 Thiét Ké SOPC Builder Ding Ma Verilog

1.2.2.1, Bét Du M6t SOPC Builder: Sao khi hoan thanh xong chong
trinh chinh vige xay m6t project méi cha Quartus I, géc phai cha giao dién ta
thay biéu tugng SOPC Builder, click vao dé sé cho phép ching thiét ké mét hé
théng SOPC Builder cé thé lap trinh duge bang Nios II IDE. Giao dién duge
thé hign & hinh 1.2.3.
WW Create fiew System Mikera S007 Builder - unvemedcoac (Catenaquarue\ ap2\unnarred toad)
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Syslen Contents System Generation
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Hinh 1.2.3. tao méi mét SOPC Builder.
1.2.2.2 Thiét Ké Hé Théng: sao khi tao méi m$t SOPC Builder, ching ta
thiét ké cdc duéng két néi bang cdch click vao Nios II processor dé add mét
cpu_0 duge thé hién & hinh 1.2.4.

4 Edit Module - Altera SOPC Bui ee ey

File Edit’ Module System View T| Nios II Processor
Documentation
System Contents System Generati
(4) Altera SOPC Builder

af ER Bay Nege]-1o(t Teg
fa ‘Bridges and Adapters :
(#nterface Protocols ~ Gore Nios Il-
‘Legacy Components
Select a Nios Il core:
ONios Il/e |ONiosIl/f |

‘RISC RISC
Nios Il 32-bit 32-bit
Selector Guide Instruction Cache
Family: Cyclone Il Branch Prediction ‘Branch Prediction
z- é Hardware Multiply ‘Hardware Multisly
Peripherals feystem: 50.0 MHz HardwareDivide Hardware Divide
SPL epuict 0 BarrelShifter
f-USB 7 Data Cache
f41-Video and Image Processing (Dynamic Branch Prediction
Performance at 50.0 MHz Upto 5 DMIPS Up to 51 DMIPS:
Lagic Usage 600-700 LEs 1200-1400 LEs 1400-1800 LEs
€ Mr | Memory Usage Two M4Ks (or equiv.) Three M4Ks + cache
- Harchware Multiply: | Embedded Multipliers +) [HardwareDivide

Edit. Add
Reset Vector: Memory: ~ | Offset: ‘oxo
2 To Do: epu_O: Noreset vector ha Exception Vector: Memory: | ~ Offset: p20
2 To De: epu_d: No exception vect
22 Warning: ¢pu_0: Reset vector an Include MMU
Only include the MMU when using an operating system that explicitly supports an MMU
Fast TLB Miss Exception Vector. Memory: | _ |OffSet |o.5
Include MPL
| Warning: Reset vector and Exception vector cannot be set until memory devices are connected ta the Nios Il processor
ii
Hinh 1.2.4. add cpu _0 vao dé tao két néi.

Nhan finish 14 ching ta da hoan thanh viéc thiét ké mét két néi cpu_0 co ban.
Giao dién dugc thé hién & hinh 1.2.5.
‘+ Altera SOPC Builder - unnamed.sope* (c:\altera\81\quartus\lap2\unnamed.sopc) a]

[=e]
File Edit Module System View Tools Nios Il Help
System Contents System i |
Clock Settings
(J Attera SOPC Builder “EEE 8
Device Family: | Cyclone Il 7) Name Source MHz
Bridges and Adapters
terface Protocals clk_0 External 50.0 Remove
egacy Components
emories and Memory Contrallers
Use Conne... Module Name Description Clock Base End
OB cpu_t Nios Il Processor

instructiom_master Avalon Memory Mapped Master clk_0
data_master Avalon Memory Mapped Master IRQ oO
jtag_debug_module Avalon Memory Mapped Slave Ox00000300 [Oxd0000
Video and Image Processing
a | Mr | +
4 4 Mr r
Edit... Remove Edit... a Move Up WF Move Down Address Map...
© To Do: epu_0: No reset vector has been specified for this CPU. Please parameterize the CPU to resolve this issue
© To Do: epu_0: No exception vector has been specified for this CPU. Please parameterize the CPU to resolvethis issue
i Warning: cpu_0: Reset vector and Exception vector cannot be set until memory devices are connected to the Nios Il processor
q Prev

Hinh 1.2.5. thiét ké module cpu_0.

Tuongty, trong ctra sé SOPC Builder nay cting cho phép ching ta add thém
cdc module két néi can thiét cho vic ké mét hé théng can thiét, Minh hoatrong hinh
1.2.6 sé cho ching ta nhin r6 hon qua trinh nay.
“Altera SOPC Builder- unnamed.sopc*(c\altera\1\quartus\lap2\unnamed.sope) eee

Fie Edt Module System View Tools Nosit Hep
System Contents System Generation]
— Clock Setings
terface Protocols * a
“5 ASI Device Famiy|cycione | (name aa = a
c5-Ethernet Remove
is-High Speed iclk_0 [External '50.0 ean
ce-PCl
£5-Seria
cp-Legacy Components
E-Memaries and Memory Control= ||use Cone... Module Name Desertion Clock Base End
c5-DMA,
co-Flash wl i epuo Ios t Processor
©-On-Chip instructionmaster [Avalon Memory Mapped Master emo
© Avalon-ST DualCI data_master [avalon Memory Mapped Master me
® Avalon-ST Mutti-C’ jtag_debug_module jAvalon Memory Mapped Slave ‘ex00000800 [0x00000
2 Avalon-ST Round w © tag_uart_o lac uaRT
© AvalonST Single avalonfag_save [Avalon Memory Mapped Slave ‘emo ‘exao0e000e [000000
© On-Chip FFO Men 7 El onchip_memory2_0 [On-chip Memory (RAM or ROM)
Efon-crip Memory (Bg st [avalon Memory Mapped Slave emo ‘9x00002000 [000002
«ft .
‘ i J ,
New...} Esit Add. Remove cit A Move Up Move Down [Address Fiter..._|
(D To Do: epu_0: No reset vector has been specified for this CPU. Please parameterize tie CPUto resolvethisissue
© ToDo: epu_0: No exception vectorhas been specified for this CPU. Please parameterize the CPUto resolvethis issue
Bat Hep (rev (Net D Generate
Hinh1.2.6. add cic module cin thiét

Dé két néi cpu_0 véi onchip_memory2_0 lai véi nhau, ta can chi ra dwong dan
cho cpu_0 di dén. duéng dan nay duge thé hign trong hinh 1.2.7.

ee
"2NiosIPracessor~cpu. Ss
Nios II Processor
Sree
Core Nios Il
Select atlios ll core:

ONios Ive ON ONios IA
F isc RISC Rise
Nios Il sz S2-be sabe
Selector Guide Instruetion Cache instruction Cache
Font Oeionel: Branch Prediction Branch Prediction
Hardware Muttiply Herelware Mutiny
feystem: 50.0 MHz Hardware Divide Hardware Divide
dames Barrel Shifter
Data Cache
Dynamic Branch Prediction
Performance at 50.0 MHz Up to S DMIPS 250MPSupto st ups
Logie Usage ‘600-700 Les 4400-1800 LES
Memory Usage Two Maks (oF equiv) Three MAK+ cache
Hardware Multiply: Empedctect Muttipliers +) [Hardware Divide
Reset Vector: Memory: | onchip_memory2_0 Offset: /ox0 ‘9x00002000

Exception Vector: Memory onchip_memory2_0 =) ottset [0x20 ‘0002020
Include MMs
nly include the MMU when using an operating system that explcly supports anMM
Fast TLB Miss Exception Vector: Memory: Offset:
Ineuele MEU
Hinh1.2.7. lign két cpu_0 véi onchip memory2 0
Xong céngviéc thiét ké mt hé théng, chungta bién dich lai chongtrinh bang
cach click vao button Generate dé biét xem trong qué trinh thiét ké cé sai xét gi khéng.
Quétrinh bién dich thanh céng duge thé hién & hinh 1.2.8.

rayiergrerasaiar
Options
System module logic will be created in Verilog.
{-] Simulation. Create project simulator files. Run Simulator
Nios Il Tools
Tira, Tse was: verors, 0
Info: Peak virtual memory: 70 megabytes:

Info: Processing ended: Tue Dec 02 13:51:56 2008
Info: Elapsedtime: 00:00:01
Info: Total CPUtime (on all processors): 00:00:01
# 2008.12.02 13:51:56 (*) Completed generation for system: unnamed.
# 2008.12.02 13:51:56 (*) THE FOLLOWING SYSTEM ITEMS HAVE BEEN GENERATED:
SOPC Builder database : C:/altera/31 /quartus/lap2/unnamed
‘System HDL Model : C:/altera/S1 2/unnamed.v
System Generation Script : C:/altera/81 /quartus/ap2/unnamed_generation_script
# 2008.12.02 13:51:56 (*) SUCCESS: SYSTEM GENERATION COMPLETED. [2
(Leet) (Latics) [gdurrens) [vet > | (generate)
Hinh1.2.8. bién dich thanh cong
Bién dich thanh céng, dé tiép tuc chwongtrinh thiét ké hé thong ching ta quay
lai voi ctra sé chinh cua QuartusII trong hinh 1.1.1 va gan pin cho hé théng theo hinh
1.2.9.
File Edit View
D or dl et | & | % Device... Wk # SVS Oly Fes |\sslh |S| S| ale

Project Navigator SP Bins
84 Timing Analysis Settings...
Cyclone I: EP2C35F67_.| 2% EDA Tool Settings...
» lap2? # Settings... (Ctrl+Shift+E
Classic Timing Analyzer Wizard...
@ Assignment Editor Ctrl+Shift+A

2 Pin Planner Ctrl+Shift+N
Remove Assignments...
fe Demote Assignments...
I Back-Annotate Assignments...
Assignment (Time) Groups...
&% Timing Closure Floorplan

@ LogicLock Regions Window Alt+L
85 3) Design Partitions Window Alt+D
Hinh 1.2.9. Gan pin

Sao khi gan pin xong, ching ta bién dich lai chong trinh métlan nia trong
Quartus II dé hé thong lién két lai véi nhau. Quatrinh bién dich thanh céng dugc thé
hién trong hinh 1.2.10.
=Pas c/altera/81/quartus;eae= ceiiee ene Flow —
w Project Assignments
D aw a Ea I M’“EVS |G
Project Navigator ax
@c ion Report - Flow Summary |
Entity Dedicated Logic =
C lation Report Flow Si
& CycloneIl: EP2C35F672C6 FSI Compilation s oe SS
fee ee i BB Legal Notice
He, lapAy 215943) [1321 (0) BEDI Flow Summary
BEB Flow Settings
> GBEB Flow Non-Default Global Se Flow Status Successful - Tue Dec 02 14:07:14 2008
EB Flow Elapsed Time Quartus {| Version 8.1 Build 163 10/28/2008 SJ Web Edition
GED Flow 05 Summary Revision Name lap3_1
4B Flow Log Toptevel Entity Name fap3_1
t#]-€§000) Analysis & Synthesis Family Cyclone Il
ZG i iH Sp Fitter Device EP2C35F672C6.
a - —_ 00 Assembler Timing Models Final
@yHierarchy E Files a? Design Units a pG Timing Av “ = a os
juartus [een] ¥
Tasks ax 2,159/33,216(6%)
Howe =—ti“‘C;CS*”*”*”*”*”*”*”*”*”*”*”*”*~;CY - al Functions 2.018 /33.216(6%)
ist 1,321 /33.216(4%
a fea] @ Full Compilation was successful (486 wamings) jee eae ($0)
wl & Compile Design |o0-02:02| - 6/475(1%)
wv & Analysis & Synthesis |00:00:53] 0
w Fitter (Place & Route) 00:00:44 78,080 / 483,840 (16%)
wv Assembler (Generate programmingfiles} |00:00:10| Shit elements 4/70(6%)
vw Bt Classic Timing Analysis 00:00:09) Total PLEs 0/4(0%)
I~ EDA Netlist Writer
{YW Program Device (Open Programmer)
a I FE m '
- Type Message
Le iD Info: tsu for register "“pzdyqu:nabboc|pzdyqx_impl:pzdyqu_impl_inst|VELJ8121: nigh abe amen (data nae = “altera_internal_jtag~SHIFIUSEI
Bw internal_jtag~TDO” to destinati
BW t|sidshadowjsm:shadow|
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Hinh 1.2.10. QuartusII bién dich thanh céng
Xong qua trinh thiét phan ctmg. Dé diéu khién dugc hé théng trén, Nios II IDE
sé cho phép chungta lap trinh diéu khién toan bé hé théng ma chingta vira thiét ké.
Quay lai voi SOPC Builder sao khi bién dich thanh cong,click vao button Nios II IDE
dé thuhién viéc lap trinh. Hinh 1.2.11 sé cho chungta dugc nhin r6 hon van dé nay.

& Altera SOPC 6) IIB Nios I C/C++ - Nios TIDE

File Ecit Module File Edit Navigate Search Project Tools Run Window Help ee
SystemContents 4~ @~ ~~ G~ H-O-rQ-~i: 8 # fa ~ He Pe © Nosicic=|
6piiogs BB Nios 1C/C++ Projects £2 aa = || @Make Targets 23 =O
‘System moduleIo| le & -
a&
Simulation z
[eS altera.components
#2008.12.021
# 2008.12.02 1
SOPC Builder
System HDL N
System Genet
# 2008.12.021
|@ Info: System ga
«i
(@ info: No errors
fi. Problems £2 Console) Properties te

0 errors, 0 warnings, 0 infos
Hinh 1.2.11. lap trinh Nios II IDE
1.3 Phan Mém NIOS II IDE
Day 1a chuong trinh bién dich ng6én ngit lap trinh C va download chung vao
trong chip Nios II. Né chon hé théng SOPC gém co: bé nhd, b6 dém va nhiéu va
chon khac dé bién dich, debug va chay chuong trinh C. JTAG UARC ding dé
download file C téi chip NIOSII. NIOS II IDE cé métnew project wizard ding dé tu
déng cai dat project ing dung C/C++ va project thu vién hé thong. hon nia, NIOS II
IDE cung cép ma phan mém vi du( trong dang project khuén mau)dé hé tro cdc k¥ su
phan mém 1am viéc véi hé théng nhanh nhat cé thé. Mi khu6n méau1a lwa chon file
phan mém va thiét lap project. Ngudi thiét ké cd thé thém m4 nguén cuariéng ho vao
project bang cach thay thé code vao trong thu mucproject hodc import file vao trong
project. Dya trén chudn céng nghiép chudi céng cu JNU, NIOSII cungcap giao dién
ngwoi ding dé bién soan. Méi trudng xdy dung NIOSS II IDE dugc thiét ké dé thuan
tién phat trién phan mém cho bé xir ly NIOS II cua ALTERA mién 1a dé ding Push-
Button. Mac da ciing cho phép nguoi thiét ké xdy dumg cac thiét lap cao cap bangtay.
Méitruéng x4y dung NIOS II IDE cung cap mét makefile dya trén cau hinh hé thong
cu thé(file SOPC Builder GENERATE PTF). Thay d6i thiét lap trinh bién dich/méi
lién két trong NIOS II IDE dugc lam ty déng trong make file nay. Thiét lap nay cd thé

bao gdm tuy chon chofile khdi tao bé6 nhé(MIF), ndi dung flash, file khoi tao m6
phéng(DAT/HEX), va file tom tat profile.
NIOS II IDE chira debug phan mém dia trén debug GNU, GDP. Debug cung
cap nhiéu tinh nang debug co ban, ciing nhu cdc tinh nang debug khac thuong 1a
khong c6 san trong cac kit phat trién bd xi ly gid thap. Hoadt dong chay debug dugc
cung cap san bang cach click phai vao project. NIOS II IDE cho phép ban chay hoac
debug project trén board muc tiéu hoac tap lénh mé phdong NIOS II(ISS). Mdéi img
dung c6 thu vién riéng cua n6. Thu vién nay chita file lién quan tdi hé thong x4y dung
cia SOPC Builder. N6 c6 thé thuc hién lua chon b6 nhé ng6 vao, ngd ra va bd dém
cho tmg dung. Cé nhiéu tiy chon ctia bién dich va chay chuongtrinh. No thi rat hitu
ich cho luan diém project nay ”tiy chon thu vién C nhd”. Khi “tay chon thu vién C
nho” duoc chon, thu vién hé thong ding b6 xung giam bét cua thu vién chuan Newlib
ANSI C. dat bigt, ho prinfQ) cua thu tuc(prinfQ), fprinfQ, sprinfQ) gia tri con tré thay
d6i khi tuy chon nay duoc check.
L3.1 T.ong quan cac tinh nang cia bé vi xu ly NIOS IT:
NIOSII 1a m6t bé vi xt ly mém cé mét sé tinh nang cé thé cau hinh phu hop
voi ngudi ding dé tao ra mét hé thong mong mudn duge xt ly cé thé cung cap cong
cu trong ba cach cé thé cau hinh khac nhau.
NIOSII/“fax” due thiét ké cho viéc thuc thi manh. No cé nhiéu tuy chon dé cau hinh,
cé thé dugc str dung dé t6i wu cho bd xt ly thuc thi.
NIOSII/S 1a mét phién ban “chuan”, phién ban nay yéu cau nguén tai nguyén thap
trong mét thiét bi FPGA thich hgp chocdc thuc thi don gian.
NIOS IVE 1a m6t phién ban “kinh té”, phién ban nay yéu cau nguén tai nguyén thap
nhat cua thiét bi FPGA nhung né ciing cé nhiéu gidi han nhat dé thiét 1ap cdc tinh
nang ma nguwoi str dung cé thé dung.
Bo xi ly NIOS II 1a kién tric maytinh thiét lap cdc tap lénh don gian(RISC),
cac hoat dong sé hoc logic cua no dugc thi hanh trén cac toan han trong cac thanh ghi

da nang. Dit liéu duoc di chuyén gitta bé nho va cac thanh ghi nay theo muc dich cua
lénh load vastore.
D6 dai cia b6 xu ly NIOS II 1a 32bit. Tat ca cdc thanh ghi cd d6 dai la 32 bit,
cac byte dia chi trong 32 bit c6 thé dugc gan trong kiéu little-endian hodc kiéu bit-
endian. Cac kiéu gan nay la mét trong nhimg tiy chon ma nguwdi str dung cé thé lua
chon dé cau hinh thoi gian. Kién tric NIOSII ding dé tach roi cdc bus tap 1énh vadit
liéu. cai nay thudng lién quan téi kién trac phan cimg.
Mot b6 xt ly NIOSII co thé hoat dong trong ba ché d6 sau:
> Ché dé gidm sat: cho phép bé6 xt ly thi hanh tat ca cdc tap 1énh va thuc hién tat
ca cdc ham co san. khi bd xt ly reset, nd sé di vao ché d6 nay.
> Ché dé ngudi ding: ngan ngira viéc thuc hién mét vai tap lénh dung cho hé
thong muctiéu. Mét vai tinh nang cua b6 xu ly khéng sit dung dugc trong ché
do nay.
> Ché dé debug: dugc str dung béi cdc céng cu debug dé thuc hién cdc tinh ning
nhu diém ngat va diém theo déi.
Cac chuongtrinh img dung cé thé chay trong ché d6 ngudi ding hoac ché dé giam
sat. Cac phién ban c6 san hién gid cua bé xit ly NIOS II khéng hé tro ché d6 ngudi
dung.
1.3.2 Cau Triic Thanh Ghi

Bo xt ly NIOSII c6 32 thanh ghi da nang c6 32 bit, mdt vai thanh ghi duoc
gianh cho mét muc dich cu thé va co tén riéng. No duge thira nhan bdi chuong
trinh dich hop ngit.
> Thanh ghi RO duge xem nhu 1a thanh ghi zero luén lu6én chwa gia tri khong
ddi 1a 0.
> Thanh ghi R1 duoc st dung boi chuongtrinh hop ngit nhu mét thanh ghi
tam thoi. No khong duoc str dung cho chuongtrinh nguwoi ding.

> Thanh ghi R24 va R29 duoc sir dung xt ly cdc ngoai 1é. ching khong cé san
trong ché d6 ngudi dung.
> Thanh ghi R25 va R30 duoc sir dung gianh riéng cho ché d6 debug JTAG.
> Thanh ghi R27 va R28 ding dé diéu khién Stack.

> Thanh ghi R31 duoc str dung dé git gid tri tra vé khi m6t chuong trinh con
duoc goi.
Thanh ghi Tén Chic nang
r0 zero 0x00000000
rl at Chuongtrinh dich hop ngit tam thoi
r2
r3
123
124 et phan déi tam thoi (1)
125 bt diém ngat tam thoi (2)
126 gb con tré toan cuc
127 sp con tro stack
128 fp con tré khung
129 ea dia chi tra vé ngoai1é (1)

630 ba dia chi tra vé diém ngat(2)
r3] ra dia chi tra vé
(1) thanh ghi khong cé san trong ché d6 ngudi ding
(2) thanh ghi chi ding trong ché d6 debug JTAG
Bang I Cac Thanh Ghi Da Nang
Cac thanh ghi nay duoc str dung tu déng cho muc dich diéu khién. ching cé thé
doc va ghi bang cac lénh riéng biét rdctl va wrdctl, cdi nay chi cd thé thuc hién cho
muc dich giam sat. Cac thanh ghi dugc str dung nhusau:
> Thanh ghi ctl0 tuong tng voitrang thai hoat déng cua b6 xu ly. Chi co 2bit
cua thanh ghi nay co y nghia:
e U la bit ché dé ngudi ding/gidm sat. U=1 1a ché dod

ngudi dung, U=0 1a ché dé giam sat.
e PIE 1a bit xt ly enable ngat. PIE=1, b6 xi ly cé thé

chap nhan ngat bén ngoai. PIE=0, bé xt ly bd qua ngat
bén ngoai.
Thanh ghi ctll git ban sao luu tri cua thanh ghi trang thai trong qua trinh
xu ly ngoai 1é. bit EU va EPIE ding dé luu trit cdc bit trang thai U va PIE.
Thanh ghi ctl2 luu giit ban sao cua thanh ghi trang thai trong quatrinh xu ly
ngat debug. Bit BU va BPIE luu gia tri cua bit trang thai U va PIE.
Thanh ghi ctl3 dung dé enable riéng ngat bén ngoai. M6ibit tuong tng mét
ngat irqO toi irq31. Gia tri 14 1 cé nghia 1a ngat enable, 1a 0 thi né disable.
Thanh ghi ctl4 chi ra ngat dang cho. Gia tri cua bit nhan dugc, ctl4, duoc set
la 1 néu ngat irqk thi ca 2 active va enable bdi bit ngat enable, ctl3, set dén
1.
Thanh ghictl5 gitr gid tri nhan biét xi ly duy nhat trong hé thong da xu ly.

Thanh ghi Tén b31.......b2 bl bO
ctl0 status Danh riéng U PIE
ctll estatus Danhriéng EU EPIE
ctl2 bstatus Danh riéng BU BPIE
ctl3 ienable Bit enable ngat
ctl4 ipending Bit cho doi ngat
ctl5 cpuid Nhan biét b6 xt ly duy nhat
Bang 2 Thanh Ghi Diéu Khién
1.3.3. Truy Xuat B6 Nhé Va Thiét Bi I/O

Dé thuc thi tot nhat, bd xt ly NIOS II/F cé thé bao gém ca hai b6 nhé dém tap
lénh va dir ligu. b6 nho dém dugc thuc hién trong khéi b6 nhé FPGA,cach str dung
cia ching la tay y va ching duoc chi dinh (bao gém kich thudc cua ching) 6 thoi
gian khdi tao hé thong bang cach str dung SOPC Builder. Phién ban NIOS II/S cé
thé cd b6 nhé dém tap lénh nhung khong co b6 nho dém di ligu. phién ban NIOS
II/E khéng co bé nho dém tap 1énh va dit ligu, ndi cach khac dé bé xu ly truy xuat
nhanh dén b6 nhé trén chip bang cach su dung két hop chat ché ca hai bé nho,
trong trong hop nay bé xt ly truy xuat bd nhé qua dudng dan chi ra tt hon qua
mang luéi Evelon. Truy xuat dén b6 nhé két hop chat ché bd qua bé nhdém. cd
thé cd mét hodc nhiéu bé nhé tap 1énh vadit liéu két hop. Néu b6 nhé dém tap lénh
khong bao gém trong hé thong, khi d6 phai co it nhat mét b6 nhé ket hop dugc
cung cap cho bé xir ly NIOS II/F va NIOS II/S. B6 nho onchip cing cé thé dugc
truy xuat qua mang lwéi Evelon. Thiét bi b6 nhé offchip nhu chip SRAM, SDRAM
va bé nhé flash cé thé dugc truy xuat bang giao dién thich hop. Thiét bi I/O dugc
Map bé nhé cé thé truy xuat nhu xac dinh truy xuat b6 nhé. Dit liéu truy xuattéi vi
tri b6 nhoé va giao dién I/O dugc thyc hién gianh cho lénh load vastore, di li¢u
dugc chuyén déi bé nhé va thanh ghi da nang.

General purpose
Instruction bus selector logic Data busselector logic
Instruction Data
cache cache
Avalon switch fabric
Tightly coupled Memory vo Tightly coupled

instruction memory interface interface data memory
Memory VO
device device
Hinh 1.3.1 T6 Chive B6 Nhé Va VO
1.3.4. Dia Chi.
Bo xu ly NIOSII dua ra dia chi 32bit. Khong gian b6 nho 1a 32 dia chi cho
phép. Cac lénh cé thé doc va ghi dit liéu word(32bit), halfword(16bit), hoc byte
8bit. Viéc doc va ghi mét dia chi khong tuong img vdi mét b6 nhé dang ton tai
hoac vi tri I/O cho ra métkét qua khéng xac dinh. Cé nam ché dé dia chi dugc dua
Ta:

> Ché dé titc thdi: mét toan han 16bit dugc ghi vao tap lénh. Gia tri nay cé
thé mo rong dé cho ra mét todn han 32bit trong tap lénh ma thuc hién
cac phép toan sé hoc.
Ché d6 thanh ghi: toan han trong thanh ghi xt ly.
Ché dé thay thé: dia chi dang tén tai cua toan han duoc cong vao ndi
dung cua mét thanh ghi vao m6tgia tri thay thé 16bit ghi vao trong tap
lénh.
Ché d6 thanh ghi gian tiép: dia chi dang tén tai cua mét toan han 1a ndi
dung cua mot thanh ghi dugc chi dinh trong tap lénh.
Ché dé tuyét déi: mOt dia chi tuyét d6i 16bit cha mét todn han cé thé
duge chi dinh bang cach dung ché d6 thay thé voi thanh ghi RO luén
luén cé gia tri bang 0.
3.5. Tap Lénh
Tat ca cac lénh cua NIOS Il cé d6 dai 32bit. Cac 1énh nay duoc thuc hién truc
tiép bdi b6 xtr ly. Cac lénh NIOSII bao g6m méts6 caclénh gia c6 thé duoc ding
trong ng6n ngit lap trinh hop ngit. chong trinh bién dich hop ngit thay thé cac 1énh
gia bang m6t hoac nhiéu cac lénh may. Co ba Jénh cé thé dinh dang: kiéu I, kiéu R
va kiéu J. Trong tat ca cdc trudng hop B[5:0] ding cho OP code. Cac bit cén lai
dugc str dung cho thanh ghi chi dinh, toan han tic thoi hoac OP code mo rong.
> kiéu I: 5 bit A va B duge sit dung dé chi dinh thanh ghi da nang 16bit
IMM 16 duara dit liéu tic thoi cd thé mo rong cho ra toan han 32bit.
> Kiéu R: 5 bit A, B va C chi dinh thanh ghi da nang. 11bit OPX ding dé
mo rong OP code.
> Kiéu J: 26 bit IMM26 chia gia tri Unsign tic thoi. dinh dang nay chi
dugc dung trong goi lénh.

ee
31 27 26 22 21 6 5 0
A B IMMED 16 OP
(a) L-type
31 27 26 22 21 17 16 6 5 0
A B c OPX OP
(b) R-type
31 6 5 0
IMMED26 OP
(c) J-type
Hinh 1.3.2 cdc dinh dang cilia cic tap lénh NIOS IT
1.4 Board DE2
4.1, Tinh ning cia mech DE2
Tinh ning cua mach DE2 1a chip Cyclone® II 2C35 FPGA trong goi pin 672.
Tat ca cdc thanh phan quan trong trén mach duge két néi véi cdc pin cua con chip nay,
cho phép ngwii sir dung didu kién tat cd cdc b6 phan bén ngoai cua qué trinh hoat déng
cua mach. Cuéc thir nghiém don gian, mach DE2 bao gém mé@t sé kha ning cua
switches, LEDsva hién thi 7 doan. Cuécthi nghiém cao hon c6 SRAM, SDRAM,va
chip bé nhé Flash,ciing nhu hién thi ky ty 16x2. Nhitng cuéc thi nghiém phy thudc
vao b6 xit ly va giao dién VO don gidn. Didu nay thi dé dé dign gidi cho b6 xi ly
Altera’s Nios II va str dyng giao dién chudn nhw giao dién chudn RS-232 va PS/2.
Cuéc thi nghiém bao gém tinh higu am thanh va video, cé bé két néi chudn nh1a
microphone,line-in, line-out (24-bit audio CODEC), video —in (TV Decoler), va VGA
(10-bit DAC); Nhiing tinh nang nay c6 thé duge sir dung dé tao ra tng dung audio
CD-quality. Dy 4n thiét ké DE2 lén hon cung cap két néi USB 2.0 (ca may chu va
thiét bi), 10/100 Ethernet, va céng héng ngoai (IrDA) va mét két ndi thé nhé SD. Néi
tom lai, né c6 thé két ndi khdc do ngudi ding qui dinh téi mach DE2

ee
Hinh 1.4.1 Board DE2
1.4.2, Théng sé kj thugt

50Mhz / 27Mhz/ Extin
¥v
USB 2.0 Host/Device Mj—>| 16-bit Audio CODEC
10/100 Ethernet Phy/MAC ———} VGA 10-bit Video DAC
SD Card j——| TV Decoder

Cyclone Il
IrDA Transceiver §——- E PGA —<—$<—<$$| User Green LEDs (8)
Flash (1 Mbyte) e— 9C35 p———e| UserRed LEDs (18)
SDRAM (8 Mbytes) ad P| 16x 2 LCD Module
SRAM (512 Kbytes) — +—_>| PS2 & RS-232 Ports
T-SegmentDisplay (8) a Md—} Toggle Switches (18)

Expansion Headers (2) — — Pushbutton Switches(4)
=]
IEE
Hinh 1.4.2 Biéu Dd Khéi Cia Board DE2

FPGA
> Cyclone Il EP2C35F672C6 FPGA va EPCF16 vathiét bj cau hinh serial
Thiét bj YO
> Dugc xdy dung trén USB Blaster cho FPGA
> Céng Ethenet1 0/100 RS-232, céng héng ngoai
> Video-out (VGA 10- bit DAC)
> Video-in (NTSC/PAL/ Multi format)
> USB 2.0kiéu A kiéuB

> Céng PS/2 cho chuét va ban phiém
> Line-in, line-out, microphone-in, 24bit audio CODEC
> Moréng phan dau(76 chan tin hiéu)

ee
Memory
> 8 MB SDRAM,512 KB SRAM,4 MBFlash
> Khe cam thé nhé SD

Switches, LEDs, Displays, and Clocks
> 18 switch
> 4 mit dn debuonced switch
> 18 LED dé, 9 LED xanh
> 8 hién thj 7 doan
> Hién thi LCD 16x2

> Bé6tao dao dng 27MHz va 50 MHz, ngé vao clock SMA bén ngoai.
Hinh 1.4.3 cha board DE2 chi ra cach bé tri va vi tri chi dinh cla cdc thanh
phan trén board DE2.
UsB Usa USB Ethernet

Blaster Device Host Mic Ling Line Video VGA Video 10/00M
Pot Pot Pot in in Ga In Post Port RS-232 Port
Lert Litt 1 ! J
27-Mtz Oscar rR
24-04 Audio Codec }
Poner ON/OFF Smiter => PS/2 Keyooard/Mouse Port
VGA {Obit DAC
USB HostSiave Contraller
Eternet 10/100M Controier
TV Decoder (NTSCIPAL)
Expansion Header 2.(.P2)
Aliera USBBlaster Controller Chipset
m Expansion Header 1 Pt)
Altera EPCS! Configuration Device
Alera Cyclone IIFPGA,
RUN'PROGSwitch for JTAGIAS Nodes
6x2 LCD Module
‘80 Card Siot
7-Segmert Displays 8 Green LEDs

1 Red LEDS lFDA Transeaivat
‘SMA Extemal Clock
18 Toggle Switches
4 Debouncad Pushbution Switches
S0-MHz Oscillator BAMBSORAM 512-48 SRAM 4.MB Flash Namery
Hinh 1.4.2. Board DE2 cija Altera.

Board DE2 cé nhiéu dic diém cho phép ngudi siz dung cé thé thiét ké va thuc
thi cdc machtir don gian dén phitctap.
Sau day 1a cdc phan cimg duoc board DE2 cungcap:
> Altera Cyclone II 2C35 FPGA.
Altera Serial Configuration device-EPCS-16.

WV
Cac céng USB.

VW
SRAM 512 Kbyte.

VW
SDRAM 8 Mbyte.
VW
Flash memory 4 Mbyte.

VW
SD card socket.
VW
4 SW nhan.
VW
18 SW day.
VW
18 LEDsdo.
9 LEDs xanh.
VV
Clock source dao d6éng S5OMH va 27 MHz.

Vv
24 bit CD-quality audio CODEC v06i cac jack line-in,line-

Vv
out,microphone.
VGA DACv6idau két noi VGA-out.

WV
TV Decoder va dau két néi TV-in.

WV
Céng Ethenet 10/100.

VV
Céng RS232 9 pin.

Céng SP/2.
Vv
Céng hong ngoai IrDA.

Vv
2 Expension Heard 40 pin.

Vv

1.4.3. Nhieng Vi Du Vé Nhitng eng Dung Cao Cap

Mach DE2cé thé duge str dung dé thuc thi nhimg phan loai r6ng cua nhitng du
an thiét ké.
Ung dung TV box
ry
Video ln
7 Line Out
Line In ———_——S= =
CVBS VGA Out

S-Video
YPbPr
Output
VGA (LCD/CRT) Monitor

YCbCr (YUV)
to
RGB )
Hinh 1.4.3 Ung Dung TV Box

> Giai ma TV chat luong cao
> Chat luong CD 4m thanh 24 bit
> Man hinh VGA
> Dungtiéu chuan cho tng dung cho video
> Tat cd ma nguéndriver phan mém cho Nios® II
USB Mouse Paintbrush
> Su dung céng USB 2.0 trén mach DE2

VGAOut .
USB Device
ORS =} VGA
DE2 Board
Driver Controller
=
SRAM
Video www.terasic.com
FrameBuffer
VGA Monitor
Hinh 1.4.4 USB Chuot Paintbrush
> Phan mém USB maychi va thiét bj cho Nios II
> Cung cap vi du cia bé dém video SRAM
Karaoke Machine va SD music player
MP3/Any Audio Output Speaker
Speaker
_— §j— 8D Card
See: With music
RIPPER eRe
F ado : files(WAV)
Microphone
ep ae ebeihh
BFL
Frequency
Controller
Generator
Hinh 1.4.5 Karaoke Machine va SD Music Player
> CD chat lugng 4m thanh 24 bit

> Ding tiéu chuan cho tng dung audio
> Tat cd ma nguéndriver phan mém cho Nios® II

Chuong IT
Audio Codec W8731/L
11.1 Giéi Thigu Ve AUDIO CODEC W8731/L
WM8731 la mét audio CODEC cong suat thap duoc thiét ké dic biét cho san
pham audio linh dong. No tién loi va tiéu thu dién 4p thap pha hop cho y tuéng tao ra
nhiing san pham MP3 Player va Mini-disc Player.
CODEC bao gém nhitng duong va ngd vao microphone téi ADC on-board,
dudng va ngé ra headphone tir DAC on board, mét may tao dao déng, dinh cau hinh
giao dién digital audio va lua chon giao dién diéu khién 2 hay 3 day MPU. No hoan
toan tuong thich la mdt y tudéng két hop cho mot phan cua b6é vi xu ly, mach diéu
khién, va DSP chuan cong nghiép.
CODECbao gom 3 loai tin hiéu vao — mono microphonevastereo line. Line tin
hiéu vao cé thé diéu chinh cp d6 4m thanh ti +12dB téi -34dB va mute. Tin hiéu vao
microphone co thé diéu chinh ti -6dB dén 34dB. Tat ca quy dinh b6 loc tin higu vao
duge chira vao trong thiét bi khong cé thanh phan bén ngoai quy dinh.
BO chuyén déitin hiéu tuong ty sang tin hiéu s6 trén 4m thanh ndi on-board 1a
chat luong cao dung nhiéu bit bac cao trén viéc mau cau trac phan phdi thuc thi tét
nhat ma tiéu thu nang lvong thap. Tin hiéu ngé ra tir ADC cé san trén giao dién audio
tin higu so. ADC bao gdm mottin higu so thy chon cao qua b6 loc tdi
ADC bao gém mottuy chon sé ding gd bd phan khéng cAnthiét tir tin hiéu
audio.
Bo chuyén déi tin hiéu sé sang tuong tu on-board chap nhan tin hiéu s6 audio
tir giao dién tin hiéu sé audio. B6loc tin hiéu sé 6 32 kHz, 44.1 kHz, 48 kHz cé thé ap
dung dir liéu tin higu so dudi dang phan mém diéu khién. DAC tan dung kiéu cau trac
oversampling da tang - kha cao- c6 chat luong tét dé thuc hién céng viéc véi hiéu suat
tot nhat malai tiéu thu it nang luong

Tin higu ra DAC, microphone (SIDETONE) va Line ngé vao (BYPASS) duge
cung cap san ca 2 mirc line va m6t b6 khuéch dai 4m thanh headphone. Am luong tin
hiéu ra headphoneco thé diéu chinh trong tin hiéu tuong ty 6 mic +6dB dén -73dB va
co thé mute.
Thiét ké WM8731/L phai chu y nhiéu dén tiéu thy dién ning ma khéng anh
huong dén hiéu suat. No bao gdm viéc khéoléo trong Ilya chon tat dién nang cia mach
dudi dang phan mém diéu khién, lam nhu thé dé bao tén dién ning. Cach luu nang
luong khac la dinh dang trong phan mém diéu khién bao gdm ché dé standby va tat
nguon. Ky thuat dic biét cho phép audio cé thé bi mute va thiét bi dat trong tinh trang
standby mdotcach an toan, phan thiét bi duoc tat nguon va mirc 4m thanh dugc tu diéu
chinh. Vi thé ché d6 standby va poweroff cé thé dugc tan dung trong phan mém diéu
khién, bat ctr khi nao dang ghi 4m hay dang nghe ma khéng can dén.
Thiét bi phuc vu cho téc d6 mau khac nhau bao gom cac chuan 8kHz, 32kHz,
44.1 kHz, 48 kHz, 88.2 kHz va 96 kHz. Ngoai ra, thiét bi c6 mét ADC va DAC céthé
hoat dong @ t6c d6 mau khac nhau. Co 2 su phéi hop duy nhat dic trung trong téc dé
mau duoc lap trinh cua WM8731/L. Chuan thong thudng 1a tic d6 256/384fs co thé
dugc ding, véi kha nang thém vao téc dé lay mau khac. Hon ntta ché d6 USB diacbiét
dugc bao gém bén trong, nho do tat ca toc d6 mau audio cé thé dugctao ra ty xung
clock USB 12.00MHZ. Theo cach do, vi du, DAC cé thé ghi vao DSP 6 toc dé
44.1kHz va chaylai tir CODEC véi téc dé 8kHz ma khong can phu thudc vao tién
trinh xir ly tin higu sé bén ngoai. Bd loc ky thuat sé str dung ghi va nghe lai khach
quan cho mditéc d6 dugc str dung. Ngé ra ky sé hoa san co trong mét sé dinh dang dit
liéu audio ché d6 128, DSP, MSB-First, left justified va MSB-First, right justified.
Giao dién audio s6 cé thé hoat dong ca 2 ché d6 Master hodc Slave.
Phan mém diéu khién st dung giao dién MPU 2 hoa3- Wire.
Maytao dao dong duoc bao gém trén board cua thiét bi. Thiét bi cd thé tao ra
hé thong master clock hoadc né cé thé chap nhan m6t master clock bén ngoai tt hé
thong audio.

MODE
SCLK
SDIN
sa
CONTROLINTERFACE ‘WM8731
VMID
AGND © .
4610 7308
aT 4 4B Steps, Reg Ch
vou WP
* rap MUTE DRIVER
MIGBIAS 7+#—— q
RLINEIN b + VOL I
DAC me me PE}
1210 SEB, 1 55 Steps,
eg OB — L—_/ Gaoame Siocroe
5 Regdah Rag Oh
MICIN ¢ [> oar
maa 3 DIGITAL a
2 FILTERS é
NIC BOOST ReCeh] DaCMUTE
egOth SDETONE
fag 8h ———*
DAG)» wuTe ou
LLINEIN§ G-—) vot
#12 19-34 508, 15dSop, eott
LLINEIN ute “THSEL, Regan ( ‘f4 vou |
MUTE
HP
RIVER
Peg oth sear, | [
Reg Qth ff 46 0 TS
[arrew
mre | aeBaps eg th
cxseo
heath : WIE j
eee rat x tY |
ose 1 DIGTAL AUDIO INTERFACE Bypats, Reg 08h
’ | Sees, ,yo ooo

x3 = 8@ 5&
@R 8 52 a8 S35 §3 @8 6 8s
Ba 8s
28 2&
= gF 2a 8 g 8a 4 = Bs
Hinh 2.1.1 So Bd Khéi Chite Nang WM8731/L
4.1.1 Duong Dan Line Input

WM8731/L cung cap 2 line tin hiéu vao trai va phai (RLINEIN va LLINEIN).
Nhiigtin hiéu ngd vao cé tré khéng cao va cé dign dung thdp. diéu nay phi hgp voi
nhan tin hiéu 6 mite Linetir thiét bj hi-fi hay audio bén ngoai.
Ca hai Line ngd vao cé thé lap trinh déc lap diéu chinh mic d6 am thanh va
ngé vao ADC mute. Luge dd duge mé ta trong hinh 2. Bé loc bj dgng RF va béloc
tich cyc Anti-Alias thi két hgp chat ché véi nhau trong Line ngd vao. Diéu nay ngin
can alias tin s6 cao vao trong bing tan audio hay lam giam gidtri thyc hién.
SVTH: NGUYEN MINH HIBU - HUYNH CONG PHU Trang 38

ee
To
ADC
Hinh2.1.2 Lirge Dé Line Ngo Vao.

Két qua thu duge gitta Line ng3 vao va ADC A cé thé diéu chinh tir +12dB dén
-34.5dB. ADC lam giam ngé vio AVDD ti 3.3V xudng 1V. Bat ky dién thé lon hon
lam giam xudng sé cé thé lam tran ADC vavi thé khéng chinh xdc. Chi y viéc lam
giam ngé vao phai kiém tra AVDD ngay lap tic. Tuy nhién, bang cach dat bit
INBOTHtrongkhi Jap trinh digu khién 4m thanh, ca 2 kénh duge cap nhat déng théi
véi gid tri trong ty. Line ngé vao dén ADC cé thé mute trong vingtin hiéu trong tr
dudi dang diéu khién phan mém. Chi y Line ngé vio Mute chi Mute ngé vao dén
ADC,diéu nay cho phép tin higu Line ngé vao di qua ngé ra trong ché d6 ByPass.
Register
address
Bit Nhan Mac Dinh Phin Mé TA
Left Channel Line Input
Volume
0000000 ; a, {10111 Control
LeftLineIn [#9 UINVOLI4:0] (ga3y tyi11 = +1248 . . 1.543
steps down
to 00000 = -34.5dB
7 1 Left Channel Line Input

Mute to ADC
LINMUTE 1 =Enable Mute
0 = Disable Mute

8 0 Left to Right Channel Line

Input
Volume and Mute Data
Load Control
1 = Enable Simultaneous
LRINBOTH Load of
LINVOL|4:0] and
LINMUTEto
RINVOL/4:0] and
RINMUTE
0 = Disable Simultaneous
Load
Right Channel Line Input

Volume
10111 Control
4:0 LINVOL[4:0] ( 0dB ) 11111 = +12dB . .1.5dB
steps down
to 00000 = -34.5dB
7 1 Right Channel Line Input

Mute to
LINMUTE ADC
1 = Enable Mute
0 = Disable Mute
0000001
Right Line In 8 0 Right to Left Channel Line

Input
Volume and Mute Data
Load Control
LRINBOTH Load of
RINVOL|[4:0] and
RINMUTEto
LINVOL[4:0] and
LINMUTE
Load
Bang 3 Diéu Khién Phan Mém Line Ngé Vao
Nhitngtin hiéu Line ngé vao thé hiéu dich bén trong sudt qua trinh may khuéch
dai hoat déng dén VMID. Bat cir khi nao cac Line ngé vao bi mute thiét bi dich
chuyén vao ché d6 Standby, cac Line ng6 vao duocgit lai thé hiéu dich dén VMID

ding chong lai va dap cua mach. Viéc lam giam bat ky tap dm nao ma co thé nghe
duoc khi ng6 vao hoat d6ng tré lai.
[1.1.2 Ngo Vao Microphone

MICIN1a m6tngé vao tré khang cao va cé dién dung thap phu hop két ndi dién
rong cua Microphonechi dung | kénh 4m thanh co do nhay va dong.
MICIN bao gém14ptrinh diéu chinh 4m thanh va chic nang mute.
Diéu khién phan mém cho MICIN dugc trinh bay trong bang 3. Cha y
Microphone chi Mutetin hiéu dén ADC. Diéu nay cho phéptin hiéu vao Microphone
Di qua ngé ra trong ché dé Sidetone.
Register address Bit Nhan Mac Dinh Phan M6 Ta

00000100 0 MICBOOST 0 Microphone Input Level
Analogue Audio Boot
path control 1 = enable Boost
O= disable Boost
] MUTEMIC 1 Line Input Mute to ADC
1= enable MUTE
0= disable Mute
Bang 4 Diéu Khién Phan Mém Ngo Vao Microphone.
Ngo vao Microphonebj thé hiéu dich bén trong suét qua trinh may khuéch dai
hoat d6éng dén VMID. Khi nao Line ngé vao bi mute ngd vao MICIN bi gitt lai hiéu
dich dén VMID ding chong lai tiéng 6n cua mach. Diéu nay lam giam tap 4m ma cé
thé nghe thay khi ng vao hoat déngtrélai.
I,1.3 MICROPHONEBIAS
Ngo ra MICBIAS cung cap mét 4m thanh thap dién thé pha hop véi dong dién
hiéu dich microphoneva két hop véi dién tré bén ngoai mangluibias.
Chu y rang nguén max hién thoi 1a 3mA. Gidi han nay 1a gid tri nho nhat cua
dién tro bias bén ngoai ma cé thé sir dung an toan. Chi y ngé ra MICBIASkhonghoat
déng trong ché d6 standby.
17.1.4 B6 Loc ADC

WM8731/L sit dung ADC da tang multi-bit oversampled sigma-delta.
Str dung phan hi da bit va toc d6 oversampling cao lam giam tac dong dét ngét
va 4m thanh tan s6 cao. ADC lam giam ngé vao AVDDtir 3.3V xudng 1.0. Bat ki dién
thé cao hon lam giam xudéng sé lam tran ADC vavi thé khéng chinh xac. Cha y viéc
lam giam ng6 vao phai kiém tra AVDD ngay lap tuc. Thiét bi phu vu cho mot cap
ADC. Ngo vao co thé duoc Iva chon hodc tr Line ngd vao hoac tu ngd vao
Microphone dudéi dang diéu khién phan mém.2 kénh khong thé duge chon déng thoi.
Register address Bit Nhan Nor Phan M6 Ta

00000100 2 INSEL 0 Microphone/Line Input
Analogue Audio Select To ADC
path control 1= Microphone Input
Select to ADC
0 = Line Input Select to
ADC
Bang 5 Diéu Khién Phan Mém ADC
Dé liéu sé tir ADC duoc cap cho tin higu xu ly dén b6 loc ADC.
B6é loc ADCthuc hién xt ly tin hiéu 24 bit dé chuyén d6i dit liéu oversampled
nhiéu bit tir ADC dén tan sé mau ding thanh ngé ratrén giao dién audio sé.
B6 loc s6 ADC chita mét tin hiéu s6 cao qua b6 loc, cd thé lva chon qua diéu
khién phan mém. B6 loc high-pass sé dap tmgchi tiét trong trong dac diém cua bé loc
sé. Khi b6 loc high-pass duoc enable offset DC lién tuc tinh toan va tri nhimg tin
hiéu vao. Bang cach cai dat HPORtinh toan cudi cing giatri offset de duoc luu trit
khi dé bé loc high-pass bi disable va sé tiép tuc tri nhimg tin ngd vao. Néu offset de
tahy d6i, viéc luu trit va gia tri tri sé khong thay dditrir khi bd loc high-pass enable.
Register ,
Bit Nhan Mac Dinh Phan Mo Ta
address
0000101 0 ADCHPD| 0 ADC High Pass Filter

path Control 1= disable high passfilter
0 = enable Highass Filter
4 HPOR 0 Store DC offset when high

Pass Filter Disable
1= store offset
0 = clear offset
Bang 6 Diéu Khién Phan Mém ADC
Cé vai kiéu bé loc khac nhau, dap img tan s6 va dap tmg pha. Nhiing kiéu b6
loc sé tu déng cau hinh phy thudc vao chon tic d6 mau.
11.1.5 BO Loc DAC

B6 loc DAC thuc hién xt ly tin hiéu 24 bit dé chuyén déi dit liéu audio s6 dén
tir giao dién audio s6 6 téc d6 mau ly thuyét dén dit liéu multi-Bit Oversample dé xu ly
bangtin hiéu tuong tw ADC.
B6 loc sé DAC ca thé 4p dung dudi dang diéu khién phan mém. DACcé thé
thc hién mute ma dir liéu audio dang s6 mang dén mirc d6 mute. Viéc thay doi nay
chuyén di timg budc trong audio ma cé thé cho két qua khac nhau cé thé nghe thay
trong ngo ra audio.
Register ‘
Bit Nhan Mac Dinh Phan Mo Ta
address
0000101 2:1 DEEMP{[1:0] 00 De-emphasis control(digital)
Digital Audio 11= 48 kHz
path Control 10 =44.1 kHz
01= 32 kHz
00 = disable

3 DACMU 1 DAC Soft Mute Control
(digital)
1= enable soft Mute
0= disable soft mute
Bang 7 Diéu Khién Phan Mém DAC

DAC chuyén déi dong tin higu audio sé da tang tir bd loc s6 DAC vao trong tin
hiéu audio tuong tu chat luong cao.
11.1.6 Line Ngo Ra.

WM8731/L cung cap tro khang thap line ngé ra 14 LLINEOUT va RLINEOUT,
phu hop voi dac tinh load line ca tré khang 10K va dién dung SOpF. Line ngo ra
thong str dung cé lya chon tong hop cac ngé ra tir cac DAC or/and line ngé vao trong
ché d6 bypass.
Cac ngd ra LLINEOUT va RLINEOUTchi c6 san 6 mtrc dé Line ngé ra va

khong cé diéu chinh cap d6 trong ving tin hiéu tuong ty. Co gid tri gain c6 dinh 1a
0dB. Mic 46 cé dinh nhu vay 6 DAC lam giam mirc d6 ngé ra 6 AVDD = 3.3V. Chi
y DAC lam giam mitc d6 phai kiém tra ngay lap tic voi AVDD. Line ngé ra bao g6m
tin hiéu audio bac thap di qua bd loc chuyén tiép dén bang thanh phan bén ngoai tir
DACsigma-delta. Vi thé khong loc thém ra bén ngoai bi phu thudc vao phan lén cac
ung dung.
Ngé ra DAC, Line ngé vao microphone duoc tong hop vao trong Line ngéra.
Trong ché d6 DAC chi co ngé ra tir DAC duge dinh tuyén dén line ng6 ra. Trong ché
dé bypass Line ngé vao tong hop vao trong Line ngé ra. Trong ché dé Sidetone ngd
vao microphone dugc tong hop vao trong Line ngé ra. Nhimng dac diém nay cé thé
dung cho hoac over-dubbing hoac néu DAC bi mute, nhu m6ttin hiéu tuong tu bypass
hay dictinh cla sidetone. Cho néntranhbat ky xt ly tin hiéu sé nao.
Line ng6 ra bi mute bang cach mute DAC(tin hiéu tuong ty) hay mute mém
(tin hiéu sd) va disable dudng dan BYPASS va SIDETONE.Bat ctr khi nao DAC bi
mute hoac thiét bi bi dua vao trong ché 6 standby dién thé DC duoc duy tri 6 ngo ra
dé ngan ngira tap 4m téntai hién thdi.
Diéu khién phan mém cho Line ngéra duoctrinh bay trong bang 7.
Register Bit Nhan Mac Dinh Phan Mé Ta

address
0000100 3 BYPASS 1 Bypass Swich
1= enable Bypass
0 = disable Bypass
4 DACSEL 0 DACSelect
1= select DAC
0 = Don’t select DAC
5 SIDETONE| 0 Side Tone Swich
1= enable Side Tone
0 = disable Side Tone
Bang 8 Diéu Khién Phan Mém Line Output.
11.1.7 HEADPHONE AMPLIFIER

WM8731/L c6 ngd ra headphone 4m thanh ndi co san trén LHOUT va
RHPOUT. Ngéra duoc thiét ké riéng cho headphone 16 hoadc 32 ohm véi hiéu suattéi
da va tiéu thy nang long téi thiéu. ngé ra headphone bao gém sy diéu chinh 4m luong
am thanh cao va chic nang mute.
Am luong cua LHPOUT va RHPOUTcothé duoc diéu chinh déc lap dudi su
diéu khién cua phan mém str dung LHPVOL [6:0] hoic RHPVO [6:0] bits tach biét
voi su diéu khén thiét bi ngo ra headphone. Su diéu chinh trong khoan 80dB tu +6dB
dén -73dB.
Ngo ra headphone cé thé mute béi ma chuongtrinh thap hon 0110000 dén
LHPVOL [6:0] bits. Bat ctr khi nado ngé ra headphone mute hoac thiét bi duoc dat
trong ché d6 standby, dién thé DC duoc duy tri tai duong dan xuat ra dé ngan can bat
ki 4m thanh nao cé thé nghethay trong hién tai.
M6t mach do tim giao zero dugc cung cap tai ngd vao dén headphone dudi su
diéu kién cua bit LZCEN va RZCENcuasu diéu khién ngé ra headphone. Khistr dung
su diéu khién nay 4m luong chi dugc cap nhat khi tin hi¢éu vao dén cong Gain thi dong
toi mirc dé tin hiéu tuwong ty. Nhitng 4m thanh nho va tiéng 6n nhu 1atri s6 Gain dugc
thay déi hodc im ling. Chu y rang mach nay khong cé thdi gian tam ngung chi khi

mirc DC duocchi ra téi ngd vao céng Gain cia nhiéu hon khoang 20mV,sau dé Gain
sé khong dugc cap nhat. Chic nang Zero cross thi dugc lam cho khi bit LZCEN va
RZCENcé thiét lap cao trong sudt volumeregister write . Néu c6 su lién quan rang
mirc d6 DC cé thé bi ngan can thay d6i 4m lvong sau d6 4m lugng duoc ghi vao cing
1 gia tri, nhung voi LZCEN hoac RZCENbit set low sé bat buéc sw cap nhat am luong
bat chap mirc d6 cia DC.
Am luong cia LHPOUT va RHPOUT vacai dat zero-cross cé thé duoc thay
déi déc lap. Thay vao dé, nguéi str dung cé thé mé 2 kénh cing voi nhau, cho phép ca
hai co thé cap nhat dong thoi, doi hoi su chia déi sé serial writes voi diéu kién 1a cing
Gain duoc can cho ca 2 kénh, Diéu nay 1a két qua trong khi diéu khién bit HPBOTH.
Cai dit LRHPBOTHtrong khi viét LHPVOL va LZCEN sé cap nhat déng thoi The
Right Headphonecontrols. Su anh huéng phu hop trén cap nhat RLHPBOTH 1a két
qua.
Register
address
Bit Nhan Mac Dinh Phin Mé Ta
Left Channel Line Input
Volume
Control
6-0 LHPVOL[6: 1111001 1111111 = +6dB .. 1dB
0] ( OdB ) steps down
to 0110000 = -73dB
0000000 to 0101111 =
MUTE
00000010 7 0 anne ZERO Cross
Left LZCEN _
Headphone | = Enable
0 = Disable
out
8 0 Left to Right Channel

Headphone volume, mute,
and zero Cross Data load
control
LRHPBOTH 1 = Enable Simultaneous
Load of
LHPVOL[6:0] and LZCEN
to RHPVOL[6:0]
and PZCEN

Load
Right Channel Headphone

Output Volume Control
60 RHPVOL[6: 1111001 11111 = +6dB . .1dB steps
0] ( OdB ) down
to 00000 = -73dB 0000000
to 0101111 =Mute
7 0 Right Channel Zero Cross

RZCEN Detect Enable
1 = Enable
0000011 0 = Disable
Right
qeadphone 8 0 Right to Left Channel
Headphone volume, Mute
and Zero Cross Data load
control
RLHPBOTH Load of
RHPVOL[6:0] and RZCEN
to LHPVOL|[4:0] and
LZCEN
Load
Bang 9 Diéu Khién Phan Mém Ngé Ra Headphone
11.2 Cac Ché D6 Hoat Dong
11.2.1 SYPASS MODE

WM8731/L_ bao gém phuongthitc vong do d6 dudng dan nhap vao tin hiéu
tuwong tu duoc xac dinh cu thé dé dén dudng dan xuat ra tin hiéu tuong tu va ngé ra
headphone.

a
UNEN o-OBEK I SIDETONE (OFF)

T F a +
ved ta 7 —
BYPASS (OF
FROM
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UNE —*| 7
INPUTS 1
passer yorr)| 7—L—__}-
FROM —»|
eons
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© HPOUT
win o—4
Hinh 2.2.1 Dinh Tuyén Tin Higu Trong Ché DG Bypass

Phuong thitc véng duge chon duéi sy diéu khién cia phan mém sit dung bit BYPASS
microphone duge thé hign & bang 9. Néi vé phuong thirc vong , ngd ra tir DAC
(DACSEL)va SIDETONE khéng nén chon ti duéng dan ngé ra. Tuy nhién, diéu nay
cing c6 thé duge st dung dé téng hop ngd ra DAC, Line ngd vao va ngé vao
headphone. Didu khién 4m lugng va mute tin higu tuong ty Line ngé vao va ngé ra
headphone van duge hoat d6ng trong phuong thirc vong. Thiét lap gid tri gain 0dB
duge yéu cau cho diéu chinh am lugng Line ngé vao dé tranh sy khéng chinh xac. Tin
hiéu lén nhéttai bat ki diém nao cha dudng din ving khéng duge lén hon 1.0V rms &
AVDD =3.3V dé tranh sy khéng chinh xc. D6 lén cha kiém tra tuyén tinh voi
AVDD. Diéu nay cé nghia la néu DAC dang phat ra tin hiéu 1 Vrms, va n6 duge téng
hop véi dudng din 1Vrmstin higu BYBASS, két qua cua tin higu LINEOPsé bj chia
cat.
Register
address Bit Nhan Mic Dinh Phan M6 Ta
0000100 3 BYPASS 1 Bypass Swich (analogue)
Analogue 1 =enable Bypass
Audio path 0 = disable Bypass
Control
Bang 10 Diéu Khién Phin Mém Trong Ché Dé Bypass

ee
11.2.2 SIDETONE MODE

WM8731/L cing bao gdm ché 6 canh tin higu sé noi ma ngé vao tai nghe
duge djnh hudéng dén dung din va ngéra tai nghe. Hinh anh duge thé hién & hinh 24.
Chén d6 Sidetone cho phép ngé vao microphone bj yéu di dén ngé ra cho img dung
telephone va headset.
1048 GAN aDCST

Mic {tk
Lr
F vane
SIDETONE (aN
Hinh2.2.2 Luge Dé Ché D6 Sidetone
Register
address
Bit Nhin Mic Dinh Phin M6 TA
0000100 5 SIDETONE 0 Sidetone Swich (analogue)
Analogue 1 = enable Side Tone
Audio path 0 = disable Side Tone
Control 76 SIDEATT 00 Side Tone Attenuation
11=-15 dB
10 =-12dB
01= -9dB
00= -6 dB
Bang 11 Ché Dé Sidetone
Ché 46 canh tin hiéu s6 va sy suy giam duge chon duéi sw didu khién cha phan
mém sit dung bit SIDETONE duge thé hign & bang 10.Tin higu canh ngéra tir DAC
va Line ngd vao (BYBASS) khéng nén chontit khéi Line ngé ra. Tuy nhién, didu nay
cing cé thé dugc sir dung dé téng hop ngé ra DAC, duéng din ngé vao va ngd vao
microphonelai véi nhau. Diéu khién microphone boost gain va diéu khién 4m lugng

va mute ngd ra headphone van hoat dong 6 ché d6 tin hiéu canh. Tin hiéu 1én nhat tai
bat ki diém nado trong dudng dan tin hiéu canh phai khéng lon hon 1.0Vrmstai
VDD=3.3V, dé tranh su khong chinh xac. Bién d6 nay phai kiém tra ngaylép ttre véi
AVDD.
11.3 Hoat Dong Cia Thiet Bi
11.3.1 Cai Dat Lai Thiét Bi
WM68731/L chita dung nang lwong trén mach xac lap lai ma xac lap lai trang
thai cua thiét bi bén trong. Nang luong xac lap lai duoc tmg dung nhuw 1a nang luong
DCVDDva phéng dién chi sau khi mirc d6 dién thé cua DCVDD giao voi nguéng
thap nhat. Néu sau d6 DCVDDroi thap hon nguéng dién thé nhé nhat sau dé nang
luong duge xac lap lai dugc img dung lai. Ngwéng dién thé va két hop hién tuong tré
dugc thé hién trong bang Electrical Characteristics. Ngudi st dung citing cé kha nang
xac lap lai thiét bi dé biét tinh trang bang cach diéu khién phan mém dugc thé hién 6
hinh bén dui.
Register address Bit Nhan Mac Dinh Phan M6 Ta

0001111 8:0 RESET Notreset Reset Register
Reset Register Writing 00000000 to register
resets device
Bang 12 Diéu khién phan mém cuareset.
Khi su dung xac lap lai phan mém trong ché d6 3-wire, su xac lap lai duoc tmg
dung trén su gia ting tudi cla CSB vareleased trén su gia tang tudi tiép theo cua
SCLK.In 2-wire mode, su xac lap lai duoc tmg dung trong khoang thoi gian cuatin
higu ACK (khoang 1 SCLK thoi gian)
11.3.2 Lwoc Do CLOCKING
Trong dac trung hé thong ki thuat s6 audio, chi cd mét nguon xung clock trung
tam san xuat xung clock tham chiéu matat ca dit ligu audio duoc déng b6 hoa. Xung
clock nay thuong lién hé véi hé thong xung clock chu. cho phép WM8731/L str dung
trong hé thong khoa trung tam, WM8731/L c6 kha nang phat sinh hé thong khoa nay
hoac nhan no tt nguon bén ngoai.

Trong tng dung nay, WM8671/L dugc mong muon 1a hé thong xung clock
nguon, sau do xung clock trung tam duoc tién hanh trong qua trinh str dung tinh the
phi hop duge két ndi gitta ngd vao XTI/MCLK va ng6 ra pin XTO
Trong tmg dung nay, nhiing tinh nang khac hon han WM8731/L sé dugc tao ra
6 xung clock tham chiéu, hé thong bén ngoai cé thé dugc img dung cu thé trong ngo
vao XTI/MCLKpin ma khéng can su diéu khién cua phan mém. Chi y rang trong tinh
hudng nay, may tao giao déng mach cua WM8731/L giam nang long an toan dé bao
toan nang luong.
11.3.3 LOI XUNG CLOCK.
Léi WM8731/L DSP cé thé co 1 xung clock MCLK hoac 2 xung MCLKriéng
biét. Duoc diéu khién béi phan mém trong bang 12.
Register
address
Bit Nhan Mac Dinh Phan M6 Ta
0001000 6 CLKIDIV2 0 Core Clock Divider Select
Sampling 1= Core Clock Is MCLK Divied
Control By 2
0 = Core Clock is MCLK.
Bang 13 Diéu Khién Phan Mém Ciia Loi Clock.
Cé 1 MCLKchia ré cé thé 14p trinh duoc cho phép thiét bi duoc ding trong
nhitng tng dung xung clock chu tan sé cao cé san. Vi du thiét bi cd thé hé tro xung
clock cht: 512fs trong khi hoat déng co ban & ché d6 256fs.
IT,3.4 May Tao Dao Dong CRYSTAL
WM8731/L bao gém mét mach tao dao déng Crystal cho phép xung clock tham
chiéu dén hé thong audio duoc khdi tao trén thiét bi. Diéu nay c6 san dua trén hé thong
audio trong b6 nhé dém tao thanh CLKOUT. Maytao dao déng Crystal 1a mét kiéu
nhiét thap, duoc thiét ké cho EMI thap.

a
XTUMCLK xTO
oO Cl
Cp —_ I == Cp
Vv Vv
DGND DGND
Hinh 2.3.1 Mach Ung Dung May Tao Dao DongCrystal.
Mién tin s6 cha Crystal 1a 12MHz, Cp dé nghj 1a 10pF. Mian tan sé cua Crystal
la 18MHz, Cp dé nghj la 15pF. May tao dao déng Crystal cha WM8731/L cung c4p
ngudn xung clock thap cye dé. Nguén xungclock thap 14 m6t nhu céu cho ADC va
DACaudio chat long cao khéng quan tam c4u trac méy chuyén déi. Cau tric may
WM8731/L it bj anh hudng boi ky thudt cia may chuyén dai hon tuy nhién vn ddi
héi cdc xung dién véitéc dé it hon trong duong Ins dao déng dé duytri chongtrinh.
Trong img dyng cé nhiéu hon mét ngudn xung clock master, né duge dé nghi ring mot
xung Clock duge khéi tao boi WM8731/L dé gidm rui ro téi mite t6i thiéu.
17.3.5 CLOCKOUT
Léi xungclock 14 bd nhé dém bén trong va duge lam san bén ngoai dén mét hé
théng audio trén chin ngé ra CLKOUT. CLKOUT cungcap m6 hinh cia Core Clock,
nhung bé nhé dém phi hop cho duong dan bén ngoai nhap vao.
Khéng cé dao pha gitta XTVMCLK, Core Clock vi CLOLKOUT nhung 6 46 chic
chin sé bj tré. Viéc delay sé phy thuéc vao vige dua vio CLOCKOUT.
CLKOUTciing cé thé bj chia cat boi 2 diéu khién phan mém bén dudi. Dé cap
trong ban 12. Chi y rang néu CLKOUTkhéng yéu cau khi dé b§ nho dém CLKOUT
trén WM8731/L cé thé gidm ning lugng an toan dé bao tén dién nang. Néu cautric hé
théng cé chon hiya giita sit dung Ferxour=Facix hoe Forxour=Facix/2 trong giao
dién, sau cing dé nghi dé bao toan nang lwgng. Khi hai lya chon CLKOUTthay déi
trén tac d@ng canh 1én cla MCLK, phai dé cap dén théngtin timing.

Register
address
Bit Nhan Mac Dinh Phin M6 Ta
0001000 7 CLKODIV2 0 CLKOUTDivider Select
Sampling 1= CLOCKOUTIs Core Clock
Control Divied By 2
0 = CLOCKOUTis Core Clock
Bang 14 Lap Trinh Cia CLKOUT
11.3.6 Giao Digén Phin Mem

Giao dién phan mém cé thé dugcsir dung hoac 3-wire (tuong thich SPI) hoac la
2- wire giao dién MPU. Lua chon dinh dang giao dién dugc thurc hién bang cach thiét
lap trang thai cua pin MODE.Trong ché dé 3-wire, SDIN dugc str dung cho dit liéu
cua chuong trinh, SCLK duoc ding cho clock trong dit ligu chuongtrinh va CSB dugc
ding khéa rap ngoai dit liéu chuong trinh. Trong ché d6 2-wire SDIN dugc sir dung
cho dir liéu serial va SCLK duge str dung cho clockserial, trong ché d6 2-wire, trang
thai cua pin CSB cho phép nguoi dung lua chon 1 trong 2 dia chi.
II.3.6.1 Su Lwa Chon Ché Dé Diéu Khién Serial.

Giao dién serial co thé duoc Iya chon dé hoat dong trong ché dé 2 hodc 3-wire.
Diéu nay duge thuc hién bang cach thiét lap trang thai cua pin MODE.
MODE Dinh Dang Giao Dién
0 2 wire
1 3 wire
Bang 15 Giao Dién Lua Chon MODE
II.3..6.2 Ché D6 Diéu Khién Serial 3-Wire (Tuong Thich SPI)

WM8731/L c6 thé diéu khién ding giao dién serial 3 wire. SDIN duocstr dung
cho dir ligu chuong trinh, SCLK duoc st dung dé clock di liéu chuong trinh va CSB
duoc dung khoéa rap ngoai dt liéu chuongtrinh.

ee
se Lt
seck_TL# LF LF LF LF LF LALA LE LA LF LF LE LF LE LF
sow [es] e[enleapen[eo[ ele lelelesl|sl[esl=|a |=]
Hinh 2.3.2 Giao Dién Serial 3-Wire
Chi y:
> B[15:9] ld cdc bit diéu khién dia chi.
> B[8:0] 1a bit didu khién dit liéu.
> CSB la tich cyc canh khéngcé cap dé tich owe. Dit ligu duge hidu trén canh
1én cha CSB.
I1.3.6.3 Ché D6 Diéu Khién Serial 2-Wire.

WM8731/L hé tro mét giao dién serial MPU. Thiét bi hoat déng chi nhur métthiét
bi Slave. WM8731/L cé méttrong hai dia chi slave ma duge lya chon bang cach thiét
lap trang thai cha pin 15, (CSB).
= rm
TN CRROR YHA scx <Tommctea, ack (paren ack up
SDIN ‘+ — —SF T|
| |
see TN ANIA NAINA

fF JF +
STOP
START
Hinh 2.3.4 Giao Dién Serial 2 - wire
> B[15:9] la cdc bit didu khién dja chi.
> B[8:0] 1a bit didu khién dit ligu.

Trang Thai CSB Dia Chi
0 0011010
1 0011011
Bang 16 Lua Chon Dia Chi Giao Dign MPU 2 — Wire

Dé diéu khién WM8731/L trén bus 2-wire thiét bi diéu khién master can phai
chuyén déi dit liéu bang cach thiét lap diéu kién bat dau, dinh nghia béi chuyén tiép
cao hoac thap trén SDIN trong khi SCLK con lai cao. M6t dia chi va mdt dir liéu
chuyén d6i sé theo sau. Tat ca ngoai vi trén bus 2-wire dap tmg diéu kién bat dau va
dich vao trong 8 bit ké tiép (7 bit dit liéu + bit R/W). Chuyén bit MSB truéctién.7 bit
dia chi bao gém bit dia chi co ban + 1 bit don cé thé 14p trinh dé lua chon 1 trong 2
thiét bi san sang cho thiét bi nay. Néu dia chi chinh x4c duoc nhan va bit R/W 1a “0”,
biéu thi 14 ghi, sau d6 WM8731/L sé dap tmg bang cach kéo SDIN xud6ng thap trén
xung clock ké tiép (ACK). WM8731/L chi ghi vao thiét bi va sé chi dap img lai khibit
R/W biéuthi ghi. Néu dia chi khong dugc chap nh4n thiét bi sé tra vé diéu kién vé ich
va ché mét diéu kién bat dau mdi va mot dia chi ving chac.
Méi lan WM8731/L thira nhan mét dia chi dung, bd diéu khién sé go1 8 bit dir
liéu(bit B15-B8). WM8731/L sau dé sé thira nhan dit liéu di goi bang cach kéo SDIN
xudng thap cho mot xung clock. B6 diéu khién sau dé sé giri 8 bit dit liéu cdn lai (bit
B7-BO) va WM8731/L sé xac nhan m6t lan nita bang cach kéo SDIN xu6ng mircthap.
Diéu kién dimg dugc dinh nghia khi c6 mét chuyén tiép tir thap dén cao trén
SDIN trong khi SCLK 6 mic cao. Néu diéu kién bat dau hodc két thuc due phat hién
ra bén ngoai cua bat ki diém nao trong di liéu chuyén déi sau dé thiét bi sé nhay dén
diéu kién khong hiéu qua.
Sau khi nhan dugc motdia chi hoan tat va dit 1iéu lién tiép WM68731/L sé quay
lai trang thai khéng hiéu qua va cho mot diéu kién bat dau khac, dia chi thiét bi va va
bit R/W theo sau boi 16 bit thanh ghi dia chi va dit liéu.
11.3.7 Ché D6 Ning Luong
WM8731/L chia ché d6 bao toan ning luong trong khéi mach khac nhau cé thé
ha nang lugng xudng motcach an toan trong muc bao ton nang luong.
Register address Bit Nhan Mac dinh Phan M6 Ta

0000110 0 LINEINPD 1 Line Input Power Down
Power Down 1= Enable Power Down
Control 0 = Disable Power Down

] MICPD ] Microphone Input An Bias

Power Down
1= Enable Power Down
0= Disable Power Down
2 ADCPD 1 Adc Power Down
3 DACPD 1 DAC Power Down
0 = Disable Power Down
4 OUTPD ] Line Output Power Down
5 OSCPD 0 Oscillator Power Down
6 CLKOUTPD| 0 CLKOUT Power Down
7 POWEROFF| 1 Power Off Device
1= Device Power Off
0 = Device Power On
Bang 17 Diéu Khién Phan Mém Ché Dé Bao Ton Nang Luong
Diéu khién nang lugng ha xuéng cé thé duoc str dung hodc dé Cé dinh chic
nang disable khi khéng c6é yéu cau trong img dung nao dé. Hoac dé linh dong chitc
nang tang va ha nang luong phu thudc vao ché d6 hoat dong vi du trong luc nghe lai
hay ghi am.
LINEINPD: déng thoi ha nang hrong ca 2 line ngd vao. Diéu nay co thé thuc
hién linh d6éng khéng can bat ctr két qua cé thé nghe thay nao hoac trén ADC hoactrén
Line ng6ra trong ché dé Bypass. Diéu nay duoc dung khi thiét bi nhap vao ché dé
PlayBack, Pause hoac Stop hoac ng6 vao Microphone dugc chon.
MICPD: dong thoi ha nang luong ca hai ngd vao Microphone va Microphone
Bias. Néu diéu nay thuc hién linh dong, cé thé nghe tiéng pop do ADC manglai. diéu
nay chi c6 thé nghe thay néu ngd ra Microphone duge chon dén ADC vao thoi diém.
Néu trang thai cua MICPD bi thay déi sau dé viéc diéu khién DSP hoac vi xt ly sé
chuyén dén chon Line ngé ra nhu ngd ra dén ADC (INSEL) truéc khi thay déi
MICPD. Diéu nay dung khi thiét bi nhap vao ché 46 PlayBack, Pause, hoac Stop hoac
ng6 vao Microphone khéng dugc chon.

ADCPD: ha nang lugng ADC va bé loc ADC. Néu diéu nay thuc hién linh hoat
sau dé tiéng pop cé thé nghe duoc sé cho két qua bat ky tin hiéu 6 hién tai qua ADC.
Dé khac phuc diéu nay bat ctr khi nado ADCbi ha nang luong, hoac mute ngd vao
Microphone hoic MUTELINEIN,sau d6 thay d6i ADCPD.Diéu nay ding khi thiét bi
nhap vao ché d6 PlayBack, Pause, Stop khéng ké 14 Microphone hay Line ngé vao
duoc chon.
DACPD: ha nang lugng DAC va b6 loc DAC.Néu diéu nay thuc hién linh hoat
sau do tiéng pop cé thé nghe duoc sé cho két qua trir khi nhitng nguyén tac sau day
xay ra. Muc dich dé ngan ngiva tiéng pop, DAC sé bisoft-mute trudc (DACMU), ngo
ra sau do tir line va ngo ra headphone (DACSEL), sau do DAC sé bi ha nang luong.
Diéu nay dung khi thiét bi nhap vao ché d6 ghi 4m, Pause, Stop hodc ché d6 Bypass.
OUTPD: ha nang lvong Line ngé ra va ng6 ra headphone. Néu diéu nay thuc
hién linh hoat sau do tiéng pop cé thé nghe duoc sé cho két quatrir khi DAC bi soft-
mute trudc (DACMU). Diéu nay dung khi thiét bi nhap vao ché dé ghi am, Pause,
hoac Stop.
OSCPD: tat ning lugng trén board may tao dao dong crystal. Ng vio MCLK
sé hoat dng khéng phu thudc maytao dao dong bi ha nang luong.
CLKOUTPD: ha nang luong pin CLOCKOUT. Diéu nay bao toan nang luong,
lam giam 4m thanh s6 va su phat ra cua RF néu khéng duoc yéu cau. CLKOUT duoc
git & muc thap khi nang lugc ha. Thiét bi cd thé dugc dat trong ché dé standby
(STANDBY)bang cach ha nang luong tat ca mach audio dudéi dang diéu khién phan
mém. Néu may tao dao dong Crystal and/or pin CLOCKOUTstr dung sé nhan dugc tir
hé thong clock master, diéu nay sé cé thé khéng bao gid bi tat nang luong trong ché dé
standby.
A
e & A
2 5 : 5/5 |B 2 M6 Ta
E 2 16/8/46 /2|s Z
ae a
Oo
4
0O;0);0;1;1 {1414} 1 Standby, nhung voi may tao dao ddng crystal

OS va CLOCKOUTsan sang
Standby, nhung v6i may tao dao ddngcrystal

OS san sang va CLOCKOUTkhongsan sang
Standby, nhung véi may tao dao dodngcrystal

OS va CLOCKOUTkhong san sang
Bang 18 Ché D6 Stanby

Trong ché dé stanby giao dién diéu khién, mét phan nhé cua ky thuat sé va
vung mach tuong tu tich cyc con lai. Tin higu tuong ty tich cyc bao 26m tin hiéu
tong tu VMID chuyén dén vi thé ma Line ngéd vao tuong tu, line ngd ra va ngo ra
headphone van hudéng dén VMID. Viéc lam giam nay bat ctr két qua co thé nghe duoc
nguyén nhan bdi glitches DC khi nhap vao hay rdi bé ché dé standby. Thiét bi cé thé
bi tat nang lwong bang cach ghi dén bit POWEROFFcua thanh ghi POWER DOWN.
Trong ché dé tat nang luong Giao dién va mét phan nho cua ky that s6 tich cuc conlai.
Tin hiéu tuong tr VMID bi disable. Nhu trong ché d6 Standby may tao dao déng
crystal and/or pin CLKOUTcé thé khong phu thudc vao diéu khién.
CLOCKOUTPD
POWER OFF
LINEINPD
DACPD
ADCPD
OUTPD
OSCPD
MICPD
M6 Ta
Power off, nhung v6i may tao dao d6éng

—
oS
m4
rs
rs
crystal OS va CLKOUTsan sang
Power off, nhung véi may tao dao ddng

1} 1/0] x |x |xJx x |erystal OS sin sang va CLKOUT khong
san sang
Power off, nhung voi may tao dao d6éng

crystal OS va CLKOUTkhongsan sang
Bang 19 Ché Dé Poweroff

11.3.8 Ban Dé Thanh Ghi
Cé 11 thanh ghi, mdi thanh ghi 16 bit (7 bit dia chi, 9 bit dit ligu). Diu nay cd
the diéu khién dung giao dién hoac 2 wire hoac 3 wire.
B B B B B B |B
REGISTER B8 B7 B6 BS B4 B3 B2 Bl Bl
15 14 13 12 11 10 9
LRIN LIN
RO(OOh) 0 0 0 0 0 0 0 0 0 LINVOL
BOTH MUTE
RLIN RIN
R1(02h) 0 0 0 0 0 0 1 RINVOL
BOTH MUTE
LRHP
R2(04h) 0 0 0 0 0 1 0 LZCEN LHPVOL
BOTH
RLHP RZCE
R3(06h) 0 0 0 0 0 1 1 RHPVOL
BOTH N
MIC
SIDE DACS BYPA INS MUT
R4(08h) 0 0 0 0 1 0 0 0 SIDEATT BOOS
TONE EL $8 EL EMIC r
DAC ADC
R5(0Ah) 0 0 0 0 1 0 1 0 0 0 0 HPOR DEEMPH
MU HPD
PWR cLKou oscp ouTP DAcP AD MIcP LINEI

R6(OCh) 0 0 0 0 1 1 0 0
OFF TPD D D D CPD D NPD
BCLK IRS
R7(Eh) 0 0 0 1 1 1 0 MS LRP IWL FORMAT
INV WAP
CLKO CLKI USB/

R8(10h) 0 0 0 1 0 0 0 0 SR BOSR NOM
DIV2 DIV2 AL
ACTI
R9(12h) 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0
VE
RIS(LEh) 0 0 0 1 1 1 1 RESET
DIA CHI DU LIEU
Bang 20Ban Dé Thanh Ghi Chwong Trinh
11.3.9 Nét Dic Trung Cia Dau Loc Ky Thuat S6

B6 loc s6 ADC va DAClam viéc khac nhau. B6 loc ky thuat s6 co 4 kiéu, dugc
goi la kiéu 0,1,2 va kiéu 3.

Tham $6 | Kiém Tra Diéu Kién Min | TYP | Max |. DonVi

B6 Loc S6 ADC Loai 1 (ché d6 USB, tan sé hoat dong 250fs)
+/-0.05dB 0 0.416fs
Passband
-6dB 0.5fs
Passband Ripple +/-0.05 dB
Stopband 0.584fs
Lam Giam Stopband f>0.584fs -60 dB
B6 Loc S6 ADC Loai 1 (ché d6 USB, 272fs hodc hoat déng ché d6 Normal)
+/- 0.05 dB 0 0.4535fs

Passband
-6dB 0.5fs
Passband Ripple +/- 0.05 dB
Stopband 0.5465fs
Lam Giam Stopband f>0.5465fs -60 dB
-3dB 3.7
High Pass Filter Corner
Frequency -0.5dB 10.4 Hz
-0.1dB 21.6
Bé Loc Sé DAC Loai 0(ché d6 USB, 250fs)
+/- 0.03 dB 0 0.416

Passband
-6dB 0.5fs
Passband Ripple +/-0.03 dB
Stopband 0.584fs
Lam Giam Stopband f> 0.584fs -50 dB
Bé Loc Sé DAC Loai 1 (ché d6 USB, 272fs hoc hoat déng ché d6 Normal)

+/- 0.03 dB 0 0.4535

Passband
-6dB 0.5fs
Passband Ripple +/- 0.03 dB
Stopband 0.5465fs
Lam Giam Stopband f> 0.5465 fs -50 dB
Bang 21 Dat Tinh Cita B6 Loc S6

11.3.10 Su Hoat Dong O' Ché Dé Master/Slave.
WM8731/L cé thé dugc cau hinh nhu 1a chia ra 2 ché d6 master hodc slave. Khi
thiét bi 6 ché d6 Master WM8371/L kiém soat su sap Xép theo thir tu cua dtr liéu va
xung clock trén giao dién ky thuat s6. Khi thiét bi Slave 6 ché d6 WM8731/Ltra loi ti
dir ligu toi xung clock, no sé nhan dugc giao dién ky thuat sé. Ché d6 nay duoc lap ra
v6i bit MSB cua thanhghi diéu khién.
Register ,
Bit Nhan Mac dinh Phan M6 Ta
address
0000111 6 MS 0 Master Slave Mode Control
Digital Audio 1 = Enable Master Mode
interface format 0= Enable Slave Mode
Bang 22 Lép Trinh Ché Dé Master/Slave
Khi thiét bi @ ché d6 Master WM8731/L diéu khién sw sap xép cua dit liéu
chuyén d6i (ADCDAT, DACDAT) va xung clock ngé ra (BCLK, SDCLRC,
DACLRC)trén giao dién k¥ thuat s6. N6 sit dung quy trinh tao ra xung clock hoat
dong tir mach hodc ngd vao MCLK khi tham chiéu xung clock va trang thai cua dt
ligu. ADCDATlu6n luén 1a ngé ra va DACDATlu6n lun 1a ngd vao. Ché d6 master
hoac slave khéng phu thudc vao WM8731/L

ee
BCLK
wme731 “one
DACLRe |.» DSP
ENCODER!
CODEC DECODER
ADCDAT
DACDAT }*——_———_
Note: ADC and DAC can run at different rates
Hinh 2.3.5 Ché D6 Master.

Khi thiét bi 6 ché d6 slave WM8731/L_ biéu dién sy thay ddi di ligu
(ADCDAT,DACDAT)trén giao dién k¥ thyat sé théng tin ra bén ngoai duge ap dung
cho xung clock (BCLK, SDCLRC, DACLRC).
Chu y ring WM8731/L dya vao méi quan hé diéu khién gitta giao dién audio
ACLK, DACLRCva master MCLK hofc CLKOUT.
BCLK
wms731 mane
DACLRG fe! DSP
ENCODERY
CODEC DECODER
ADCDAT
DACDAT -*—————_
Note: The ADG and DAC can run at different rates:
Hinh 2.3.6 Ché D6 Slave.
IL4 Méta tong quat yé SD CARD

Lai SD Bus véi giao dién Avalon cho phép truy xudt dé ding cia hé théng
SOPC Builder dén thiét bj Secure Digital Card chuan ( SD Card), Léi SD Bus dé dang

hop nhat véi bat ky hé théng SOPC builder nao dugc tao ra. Dé xt ly Nios II, EL
Camino cung cap driver mtrc thap cé dinh véi 16i SD Bus. Driver cung captruy xuat
phé bién cho thiét bi nhé SD. Vi thé khéng can phai viet thém bat ky code dé doc hoac
ghi dit liéu tir hodc dén SD card.
IL.4.1 Tinh Nang
H6 tro SD card trong ché d6 SD Bus(4 bit hay 1 bit).

WV
H6 tro SD Card bé nhé nang suat cao (SDHC).

WV
H6tro ché d6 téc d6 cao 1én dén toc d6 xung clock 1a 50 MHz.
WV
Bao gdm driver mitc thap.

VV
File hé thong cé san tuy chon FAT12/FAT16/FAT32.

Ung dung Window cho phép doc/ghi truy xuat dit liéu trén nén PC.
Vv
BO tuong thich dau tién cho board phat trién Altera va El Camino Nios II .
Vv
11.4.2 Ung dung
L6i SD Bus tmg dung cho cac thiét bi luu dong, chuan va c6 thé trao déi, luu
trit truyén thong phy thudc vao img dung NIOSII. Khac voi tng dung cung cap cho
window no dé dang chuyén déidit liéu gitta img dung NiosII va nén PC.
1.4.3 Mo Ta Port Cua SD Card
Thé nho SD card gém mitsé port chinh sau:
> SD_CLK (ngé ra) : tin hiéu xung clock dén thé nhoé SD card. Xung clock nay
nhan tir xung hé thong béi tham sé xung clock phan chia ra. Tan s6 xac dinh toc
d6 dit liéu va thiét lap tu dong boi phan mém driver. Gan vao pin 5 cua SD
Card.
> SD_CMD(ngé vao/ngéra): tin hiéu 2 chiéu cau lénh/ tra loi. gan vao pin 2 cua
SD Card.
> SD_DAT[3 : 0] (ngé vao/ ngé ra): tin hiéu dit liéu 2 chiéu. SD_DAT3 gan vao
pin 1. SD_DAT2 gan vao pin 9. SD_DAT1 gan vao pin 8. SD_DATO gan vao
pin 7.

ee
11.5 Dinh Dang FAT
FAT(File Allocation Table) 14 hé théngfile dugc gidi thigu 1an dau tién vao
nim 1981 cing véi sy ra di cha MS-DOS . Mucdich cua FAT la cung cap mét ban
a giita nhitng Cluster - né 1a don vj co ban cua luu trit logic trén dia voi mite 6 hé
digu hanh , va vjtri vat Ii cua dit ligu duge xdc dinh béi Cylinder , Track va Sector
duge ding cho déi véi phan cimg diéu khién é dia .
Cylinder
Zoned-bit recording
Hinh 2.5.1 so dé FAT

FAT bao gdm dau vao moi File duoc lu trit trén phan ving 6 cimg va 1a dia chi bat
dau Cluster cia File. Méi Cluster bao gdm ni dung cua File va chi téi Cluster tiép
theo chita n6i dung File hoac théng bdo kétthc File: End-Of-File ( OxFFFF ) dé thong
bao Cluster 6 1diém cuéicia File .
Vi dy duéi day cé 03 File : Filel.txt ding 03 Cluster . File2.txt 1a file bi phan

manh cing cé 03 Cluster (5,6 va 8 ) , va File3.txt vita trong mét Cluster (7) .
HES
a 1 z 3 4 5 6 a a
|_| [o00s|0004leave! coos [EEE rere|

L#L# L#L__#
Hinh 2.5.2 phan manhtrong Fat

D6 dai cua méi phantit cua FAT duoctinh bang sé bit. D6 dai nay biéu thi kha
nang chi thi s6 dém cua phan tir FAT. Voi cdc dia mém sé luongcdccluster 1a nhé nén
chi can 12 bit di dé chi thi sé dém nay, vi vay cdc dia mém ding FAT 12 bit. V6i dia
ctmg cé dung luongtir 1GB tré lai dé chi thi s6 Cluster l6n nhat thi phai ding tdi con
s6 co dé dai 16 bit, vi thé hinh thanh FAT 16 bit. Vi cdc dia ctmg cé dung luongtir
vai GB tré én, sé lugng cac sector trén dia rat lén, déng thoi dé han ché cac sector b6
trong trong mdicluster thi nguéita qui dinh sé sector trong mi clusterit di, do dé sé
long Cluster cia ca dia sé rat lon. Khi ay phai ding téi con sé c6 dé dai 32 bit dé chi
thi s6 dém nay. Day 1a li do hinh thanh FAT32bit.
Hién than cua FAT dau tién la FAT12 ma hétro kich thudc Partition 1én nhat 1a
8MB. Nobi thay thé bang FAT16 vao nam 1984 va tang kich thudc cua Partition lén
2GB. FAT16 da trai qua nhiéu nam né cho phép diéu khién tén file dai hon phién ban
dau tién 1a 8.3 ki tu. Mot diém gidi han cua FAT16 1a sé Cluster lon nhat trong mét
Partition 14 c6 dinh nén 6 ctmg cé dung luong cang én thi cang co nhiéu khoang trong
khong duoc ding dén. M6t diéu thudn loi cua FAT16 1a né hé tro nhiéu hé diéu hanh
khac nhau Windows 95/98/Me, OS/2, Linux va mot vai Version cua Unix.
Phién ban Windows 95 OEM Service Release 2 (OSR2) hé tro ca FAT16 va

FAT32.
FAT32 chia sé nhitng gidi han cua FAT16 nhung lai co mot diéu nhimng hé
diéu hanh tuong thich voi FAT16 lai khéng lam viéc voi FAT32. D6i voi may tinh
chay 02 hé diéu hanh vi du Windows NT va mét hé diéu hanh dang FAT32 thi
Windows NTlai khong doc duoc truc tiép FAT32, nhung van dé sé dugc gidi quyét
thong qua mang.
Cung voi su xuat hién cua WinXP vao thang 10 nim 2001 bao g6m ca NTFS .
NTFShoan toan khac véi hé thong File cua FAT, no c6 thiét lap bao vé cao,tiét
kiém duoc khoang tréng trén dia d6éng thoi dia chi hoa dugc nhiéu Cluster.

ee
—@—_—_ Block of 16 clusters ——————_}
real clusters virtual clusters virtual clusters
[Lo 20 341 Ss] 6] 7 8) stop ipi2[i3pt4pispe 71a] |

physical clusters (an disk)
Sau day ching ta sé tim hiéu ré hon vé cdc phién ban cua FAT12, FAT16 va
FAT32.
> FAT12 (File Allocation Table, 12-bit): duge ding cho 6 dia mém,6 dia co dung
lugng tir 32MB tro xuéng. FAT12 sir dung 12 bit dé dém nén chi cé kha nang
quan ly cdc é dia cé dung lugng thdp hon 32Mb véisé Ivgngcluster thap.
> FAT16 (File Allocation Table, 16-bit): hé trg nhimg hé didu hanh DOS,
Windows 9x/Me. Véi FAT naychi hé trg nhitng tén tap tin cd d6 dai 1a 11 ky
ty (8 ky ty danh chotén tap tin va 3 ky ty dinh cho phan mé réng,) va hd trg
nhimg HDD hoicnhing phan ving(partition) cé dung longtéi da 14 2 GB, hé
théng tap tin FAT (FAT16 — dé phan biét voi FAT32) duoc cong bé vao nim
1981 dua ra m6t cach thie mdi vé vic té chirc va quan lytp tin trén dia cig,
dia mém.Tuy nhién, khi dung lugng dia cig ngay cang ting nhanh, FAT16 da
béc 16 nhidu han ché. Voi khéng gian dja chi 16bit, FAT16 chi hé tro dén
65.536 lién cung (clusters) trén mt partition, gay ra sy lang phi dung lugng
dang ké (dén 50% dung lugng déi véi nhing é dia cimg trén 2 GB).
> FAT32 (File Allocation Table, 32-bit) : dugc giéi thigu trong phién ban
Windows 95 Service Pack 2 (OSR 2), duge xem 1a phién ban mé réng cua
FAT16. Do sir dyng khéng gian dia chi 32 bit nén FAT32 hé tr¢ nhiéu cluster
trén mét partition hon, do vay khéng gian dia cig duge tan dung nhidu hon.
Ngoai ra véi kha nang hé tro kich thudc cia phan ving ti 2GB lén 2TB va
chiéu dai téi da cia tén tap tin duge mé réng dén 255 ky ty da lam cho FAT16
nhanh chongbi lang quén. Tuy nhién, FAT 32 c6 1 sé nhugcc diém sau:

“* FAT32 la tinh bao mat va kha nang chiu 16i (Fault Tolerance) khéngcao:
“* FAT32 khong hé tro cac tinh nang bao mat nhu phan quyén quan ly, ma
hoa..
¢* FAT32 cé kha nang phuc héiva chiu 16i rat kém.

“* FAT32 van con té ra hitu dung trén cdc may tinh cau hinh qua yéu,chi
c6é thé chay duoc Windows 98. Tuy nhiénFAT16 va FAT32 van dugc
ding dé dinh dang cho cac loai thé nho,vi cac thiét bi chap nhan thé nhé
nhu may anh sé, may nghe nhac van chua thay loai nao tuong thich voi
NTFSca. FAT16 luon 1a lua chon hang dau khi ban muén copy di li¢u
cua minh tir mét may tinh chay Windows sang may chay hé diéu hanh
khac nhu Mac chang han. Hau hét cac may Mac hién nay déu khongthé
nhan dang cac thé nho USB dugc dinh dang bang FAT 32.
Bang so sanh sau day sé giup chung ta nhin r6 hon nhttmng wu nhugce diém cua
phién ban FAT12, FAT16 va FAT32.
FAT 12 FAT 16 FAT 32
Nhaphat trién Microsoft
Tén day du Phién ban 12 bit Phién ban 16 bit Phién ban 32 bit
Cau trac
Cau trac thu muc Bang
Dinh dangtap tin Danhsach lién két
Gidi han
Kich thudéc tap tin

ida 2MB 2GB 4GB
Sé luong cac tap 4096 65536 268,435,437

tin toi da
D6 dai tén tap tin -

a 8.3 hoadc 255 ky ty tuy hé diéu hanh
toi da
Kich thudc phan ,

. 32MB 2GB dén 4GB 2TiB
vung toi da
Bang 23. Bang so sanh cac dinh dang FAT
11.6 Khai Niém Vé Tap Tin Wave

Tap tin wave la mét dang tap tin ding dé luu trit dit ligu 4m thanh sé (dang
song) va nd la mét trong nhitng dinh dang phé bién nhat cia hé diéu hanh Windows.
Tap tin wave thudc chuan RIFF ( Resource Interchange File Format- dang taptin tai
nguyén cé thé trao déi) va dac diém cua nhiing tap tin thudc chudn RIFF dé 1a no sé
nhom noi dung cua tap tin thanh cac khdi riéng biét va mdi mét khdi sé gdm mot
header (dung dé qui dinh kiéu va kich thudc cua khdi ) va cdc byte dit liéu. Tap tin
wave cé 2 dang la dang nén va dang khéng nén (dang chuan) vi thé trong dé tai nay t6i
chi dé cap dén dang chuan cuatap tin wavetirc la dang khéng nén.
Cau tric file wave gdm 3 khéi: khéi mé ta dang RIFF,kh6i thudc tinh “fmt “ va
khéi dit liéu “data” trong do khéi thuédctinh “fmt” va khéi dit liéu “data” 1a 2 khdi con
cua khéi m6 ta dang RIFF.
Khéi mé ta dang RIFF: Khéi nay xac dinh dang RIFF va co kich thuéc 1a 12
byte gdm cac truong:
¢* ChunkID: Kich thuéc: 4 byte. Chic nang: chita chudi “RIFF” duéi dang
ma ASCII
¢* ChunkSize: Kich thuéc: 4 byte. Chirc nang: cho biét tong kich thuéc cua
cac truong sau no.( ChunkSize=4 + ( 8 + Subchunk1Size ) + ( 8 +
Subchunk2Size)).
¢* Format: Kich thuéc: 4 byte Chitc nang: chtra chudi “WAVE”.

Kh6i thuéc tinh “fmt ”: Khéi nay xac dinh cdc thudctinh cua dit liéu 4m thanh
va c6 kich thuéc1a 24 byte g6m cac trudng:
¢* Subchunk1ID: Kich thuéc: 4 byte. Chitc nang: chita chuéi “fmt ”.
¢ Subchunk1 Size: Kich thuéc: 4 byte. Chic nang:cho biét tong kich thuéc
cua cdc truéng thuéc khéi thudéctinh dimg phia sau truong nay. (d6i voi
tap tin wave khéng nén thi Subchunk1 Size bang 16).
“* AudioFormat: Kich thudc: 2 byte. Chic nang: chota biét dang nén cua
dir ligu trong tap tin wave.

ee
Chuong 3 Hé Thing Téng Quat
III.1 Thiét Ké M6 Hinh SD Music Player.

Nhiéu thiét bj nghe nhac sir dyng thiét bj lu trit bén ngoai , ching han nhw1a
SDcard... dé chia cac file nhac. Nhiéu thiét bi nghe nhac cé chita b6 Igc sé DAC 06
thé tao ra 4m thanh chét lugng cao. Board DE2 cung cdp phan ctmg va phin mém can
thiét chuyén thyc hién truy xudt audio trén SD card.
Trong phan demo ching ta sé thyc hién mét thiét bi nghe nhac SD card trén
board DE2,file nhac sé dyge lay tir SD card. Chingta sé ding b6 xir ly NIOSII dé
doc dé ligu tk SD card va ding audio codec WM8731 dé chayfile nhac.
Thiét bj Audio Codec WM8731 duge cau hinh & ché dé slave, mach bén ngoai cung
cap serial ADC/DAC,bit clock va kénh clock trai phai (LRCK) dén thiét bj Audio
codec.
I2C Audio iauecout

Configuration
NiosII Audio DAC Audio Caen

CPU Controller CODEC
Bypass ae
ADC to DAC os
Hinh 3.1 so dé khdi cia thiét ké SD music player.
Dé thuc thi mach thiét ké, ching ta cin cung cAp mét bé didu khién Audio DAC
4@ hoan tat khéi tao xung clock va diéu khién dong dit ligu. BG diéu khién Audio DAC
duge tich hgp vao trong céu trac Avalon busvi thé b6 xu ly Nios II cé thé diéu khién
img dung. Khi bé xt ly NiosII hoat déng no sé kiém tra néu b6 nhé FIFO cua bé didu
khién Audio DAC bi day. Néu b6 nhé FIFO cén tréng, bd xt ly sé doc 512-byte sector
va goi dit ligu dén FIFO cia bé diéu khién Audio DAC qua duéng Avalon bus. Bé

diéu khién Audio DAC dung toc d6 lay mau 1a 48kHz dé géi dit liéu va tin hiéu clock
dén thiét bi Audio Codec.
Dé nghefile nhac trong thiét ké nay,file phai sir dung t6c dO lay mau la 48kHz
va dinh dang WAV do phangiai 16 bit.
II.2 Chuong Trinh Demo.
II1.2.1 Cac Dinh Nghia Thiét Lap

MI.2.1.1 Cho Ng6 Vao Va Ngo Ra
#ifndef SDCardH__
#define SDCardH__
#define SD_CMD_IN IOWR(SD_CMD_BASE,1, 0)
#define SDCMD_OUT IOWR(SD_CMDBASE,1, 1)
#define SD_DAT_IN IOWR(SD_DAT_BASE,1, 0)
#define SDDATOUT IOWR(SD_DATBASE,1, 1

Cac ngd vao va ngd ra cua SD card duoc dat tén la SDCMD_IN,
SD_CMD_OUT, SD_DAT_IN, SD_DAT_OUT. CaAc ngé nay duoc thiét lap 1a ng
vao hay ngo ra bang cach ghi vao dia chi co ban cia né gia tri 1a bit 1 hodc bit 0. Néu
gia tri ghi vao 1a 0 thi cé nghia 1a nhap vao, congia tri ngd vao 1a 1 cé nghia 1a xuatra.
M.2.1.2 Dinh Nghia Ngo Ra SD Card Cao/Thap
#define SDCMDLOW IOWR(SD_CMDBASE,0,0)

#define SD_CMDHIGH IOWR(SD_CMDBASE,0,1)
#define SD.DATLOW IOWR(SD_DAT_BASE,0,0)
#define SD_DAT_HIGH IOWR(SD_DATBASE,0, 1)
#define SD_CLK_LOW IOWR(SD_CLKBASE,0,0)
#define SD_CLK_HIGH IOWR(SD_CLK_BASE,0, 1)

Cac ngé ra cua SD card dugc dinh nghia cao hay thap phu thudc vao giatri ghi
vao dia chi cua no la 1 hay 0. Néugiatri ghi vao dia chi la 0 tic 14 6 mtthap va néu
gia tri la 1 thi 6 mtc cao.
II.2.1.3 Doc Ng6 Vao SD Card
#define SD_TESTCMD IORD(SD_CMDBASE,0)

#define SD_TESTDAT IORD(SDDATBASE,0)
Dé doc ngé vao SD card ta doctrong dia chi thanh ghi cua ching néu doc trong
thanh ghi SD_CMDBASEla doc ra cau lénh con doc trong dia chi SDDATBASE
thi doc dit liéu.
IT.2.1.4 Cac Dinh Nghia Khac.
#define BYTE unsigned char
#define UINT16 unsigned int
#define UINT32 unsigned long
Dinh nghia BYTE 1a theo kiéu chudi. UINIT16 dinh nghia theo kiéu int.
UINT32 dinh nghia theo kiéu long.
void Ner(void)
void Nec(void);
BYTEresponseR(BYTE);
BYTE send_cmd(BYTE*);
BYTE SD_read_lba(BYTE *,UINT32,UINT32);
BYTE SD_card_init(void);
BYTEread_status;
BYTEresponse_buffer[20];
BYTE RCA[2];
BYTE cmd_buffer[5];

const BYTE cmd0[5] = {0x40,0x00,0x00,0x00,0x00};
const BYTE acmd6[5] = {0x46,0x00,0x00,0x00,0x02};
const BYTE acmd41[5] = {0x69,0x0f,0xf0,0x00,0x00};
const BYTE acmd51[5] = {0x73,0x00,0x00,0x00,0x00};
Dinh nghia cac ham con trong chuong trinh nhu ham Ncr(void), Nec(void),
responseR(BYTE), send_cmd(BYTE *), SD_read_lba(BYTE *, UINT32, UINT32),
SD_card_init(void), read_status, response_buffer[20], RCA[2], cmd_buffer[5]. Cac
gia tri dia chi cé dinh cia cac 1énh nhu cmd0[5] = {0x40,0x00,0x00,0x00,0x00} ....
11.2.2 Cac Chuong Trinh Con Va Cac Ham Con.
IT.2.2.1 chuong trinh void Ner(void)
void Ner(void)
{
SD_CMD_IN;
SD_CLK_LOW;
SD_CLK_HIGH;
SD_CLK_LOW;
SD_CLK_HIGH;

Ham dua cau lénh vao thanh ghi dia chi cua SD_CMD_BASEsau do dua xung
clock vao. Trong nay co su thay déi gid tri xung clock.
II.2.2.2 chuong trinh void Nec (void)
void Nec(void)
{
int 1;
for(i=0;1<8 i++)
{
SD_CLK_LOW;
SD_CLK_HIGH;
}
}
Ham Void Nec(void) chu: yéu dung dé dua xung clock vao.
1.2.2.3 Ham Khoi Tao SD Card
BYTE SDcard_init(void)
{
BYTE x,y;
SD_CMDOUT;
SD_DATIN;
SD_CLK_HIGH;
SD_CMD_HIGH;
SD_DATLOW;
read_status=0;
for(x=0;x<40;x++)

NerQ);
for(x=0;x<5;x++)
cmd_buffer[x]=cmd0[x];
y = send_cmd(cmd_buffer);
do
{
for(x=0;x<40;x++);
Nec();
for(x=0;x<5;x++)
emd_buffer[x]=cmd55[x];
y =send_cmd(cmd_buffer);
NerQ);
if(response_R(1)>1) //response too longor crc error
return 1;
Nec();
for(x=0;x<5;x++)
emd_buffer[x]=acmd41[x];
Ner(Q);
} while(response_R(3)==1);
Nec();
for(x=0;x<5;x++)
y =send_cmd(cmd_buffer);

NerQ);
if(response_R(2)>1)
return 1;
Nec();
for(x=0;x<5;x++)
Ner(Q);
if(response_R(6)>1)
return 1;
RCA[0]=response_buffer[1];
RCA[1]=response_buffer[2];
Nec();
for(x=0;x<5;x++)
emd_buffer[1] =RCA[0];
cmd_buffer[2] = RCA[1];
NerQ);
if(response_R(2)>1)
return 1;
Nec(Q);
for(x=0;x<5;x++)
cmd_buffer[x]-cmd7[x];

emd_buffer[1] =RCA[0];
cemd_buffer[2] = RCA[1];
Ner(Q);
if(response_R(1)>1)
return 1;
Nec();
for(x=0;x<5;x++)
Ner(Q);
if(response_R(1)>1)
return 1;
read_status =1; //sd card ready
return 0;
Khoi tao mét hé thong SD card gdm cac di liéu vao, xuat cau lénh, xung
clock...
I1T.2.2.4 Ham Doc SD Card
BYTE SD_read_lba(BYTE *buff,UINT32 Iba,UINT32 seccnt)
{
BYTEc=0;
UINT32 i,j;
Iba+=101;

for(j=0;j<seccnt;j++)
{
{
Nec();
cmd_buffer[0] = cmd17[0];
cmd_buffer[1] = (Iba>>15)&0xff;
cmd_buffer[2] = (Iba>>7)&0Oxff;
cmd_buffer[3] = (Iba<<1)&0Oxff;
cmd_buffer[4] = 0;
Iba++;
send_cmd(cmd_buffer);
NerQ);
}
while(1)
{
SD_CLK_LOW;
SD_CLK_HIGH;
if(\((SD_TEST_DAT))
break;
}
for(G=0;1<512;i1++)
{
BYTEj;
for(j=0;j<85j+*)

SD_CLK_LOW;
SD_CLK_HIGH;
c<<= 1;
if(SD_TEST_DAT)
c |= 0x01;
}
*buff=c;
bufft+;
}
for(i=0; 1<16; i++)
{
SD_CLK_LOW;
SD_CLK_HIGH;
}
}
read_status = 1; //SD data next in
return 0;
}
M.2.2.5 Ham Response
BYTEresponse_R(BYTEs)
{
BYTE a=0,b=0,c=0,r=0,crc=0;
BYTEi,j=6,k;

while(1)
{
SD_CLK_LOW;
SD_CLK_HIGH;
if(\((SD_TEST_CMD))
break;
if(crct+ >100)
return 2;
}
crc =0;
if(s == 2)
j=17;
for(k=0; k<j; k++)
{
c=0;
if(k > 0) //for crc culcar
b =response_buffer[k-1];
for(i=0; 1<8; i++)
{
SD_CLK_LOW;
if(a > 0)
c<<=1;
else

i++;
at+:
SD_CLK_HIGH;
if(SD_TEST_CMD)
c |= 0x01;
if(k > 0)
{
cre <<= |;
if((cre * b) & 0x80)
crc “= 0x09;
b <<= 1;
cre &= Ox7f;
}
}
if(s==3)
{
if( k==1 &&(!(c&0x80)))
r=;
}
response_buffer[k] = c;
}
if(s==1 || s==6)
{
if(e != ((ere<<1)+1))

IT.2.2.6 Ham Gui Di Cau Lénh.
BYTE send_cmd(BYTE*in)
{
int 1,J;
BYTEb,crc=0;
SD_CMD_OUT;
for(i=0; 1 < 5; i++)
{
b = in{i];
for(j=0; j<8; j++)

{
SD_CLK_LOW;
if(b&0x80)
SD_CMD_HIGH;
else
SD_CMD_LOW;
cre <<= |;
SD_CLK_HIGH;
if((cre “ b) & 0x80)
crc “= 0x09;

b<<=1;
}
crc &= 0x7f;
}
crc =((cre<<1)|0x01);
b =cre;
for(j=0; j<8; j++)
{
SD_CLK_LOW;
if(crc&0x80)
SD_CMD_HIGH;
else
SD_CMD_LOW;
SD_CLK_HIGH;
crc<<=1;
}
return b;
}
MI.2.2.7 Chuong Trinh Khoi Tao LCD
#include <unistd.h>
#include <string.h>
#include <io.h>
#include "system.h"
#include "LCD.h"

void LCD_Init()
{
Icd_write_cmd(LCD_16207_0_BASE,0x38);
usleep(2000);
Ied_write_cmd(LCD_16207_0_BASE,0x0C);
usleep(2000);
Ied_write_cmd(LCD_16207_0BASE,0x01);
usleep(2000);
usleep(2000);
usleep(2000);
IIT.2.2.8 Chuwong Trinh Hién Thi Text Lén Trén LCD
void LCD_Show_Text(char* Text)
{
int 1;
for(i=0;i<strlen(Text);i++)
{
Icd_write_data(LCD_162070BASE,Text[i]);
usleep(2000);
}
}
void LCD_Line2()

{
Icd_write_cmd(LCD_162070BASE,0xC0);
usleep(2000);
void LCD_Test()
{
char Text1[16] = "Altera DE2 Board";
char Text2[16] = "SD Music Player.";
// Initial LCD
LCD_Init(Q);
/! Show Text to LCD
LCD_Show_Text(Text1);
// Change Line2
LCD_Line2();
/! Show Text to LCD
LCD_Show_Text(Text2);
}
Ham xuat chudi ky tu lén man hinh LCD. Khoi tao mét LCD sau do xuat ra
chudéi Text] va Text2 1én man hinh LCD cua board DE2. Khaibao hai bién 1a Text1 va
Text2. Ghi timg ky ty cia chudi lén dia chi thanh ghi cua LCD.
1.2.3 Chwong Trinh Chinh
#include "basic_io.h"
#include "LCD.h"

#include "SD_Card.h"
int main(void)
{
UINT16 i=0,Tmp1=0,Tmp2=0;
UINT32 j=720;
BYTEBuffer[512]={0};
while(SD_card_init())
usleep(500000);
LCD_Test();
while(1)
{
SD_read_lba(Buffer,j,1);
while(i<5 12)
{
if({IORD(AUDIO_0_BASE,0))
{
Tmp1=(Buffer[i+1]<<8)|Buffer[i];
IOWR(AUDIO_0_BASE,0,Tmp1);
i+=2;
}
}

ifGj%64—0)
{
Tmp2=Tmp1*Tmp1;
IOWR(LED_RED_BASE,0,Tmp2);
IOWR(LED_GREEN_BASE,0,Tmp1);
j
IOWR(SEG7_DISPLAY_BASE,0,j);
jt;
<0;
return 0;
}
Khoi tao SD card. Xuat ky ty 1én LCD. Doc SD cardtir bd nhé dém buffer. Khi
I nhé hon 512. Néu khong doc duoc dit liéu tir thanh ghi AUDIO_0BASE.Dat bién
Tmp1 la dich trai 8 bit buffer or voi buffer [1]. Ghi Tmpl vao thanh ghi
AUDIO_0BASE. Tang i lén 2. Néu j chia hét cho 64 Tmp2 = Tmp1* Tmp1. Ghi
Tmp2 vao thanh ghi LEDREDBASE. Ghi Tmpl vao_ thanh_ ghi
LED_GREEN_BASE. Ghij vao thanh ghi SEG7_DISPLAY_BASE.

Két luan:
Laptrinh hé théng nhung ngay nay rat phd bién va ngay cang phat trién manh
mé. Dé tai tap trung nghién ctru x4y dung hé thong SD MusicPlayer. Hé thong co thé
4p dung cho cac thiét bi nghe nhac pho bién hién nay nhu may nghe nhac MP3, hay
tich hop vao trong dién thoai di dong.
Cac tmg dung cua SOPC Builderrat r6ng. SOPC Builder cé thé duoc str dung
dé tao ra nhiéu hé thong khac nhau cho nhiing muc dich khac nhau. Tuy nhién trong
gidi han cua dé tai ching em chi cé thé trinh bay vé mét phan trong cac tmg dung cia
SOPC.

Tai ligu tham khao
Cac sach tham khao
1) tut_sopc_introduction_verilogDE2.pdf CD DE2 cuaaltera.
2) tut_nios2_introduction.pdf CD DE2 cuaaltera.
3) WM8731.pdf CD DE2cuaaltera.
4) Introduction to the Altera SOPC Builder Using Verilog Design CD DE2 cua
Altera.
5) Proof that C can match or beat assembly.
6) The New Standard, Derek M. Jones, 2005

7) C Programming for Embedded Systems, Kirk Zurell
8) Tw hoc lép trinh Visual C++ MFC qua cac vi du, Nguyén Dinh Té, NXB Lao
dong — Xa H6i.
Cac website tham khao
1) www.altera.com
2) www.dientuvienthongnet
3) btte:/Arwwdtviore
4) bttp:/sywwdesign-reuse.com
5) http://www.reuters.com
6) htto://www.bytecrafit.com

Danhsach hinh
Phu Luc
Hinh 1.1.1. Hién thi chinh Quartus Ul. o.e.cccccccccsccccececcsceseseecseceeeseseeeeees 3
Hinh 1.1.2. vi du file menu oo... eccccceeeseccceeesecceeesseceseesessesenenes4
Hinh 1.1.3. Thao tac thuc hién bang Wizard Tasks .......c.ccccceeseseeeeeeeees. 5
Hinh 1.1.4. Tao mOt project MO1. ....... cc ceceeeeeesseessssssssssseesssesseesseeees 6
Hinh 1.1.5. Phan mém QuartusII sé tao ra mét thu muccho project...... 6
Hinh 1.1.6. Wizard cé thé bao gém file thiét ké ly thuyét. 0...7
Hinh 1.1.7. Chon m6tho thiét bi va m6t thiét bi cu thé oes8
Hinh 1.1.8. Cong cu EDA Kha ou... eeccceeeessesensenccaeeececeeceeeeceeeeeeees 9
Hinh 1.1.9. Tom tat cia viéc cai dat project. oo. cccecseessseseceeesseseseeees 10
Hinh 1.1.10. Quartus IT sau khi project duoc tao ou... eee eeeeeeeeeeeeees 11
Hinh 1.2.1: So dé hé théng SOPCtich hop trén PLD cuaAltera .......... 12
Hinh 1.2.2: Cac thanh phan trong nhan system contents ..........c.ceeeee. 13
Hinh 1.2.3. tao moi mot SOPC Builder. oo. ceeececceeeeeeeeees 15
Hinh 1.2.4. add cpu_0 vao dé tao két n6i. oo. ccccceeeesceeeseeseeteeseeeees 16
Hinh 1.2.5. thiét ké module cpu0. ....ccccccccscssescsesececesesesssescecececeeeeeeeevees 17
Hinh 1.2.6. add cdc module can thiét .......c.ccccsesscesessssssssseesecseeeseseeeeees 17
Hinh 1.2.7. lién két cpu0 véi onchipmemory20 .....eeeeeeseceeeeeeeeeeees 18
Hinh 1.2.8. bién dich thanh CONG ou... eeeeeesssneesrsssessssssesseeeseeeseees 19
Hinh 1.2.9, Gan pin oo... ccccccccccecccceccceeceseeessesesessessaueaaaaeceseeeeeceeeeeeeeees 19
Hinh 1.2.10. Quartus IT bién dich thanh Ong ......... ce cccceccceeeeeeeees20
Hinh 1.2.11. lap trinh Nios IL IDE ou... cccccssssssseeeeeceeeeeesenseeees21
Hinh 1.3.1 T6 Chitc BO NAG Va VO w.ceecccecesesesessessesesessesseeseeseaeaeeaees27
Hinh 1.3.2 cac dinh dang cua cac tap lénh NIOS II .......... ee29
Hinh 1.4.1 Board DE2 wc ccccccceeesseessessessnnnsnaaaeeeeeceeeeeeeeeeeeees 30
Hinh 1.4.2 Biéu Dé Khdi Cla Boatd DE2 ou... cecccceccecsessesceseeteeteseeseenen31
Hinh 1.4.2. Board DE2 cia Altera oo... eccesssseneesessssssssseseseeeeeees 32
Hinh 1.4.3 Ung Dung TV Box ....cccccecsscscssesssssesescscncsevecscecsessvacsceesevaees 34
Hinh 1.4.5 Karaoke Machine va SD Music Player......................::00000006 35
Hinh 2.1.1 So Dé Khéi Chirc Nang WM873 1/L o.c.ecceeccessceceeseeeeeeeceeess38
Hinh 2.1.2 Lupe D6 Line NgG Va0. ..ceceeecescesecesesesssecesestevseseseseeteveveees 39
Hinh 2.2.1 Dinh Tuyén Tin Hiéu Trong Ché D6 Bypass.............ceeeee48
Hinh 2.2.2 Luge Dé Ché D6 Sidetone ....c.c.cccccecccsssecessesescssesescesescseeseeees49
Hinh 2.3.1 Mach Ung Dung May Tao Dao DongCrystal. .......eeeeeeee 52
Himh 2.5.1 SO dG FAT .ccccccccccccsscsscssessessesssscssceseeseesesssseeaceseeseeseeseaneaeeaes64
Hinh 2.5.2 phan manh trong Fat ........... ccc cccccssssssssensencccaeeeceeeeceeeeeeeeeees 64
Hinh 3.1 so dé khéi cua thiét ké SD music player. .....c.ccecseseeeeeeeeeeeees 70

Danh sach bang
Bang 1 Cac Thanh Ghi Da Nang. ou... ecesscenseresrseeessssssesseeeseeeeeees25

Bang 2 Thanh Ghi Diéu Khién oo... cccecececcecceecececececeeeseeeeverecseeceeeees: 26
Bang 3 Diéu Khién Phan Mém Line Ng VA0 .....eeeeeeseeseseeseceeeeeeseeeeees40
Bang 4 Diéu Khién Phan Mém Ng6 Vao Microphone. ............cceeeeeeee-41
Bang 5 Diéu Khién Phan Mém ADCou... .ececccsesecesecssesssesveveceeeeseesevees42
Bang 6 Diéu Khién Phan Mém ADC ou.....ceecececesecesscecesessessssesesseteveveees43
Bang 7 Diéu Khién Phan Mém DAC... .cceececsecseeccesececeseeceeeserececsceeeees: 44
Bang 8 Diéu Khién Phan Mém Line Output. ......c.ccceeeeeeeeeeeeeeeseeeeeeeees45
Bang 9 Diéu Khién Phan Mém Ngé Ra Headphone..............cceceeceeeeeees47
Bang 10 Diéu Khién Phan Mém Trong Ché Dé Bypass............eeeeeeeee48
Bang 11 Ché D6 Sidetone oo... cecccsesececececescssecsessscececesesssvevarececseeeeeeevens49
Bang 12 Diéu khién phan mém cia reset. .......ceeesesesesesssesesseceeeeeseeeeees 50
Bang 13 Diéu Khién Phan Mém Cita L6i Clock. oo... eeseeeeeeeeeeee51
Bang 14 Lap Trinh Cua CLKOUT uu... cesesesnsseesesessesseeeseeeeeees 53
Bang 15 Giao Dién Lua Chon MODE..............ccccceeeseeseeeeseeeeeeseeeeseeeeeees 53
Bang 16 Lua Chon Dia Chi Giao Dién MPU 2 — Wire......................0606 54
Bang 17 Diéu Khién Phan Mém Ché D6 Bao Tén Nang Lvong...........56
Bang 18 Ché D6 Stanby ....ccccccccsesecececesessssecececececeeesesveveverececseeeeseees 58
Bang 19 Ché D6 Powerofe ......c.cccsccesecesssesscesecesesesscestesecestesseseeesteveveen 58
Bang 20Ban D6 Thanh Ghi Chuong Trinh 0.0... cceecceceeeseesececeeeeeeeeeees 59
Bang 21 Dat Tinh Cla BO Loc S6 oo. eeceecessssssscecesessssssseevsceceeseseevees 61
Bang 22 Lap Trinh Ché D6 Master/Slave .......:.cccccsccsccessesseesececeseeeseeeees 61
Bang 23. Bang so sanh cac dinh dang FAT... cecccceeceeeeeeeeeees 68

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DO AN TOT NGHIEP GVHD: Th.

S HUYNH HUU THUAN

SVTH: NGUYEN MINH HIEU —- HUYNH CONG PHU Trang 1

Chuong 3 Hé Thong Tong Quat oo... cccccccceeceeeceeeeeeeeaeneeeeees 70

SVTH: NGUYEN MINH HIEU —- HUYNH CONG PHU Trang 2

Giéi Thigu Vé Phan Mém

tp: ‘fw. altera.com

1E)\ Spstem{Frocessng JEntalnfoJIne,Waming JL GittealWaring J Eror [

Hinh1.1.1, Hién thi chinh QuartusII.

SVTH: NGUYEN MINH HIEU - HUYNH CONG PHU Trang 3

File Edit View Project Assignment

Hinh 1.1.2. vi du file menu

SVTH: NGUYEN MINH HIEU - HUYNH CONG PHU Trang 4

[ere re eee oad

[7 Don't show me this introduction again

Hinh 1.1.3, Thao tac thye hién bing Wizard Tasks

SVTH: NGUYEN MINH HIEU - HUYNH CONG PHU Trang 5

New Project Wizard

\what is the working drectory forthis projec!?

Use Exisiing Project Settings

s Back Next> Finish Cancel

Hinh 1.1.4. Tao mt project mdi.

SVTH: NGUYEN MINH HIEU - HUYNH CONG PHU Trang 6

New Project Wizard: Add Files [page 2 of 5]

File name Type Add All

Specty the path names of any non-default fbraries UserLibraries..

< Beck Finish Cancel

Hinh1.1.6. Wizard cé thé bao gémfile thiét ké ly thuyét.

SVTH: NGUYEN MINH HIEU - HUYNH CONG PHU Trang 7

New Project Wizard: Family & Device Settings [p..

Pin count Ary 2

Speed grade: [Ary *

EP2C20F4848 Core voltage: 1.2

Hinh 1.1.7. Chon mét hothiét bi va mét thiét bi cu thé

SVTH: NGUYEN MINH HIEU - HUYNH CONG PHU Trang 8

New Project Wizard: EDA Tool Settings [page 4 of...

[~ EDA, simulation tool:

[EDA timing snabsistoct [SSC

< Back Finish Cancel

Hinh 1.1.8. Céng cu EDA khac

SVTH: NGUYEN MINH HIEU - HUYNH CONG PHU Trang 9

< Back Concel

Hinh 1.1.9, Tom tat cia viée cai dit project.

SVTH: NGUYEN MINH HIEU - HUYNH CONG PHU Trang 10

€ QuartusII - D:/introtutorial/light - light

©Aybicisichy EBFiee |g Design Units

t. ProcessingAA Esra info Ainfo }owannaA, Cnicalwenng Enonjf

SVTH: NGUYEN MINH HIEU - HUYNH CONG PHU Trang 11

System Module User

Hinh1.2.1: So dé vi du vé hé thong SOPCtich hop trén PLD cia Altera

> Cac IP va cdc két néingoai vi

> Cac thiét bi lién lac ngoaivi

> Cac léi DSP

SVTH: NGUYEN MINH HIEU - HUYNH CONG PHU Trang 12

> Thém vao hoiloai ra céc componenttrong hé thing.

> Cdu hinh cdc component.

‘Atara S0°C Bude a

Hinh Cac thanh phan trong nhin system contents

Thanh phan Chir ning

SVTH: NGUYEN MINH HIEU - HUYNH CONG PHU Trang 13

Available Component) no. Cham mau nay co y nghia sau:

e Cham trang: thanh phan chwacai dat

e Dia chico ban cho mdicéng slave