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Advanced Power MOSFET SSP2N60A

FEATURES
BVDSS = 600 V
Avalanche Rugged Technology
Rugged Gate Oxide Technology
RDS(on) = 5.0 Ω
Lower Input Capacitance ID = 2 A
Improved Gate Charge
Extended Safe Operating Area
Lower Leakage Current : 25 µA (Max.) @ VDS = 600V
TO-220
Lower RDS(ON) : 3.892 Ω (Typ.)
1
2
3

1.Gate 2. Drain 3. Source

Absolute Maximum Ratings

Symbol Characteristic Value Units
VDSS Drain-to-Source Voltage 600 V
o
Continuous Drain Current (TC=25 C ) 2
ID o A
Continuous Drain Current (TC=100 C ) 1.3
IDM Drain Current-Pulsed O
1 6 A
VGS DataSheet4U.com +
Gate-to-Source Voltage _ 30 V DataShee
EAS Single Pulsed Avalanche Energy O
2 131 mJ
IAR Avalanche Current O1 2 A
EAR Repetitive Avalanche Energy O1 5.4 mJ
dv/dt Peak Diode Recovery dv/dt O3 3.0 V/ns
Total Power Dissipation (TC=25 oC ) 54 W
PD o
Linear Derating Factor 0.43 W/ C
Operating Junction and
TJ , TSTG - 55 to +150
Storage Temperature Range
o
C
Maximum Lead Temp. for Soldering
TL 300
Purposes, 1/8” from case for 5-seconds

Thermal Resistance
Symbol Characteristic Typ. Max. Units
R θJC Junction-to-Case -- 2.32
R o
θCS Case-to-Sink 0.5 -- C /W
R θJA Junction-to-Ambient -- 62.5

Rev. B

©1999 Fairchild Semiconductor Corporation

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N-CHANNEL
SSP2N60A POWER MOSFET

Electrical Characteristics (TC=25 oC unless otherwise specified)

Symbol Characteristic Min. Typ. Max. Units Test Condition
BVDSS Drain-Source Breakdown Voltage 600 -- -- V VGS=0V,ID=250 µA
∆BV/∆TJ Breakdown Voltage Temp. Coeff. -- 0.77 -- V/ oC ID=250 µA See Fig 7
VGS(th) Gate Threshold Voltage 2.0 -- 4.0 V VDS=5V,ID=250 µA
Gate-Source Leakage , Forward -- -- 100 VGS=30V
IGSS nA
Gate-Source Leakage , Reverse -- -- -100 VGS=-30V
-- -- 25 VDS=600V
IDSS Drain-to-Source Leakage Current µA VDS=480V,TC=125 C
o
-- -- 250
Static Drain-Source
RDS(on) -- -- 5.0 Ω VGS=10V,ID=1A O
4
On-State Resistance
gfs Forward Transconductance -- 1.37 -- Ω VDS=50V,ID=1A O
4

Ciss Input Capacitance -- 315 410

VGS=0V,VDS=25V,f =1MHz
Coss Output Capacitance -- 38 45 pF
See Fig 5
Crss Reverse Transfer Capacitance -- 14 17
td(on) Turn-On Delay Time -- 12 35
VDD=300V,ID=2A,
tr Rise Time -- 15 40
ns RG=18 Ω
td(off) Turn-Off Delay Time -- 41 90
See Fig 13
tf Fall Time -- 16 40 O
4 O
5
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DataShee
Qg Total Gate Charge -- 15 21 VDS=480V,VGS=10V,
Qgs Gate-Source Charge -- 2.6 -- nC ID=2A
Qgd Gate-Drain( “Miller” ) Charge -- 6.7 -- See Fig 6 & Fig 12
O
4 O
5

Source-Drain Diode Ratings and Characteristics

Symbol Characteristic Min. Typ. Max. Units Test Condition
IS Continuous Source Current -- -- 2 Integral reverse pn-diode
A
ISM Pulsed-Source Current O
1 -- -- 6 in the MOSFET
VSD Diode Forward Voltage O4 -- -- 1.4 V TJ=25 oC ,IS=2A,VGS=0V
o
trr Reverse Recovery Time -- 280 -- ns TJ=25 C ,IF=2A
Qrr Reverse Recovery Charge -- 0.62 -- µC diF/dt=100A/ µs O
4

Notes ;
O1 Repetitive Rating : Pulse Width Limited by Maximum Junction Temperature
2 L=60mH, I =2A, V =50V, R =27 Ω, Starting T =25 C
o
O AS DD G J

O3 ISD <_ 2A, di/dt < 80A/ µs, VDD < BVDSS , Starting T J =25 oC
_ _
O4 Pulse Test : Pulse Width = 250 µs, Duty Cycle < _ 2%
O5 Essentially Independent of Operating Temperature

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N-CHANNEL
POWER MOSFET SSP2N60A
Fig 1. Output Characteristics Fig 2. Transfer Characteristics
VGS

[A]
Top : 15V
[A]

10 V
8.0 V
7.0 V

ID , Drain Current
100 100
ID , Drain Current

6.0 V
5.5 V
5.0 V
Bottom : 4.5 V

150 oC

10-1 10-1
@ Notes :
25 oC 1. VGS = 0 V
@ Notes : 2. VDS = 50 V
1. 250 µs Pulse Test 3. 250 µs Pulse Test
- 55 oC
2. TC = 25 oC
10-2 10-2
10-1 100 101 2 4 6 8 10
VDS , Drain-Source Voltage [V] VGS , Gate-Source Voltage [V]
[A]

Fig 3. On-Resistance vs. Drain Current Fig 4. Source-Drain Diode Forward Voltage
Drain-Source On-Resistance

10
IDR , Reverse Drain Current

8 VGS = 10 V
100
RDS(on) , [Ω]

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10-1 DataShee
2 @ Notes :
1. VGS = 0 V
150 oC
@ Note : TJ = 25 oC 25 oC 2. 250 µs Pulse Test

0 10-2
0 1 2 3 4 5 6 0.2 0.4 0.6 0.8 1.0 1.2
ID , Drain Current [A] VSD , Source-Drain Voltage [V]

Fig 5. Capacitance vs. Drain-Source Voltage Fig 6. Gate Charge vs. Gate-Source Voltage
500
[V]

Ciss= Cgs+ Cgd ( Cds= shorted )

Coss= Cds+ Cgd VDS = 120 V
10
[pF]

400 Crss= Cgd

VGS , Gate-Source Voltage

C iss VDS = 300 V

VDS = 480 V
Capacitance

300

200 5

C oss @ Notes :
1. VGS = 0 V
100 C rss 2. f = 1 MHz

@ Notes : ID = 2.0 A
00 0
10 101 0 3 6 9 12 15
VDS , Drain-Source Voltage [V] QG , Total Gate Charge [nC]

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N-CHANNEL
SSP2N60A POWER MOSFET
Drain-Source Breakdown Voltage

Fig 7. Breakdown Voltage vs. Temperature Fig 8. On-Resistance vs. Temperature

1.2 3.0

Drain-Source On-Resistance
BVDSS , (Normalized)

RDS(on) , (Normalized)
2.5
1.1
2.0

1.0 1.5

1.0
0.9 @ Notes : @ Notes :
1. VGS = 0 V 1. VGS = 10 V
0.5
2. ID = 250 µA 2. ID = 1.0 A

0.8 0.0
-75 -50 -25 0 25 50 75 100 125 150 175 -75 -50 -25 0 25 50 75 100 125 150 175
TJ , Junction Temperature [ oC] TJ , Junction Temperature [ oC]

Fig 9. Max. Safe Operating Area Fig 10. Max. Drain Current vs. Case Temperature
2.5
[A]

[A]

Operation in This Area

is Limited by R DS(on)
101 2.0
ID , Drain Current

ID , Drain Current

100 µs
1 ms
1.5
10 ms
100
DC

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1.0
DataShee
10-1 @ Notes :
1. TC = 25 oC 0.5
2. TJ = 150 oC
3. Single Pulse
10-2 0.0
100 101 102 103 25 50 75 100 125 150
VDS , Drain-Source Voltage [V] Tc , Case Temperature [ oC]

Fig 11. Thermal Response

Thermal Response

D=0.5
100

0.2 @ Notes :
1. Zθ J C (t)=2.32 o C/W Max.
0.1 2. Duty Factor, D=t1 /t2
0.05 3. TJ M -TC =PD M *Zθ J C (t)
10- 1
0.02
Z JC(t) ,

0.01 PDM
single pulse
t1
t2
θ

10- 2
10- 5 10- 4 10- 3 10- 2 10- 1 100 101
t 1 , Square Wave Pulse Duration [sec]

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N-CHANNEL
POWER MOSFET SSP2N60A
Fig 12. Gate Charge Test Circuit & Waveform

“ Current Regulator ”
VGS
Same Type
50KΩ as DUT Qg
12V 200nF
300nF 10V

VDS
VGS Qgs Qgd

DUT
3mA
R1 R2

Current Sampling (IG) Current Sampling (ID)

Charge
Resistor Resistor

Fig 13. Resistive Switching Test Circuit & Waveforms

RL
Vout Vout
90%
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( 0.5 rated VDS )
DataShee
RG
DUT 10%
Vin
10V
td(on) tr td(off)
tf
t on t off

Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms

BVDSS
LL 1
EAS = ---- LL IAS2 --------------------
VDS 2 BVDSS -- VDD
Vary tp to obtain ID BVDSS
required peak ID IAS

RG C VDD ID (t)
DUT
VDD VDS (t)
10V
tp tp Time

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N-CHANNEL
SSP2N60A POWER MOSFET

Fig 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms

DUT +

VDS

--

IS
L

Driver
VGS
RG Same Type
as DUT VDD

VGS • dv/dt controlled by “RG”

• IS controlled by Duty Factor “D”

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Gate Pulse Width DataShee
D = --------------------------
Gate Pulse Period 10V
( Driver )

IFM , Body Diode Forward Current

IS
( DUT ) di/dt

IRM

Body Diode Reverse Current

VDS
( DUT ) Body Diode Recovery dv/dt

Vf VDD

Body Diode
Forward Voltage Drop

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PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or This datasheet contains the design specifications for
In Design product development. Specifications may change in
any manner without notice.

Preliminary First Production This datasheet contains preliminary data, and

supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

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Semiconductor reserves the right to make changes at
any time without notice in order to improve design.

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that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.

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