Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
with SystemC
University of Tübingen
Wilhelm-Schickard-Institut
Department of Computer Engineering
University of
Tübingen Contents
Department of
Computer
Engineering
q Background & Basics
m System-on-Chip Design
Background
& Basics m C/C++ Based System Design
Tool m Processes
Support
m Ports & Signals
SystemC 1.1
m Data Types & Fixed Point Data Types
q Design Example B
Background m JPEG Compression / Decompression Stream
& Basics
Design
Activities q Tool Support
Tool m Synopsys: SystemC Compiler
Support
m CoWare: N2C
SystemC 1.1
m C-Level Design: System Compiler
m Frontier Design: AxRT Builder
Joachim
Gerlach
q Outlook to SystemC 1.1
time
Wolfgang 1980 1990 2000
Rosenstiel (source: MEDEA Design Automation Roadmap 1999)
Design
Activities
Tool
Support
SystemC 1.1
Wolfgang
Rosenstiel
SystemC 1.0
algorithmic architectural
Design
models models
Example A
hardware architecture
software architecture
Tool
device memory
Support driver map
SystemC 1.1 processor &
RTOS peripherals
Wolfgang application
Rosenstiel user specific
software co-processor
Tool
m
System SoC
Co-design, co-simulation, co-verification, co-debugging, ...
Support
SystemC 1.1
q Re-use aspect
Architect
Design Marketing
& Sales
m OptimumC/C++
re-use support by object-oriented techniques
HDL
Wolfgang
m Efficient testbench re-use
Rosenstiel
q Software
Especially C/C++ is widespread Hardware
and commonly used !
Designer Designer
Tool
m Reactivity
Support l Hardware is inherently reactive, responds to stimuli,
SystemC 1.1 interacts with its environment (→ requires handling of exceptions)
m Hardware data types
Wolfgang l Bit type, bit-vector type, multi-valued logic types,
Rosenstiel signed and unsigned integer types, fixed-point types
q Step-1: C
Background
& Basics synthesizable
restriction to subset of C
SystemC 1.0
synthesizable subset
Design
Example A
synthesizable
q Step-2: C++ subset of C++
Design
Example B extension by
Design hardware-related hardware type
Activities
components communication hardware
Tool data types
Support m new language constructs
synthesizable
SystemC 1.1
(HardwareC, C*) notion subset
of time reactivity
m library based approach
concurrency
Wolfgang (SystemC, Cynlib)
Rosenstiel
Design
Example B q Requirements
Design
Activities m Allow hardware/software co-design and co-verification
Tool m Fast simulation for validation and optimization
Support
m Smooth path to hardware and software
SystemC 1.1
m Support of design and architectural re-use
Joachim
Gerlach
System
Background C/C++ Software
& Basics
C/C++ Testbench Component
SystemC 1.0
DSP
Design IP-Core
Example A
Modeling C/C++ Hardware ASIC
Design Constructs Component
Example B Interface
Design
Activities
Tool SystemC
Support Standard
SystemC 1.1
C++ Compiler
Joachim
Gerlach
Executable = Simulator
Background
& Basics
SystemC 1.0
system 4. hand over
Design architect
Example A specification
C/C++ document
Design
Example B
Design HDL
Activities
1. conceptualize 6. (re)implement in HDL
Tool
2. simulate in C/C++ 7. (re)validate HDL
7. implementation
Support 3. write specification
SystemC 1.1 3. document 8. synthesize from HDL
hardware
Wolfgang designer
Rosenstiel
Background C/C++
& Basics
SystemC 1.0
1. conceptualize
Design 2. simulate in C/C++
Example A
3. write specification document
Design
Example B
system 4. hand over
Design architect • executable specification hardware
Activities • testbenches designer
Tool • written specification C/C++
Support
5. understand specification
SystemC 1.1
6. refine in C/C++
7. validate re-using testbenches
Wolfgang
Rosenstiel 8. synthesize from C/C++
Wolfgang
Rosenstiel Software Hardware
Designer Designer
TM
Background
S Y S T E M C is...
& Basics
Tool
... a cycle-accurate high-speed simulation
Support
SystemC 1.1
Wolfgang
Rosenstiel
your standard
C/C++ development DSP
Background
environment ASIC
& Basics
Interface
header files IP-Core
SystemC 1.0 compiler
........
Design libraries
Example A
linker
....
simulation kernel source files
Design for system and
Activities testbenches
„make“
Tool
Support e
utabl on “
SystemC 1.1 ex ec icati
„ ecif a.out
sp
executable = simulation
Wolfgang
Rosenstiel
Background
& Basics
Steering Group SystemC v0.9
SystemC 1.0 including:
• Modeling specification
Design
Example A • Source code
(reference implementation)
Design download • Reference manual
Example B
Design
Activities
Tool
Support
www.SystemC.org click-through web-based
license agreement
SystemC 1.1
Wolfgang User
Rosenstiel
Wolfgang
q Synopsys
Rosenstiel
q Texas Instruments
Wolfgang
Rosenstiel
Background
& Basics
SystemC 1.0
V0.9 launches V1.0 release
Design Scenery 9/27/1999 3/28/2000
Example A
Design
Example B
Tool
Support HDL constructs
SystemC 1.1
1997 1998 1999 2000
Wolfgang
Rosenstiel
Wolfgang
Rosenstiel 2000 2001
January 31 March 28 June 30 September 4-8 March 12-16
2000 2000 2000 2000 2001
SystemC 1.0
University of Tübingen
Wilhelm-Schickard-Institut
Department of Computer Engineering
University of
Tübingen Modules
Department of
Computer
Engineering
q Modules are basic building blocks of a SystemC design
q A module contains processes (Õ functionality)
Background and/or sub-modules (Õ hierarchical structure)
& Basics
SystemC 1.0
SC_MODULE( module_name ) {
Design
Example A
// Declaration of module ports
// Declaration of module signals
Design
Example B // Declaration of processes
// Declaration of sub-modules
Design
Activities SC_CTOR( module_name ) { // Module constructor
Tool
// Specification of process type and sensitivity
Support // Sub-module instantiation and port mapping
SystemC 1.1 }
// Initialization of module signals
};
Joachim
Gerlach
Design
.....
Example A
Tool
Support struct module_name : sc_module {
SystemC 1.1 .....
};
Joachim
Gerlach
Design
Example B q Resolution
Design m SystemC supports resolved ports and signals
Activities
m Resolved ports/signals have 4-valued logic type (0,1,Z,X)
Tool
Support m Resolved ports/signals allow multiple drivers
Design
Example B
Example: sc_clock my_clk (“CLK”, 20, 0.5, 5, true);
true
Design
Activities false 5 20
Tool 0 5 15 25 35 45 55
Support
q Clock binding:
SystemC 1.1
Example: my_module.clk( my_clk.signal() );
Joachim
Gerlach
Design
Example A q SystemC types
Design m 2-value (‘0’, ‘1’) logic / logic vector
Example B
m 4-value (‘0’, ‘1’, ‘Z’, ‘X’) logic / logic vector
Design
Activities m Arbitrary sized integer (signed/unsigned)
SystemC 1.1
Joachim
Gerlach
Design m long
Activities
m unsigned long
Tool
Support
q Floating point types
SystemC 1.1
m float
m double
Joachim
Gerlach m long double
Design q Features:
Example B
m Mixed use of operand types sc_bit and sc_logic
Design
Activities m Use of character literals for constant assignments
Tool
Support q sc_bit / sc_logic operators
SystemC 1.1
Bitwise & (and) | (or) ^ (xor) ~ (not)
Assignment = &= |= ^=
Joachim
Gerlach Equality == !=
SystemC 1.0
q Arbitrary precision integer types
Design
Example A m Signed: tsc_bigint<n> (n: word length, n > 64)
Design m Unsigned: sc_biguint<n> (n: word length, n > 64)
Example B
Design q Features:
Activities
m Mixed use of operand types sc_int, sc_uint, sc_bigint,
Tool sc_biguint and C++ integer types
Support
m Truncation and/or sign extension if required
SystemC 1.1
m 2’s complement representation
Joachim
Gerlach
Tool
Support
SystemC 1.1
Joachim
Gerlach
SystemC 1.1
Joachim
Gerlach
SystemC 1.0
( 1.75 )10 = ( 0001.1100 )2
Design 4
Example A 8
Design
Example B 1’s complement of ( 0001.1100 )2 = ( 1110.0011 )2
Design 2’s complement of ( 0001.1100 )2 = ( 1110.0100 )2
Activities
SystemC 1.1 1 1 1 0 0 1 0 0
Background
& Basics Quantization Mode Overflow Mode
SystemC 1.1
Joachim
Gerlach
Background q In SC_MODULE:
& Basics
// sub-module declaration
SystemC 1.0 module_type *my_module;
Design
Example A q In the module constructor of SC_MODULE:
Design
Example B // sub-module instantiation and port mapping
SC_CTOR( module_name ) {
Design
Activities my_module = new module_type ( “label”);
Tool my_module -> in1 (sig1);
Support my_module -> in2 (sig2);
my_module
my_module -> out1 (sig3);
SystemC 1.1
} sig1
in1 sig3
out1
in2
Joachim sig2
Gerlach
Design
Example A q Process Activation
Design m Processes have sensitivity lists
Example B
m Pocesses are triggered by events on sensitive signals
Design
Activities
q Process Types
Tool
Support m Method (SC_METHOD)
asynchronous block, like a sequential function
SystemC 1.1
m Thread (SC_THREAD)
asynchronous process
Joachim
Gerlach m Clocked Thread (SC_CTHREAD)
synchronous process
Design execution
no yes yes
Example A suspend
Design suspend wait()
Example B - wait()
& resume wait_until()
Design
Activities construct SC_METHOD(p); SC_THREAD(p); SC_CTHREAD
& (p,clock.pos());
Tool sentisize sensitive(s); sensitive(s);
Support method sensitive_pos(s); sensitive_pos(s); SC_CTHREAD
SystemC 1.1 sensitive_neg(s); sensitive_neg(s); (p,clock.neg());
modeling combinational sequential logic sequential logic
example logic at RT level at higher design
Joachim
Gerlach (hardware) (asynchronous levels
reset, etc.)
Tool i1
Support q Definition of member function
o1
(in SC_MODULE or somewhere else) i2
SystemC 1.1
// process specification
void module_name::my_process () {
Joachim o1 = i1 + i2
Gerlach .....
}
Background
& Basics SC_MODULE( plus ) { void plus::do_plus() {
sc_in<int> i1; int arg1;
SystemC 1.0
sc_in<int> i2; int arg2;
Design sc_out<int> o1; int sum;
Example A
void do_plus(); arg1 = i1.read();
Design
Example B
arg2 = i2.read();
SC_CTOR( plus ) {
sum = arg1 + arg2;
Design SC_METHOD( do_plus );
o1.write(sum);
Activities sensitive << i1 << i2;
}
Tool }
Support };
Background
& Basics SC_MODULE( plus ) { void plus::do_plus() {
sc_in<int> i1; int arg1;
SystemC 1.0
sc_in<int> i2; int arg2;
Design sc_out<int> o1; int sum;
Example A
void do_plus(); while ( true ) {
Design
arg1 = i1.read();
Example B SC_CTOR( plus ) {
arg2 = i2.read();
Design SC_THREAD( do_plus );
sum = arg1 + arg2;
Activities sensitive << i1 << i2;
o1.write(sum);
Tool }
Support }; wait();
}
SystemC 1.1
}
Joachim
Gerlach
Background
& Basics SC_MODULE( plus ) { void do_plus() {
sc_in_clk clk; int arg1;
SystemC 1.0
int arg2;
sc_in<int> i1;
Design int sum;
Example A sc_in<int> i2;
sc_out<int> o1; while ( true ) {
Design
Example B
arg1 = i1.read();
void do_plus();
arg2 = i2.read();
Design sum = arg1 + arg2;
Activities
SC_CTOR( plus ) {
SC_CTHREAD( do_plus, clk.pos() ); o1.write(sum);
Tool }
Support wait();
};
}
SystemC 1.1
}
Joachim
Gerlach
SystemC 1.0 q Halt process execution until an event occurs (SC_CTHREAD only)
Design m wait_until ( my_bool_sig.delayed() == true )
Example A
Background Step2: All SC_METHOD / SC_THREAD processes with inputs that have
& Basics changed are executed. The entire bodies of SC_METHOD
processes are executed. SC_THREAD processes are executed
SystemC 1.0
until the next wait() statement suspends execution.
Design SC_METHOD / SC_THREAD processes are not executed in a
Example A fixed order.
Design Step3: All SC_CTHREAD processes that are triggered have their
Example B outputs updated and are saved in a queue to be executed in
step 5. All outputs of SC_METHOD / SC_THREAD processes
Design
Activities that were executed in step 1 are also updated.
Tool Step 4: Step 2 and step 3 are repeated until no signal changes ist value.
Support
Step 5: All SC_CTHREAD processes that were triggered and queued in
SystemC 1.1 step 3 are executed. There is no fixed execution order of these
processes. Their outputs are updated at the next active edge
(when step 3 is executed), and therefore are saved internally.
Joachim
Gerlach
Step6: Simulation time is advanced to the next clock edge and the
scheduler goes back to step 1.
Design Example A
University of Tübingen
Wilhelm-Schickard-Institut
Department of Computer Engineering
University of
Tübingen SystemC: Example-1
Department of
Computer
Engineering
Example
Background
Two processes (process_1 and process_2)
& Basics alternately incrementing an integer value
SystemC 1.0
Design process_1
Example A
int
a +5 b
Design
bool
Example B ready_a ready_b
Design
Activities
process_2
Tool
Support int
b +3 a
SystemC 1.1 bool
ready_b ready_a
Wolfgang
Rosenstiel
SystemC 1.0
Design
Example A
process_1.cc process_2.cc main.cc
Design
Example B
library
Design
Activities
Tool
Support g++
SystemC 1.1
a.out
Wolfgang
Rosenstiel
executable = simulation
SC_MODULE( process_1 ) {
Background
& Basics // Ports
// implementation file: process_1.cc
sc_in_clk clk;
SystemC 1.0 sc_in<int> a; #include "systemc.h"
sc_in<bool> ready_a; #include "process_1.h"
Design sc_out<int> b;
Example A sc_out<bool> ready_b; void process_1::do_process_1()
{
Design // Process functionality int v;
Example B void do_process_1();
while ( true )
Design // Constructor {
Activities SC_CTOR( process_1 ) { wait_until( ready_a.delayed() == true );
SC_CTHREAD( do_process_1 , clk.ps() ); v = a.read();
Tool } v += 5;
Support cout << "P1: v = “ << v << endl;
}; b.write( v );
SystemC 1.1 ready_b.write( true );
wait();
ready_b.write( false );
Wolfgang }
Rosenstiel }
SC_MODULE( process_2 ) {
Background
& Basics // Ports
// implementation file: process_2.cc
sc_in_clk clk;
SystemC 1.0 sc_in<int> a; #include "systemc.h"
sc_in<bool> ready_a; #include "process_2.h"
Design sc_out<int> b;
Example A sc_out<bool> ready_b; void process_2::do_process_2()
{
Design // Process functionality int v;
Example B void do_process_2();
while ( true )
Design // Constructor {
Activities SC_CTOR( process_2 ) { wait_until( ready_a.delayed() == true );
SC_CTHREAD( do_process_2 , clk.ps() ); v = a.read();
Tool } v += 3;
Support cout << "P2: v = “ << v << endl;
}; b.write( v );
SystemC 1.1 ready_b.write( true );
wait();
ready_b.write( false );
Wolfgang }
Rosenstiel }
#include "systemc.h"
Background #include "process_1.h"
& Basics #include "process_2.h"
sc_start(100000);
Wolfgang return 0;
Rosenstiel }
Design Example B
University of Tübingen
Wilhelm-Schickard-Institut
Department of Computer Engineering
University of
Tübingen SystemC Design Example
Department of
Computer
Engineering
q Background:
Background
& Basics
SystemC C / C++
SystemC 1.0
Design
Example A
„top-down“
Design „bottom-up“
Example B
Design
Activities
HDL
Tool
„non-coded“ SystemC
Support
SystemC 1.1
Transforming HDL into SystemC Transforming C/C++ into SystemC
Creating new designs in SystemC • Many algorithms exist in C/C++
Joachim
Gerlach
• Many standardization committees
• (e.g., ISO) use C specifications
SystemC 1.0
JPEG Compressed
Reader Encoder
Design data stream
Example A Output Picture
(pgm)
Design Input Picture
Example B (pgm)
JPEG
Design Decoder Writer
Activities
Tool
Support
Reader
Background
& Basics
SystemC 1.0
DCT IRLEH
Design
Example A
Encoder
Design Quant IZigZag
Example B
Design
Activities ZigZag IQuant
Tool Decoder
Support
Joachim Writer
Gerlach
output pgm-file
data
data
ready ready
Reader data
data
ready ready
Background
& Basics
data data ready
SystemC 1.0 ready
DCT IRLEH
Design data data data data
ready ready ready ready
Example A
Encoder
Design Quant IZigZag
Example B
data data data data ready data data
ready ready ready ready ready
Design
Activities ZigZag IQuant
Tool data data Decoder data data
ready ready ready ready
Support
output pgm-file
Design Activities
University of Tübingen
Wilhelm-Schickard-Institut
Department of Computer Engineering
University of
Tübingen Design Activities
Department of
Computer
Engineering
q Modeling
Background m Module for “zigzag”computation
& Basics
Design
Example B q Debugging
Design m Techniques for checking the functionality of the system
Activities
Tool
Support
SystemC 1.1
Joachim
Gerlach
Background
& Basics systemc.h reader.h ...... writer.h
SystemC 1.0
Design
Example A
Design
reader.cc ...... writer.cc jpeg.cc
Example B
Design library
Activities
Tool
Support
g++
SystemC 1.1
Joachim
Gerlach run
executable = simulator
Background
& Basics > ./run motorbike.pgm motorbike2.pgm
SystemC 1.0 SystemC (TM) Version 1.0 --- May 22 2000 14:21:01
ALL RIGHTS RESERVED
Design Copyright (c) 1988-2000 by Synopsys, Inc.
Example A
Comment: CREATOR: XV Version 3.10a Rev: 12/29/94
Design SystemC: simulation stopped by user.
Example B >
>
Design
Activities
Tool
Support
SystemC 1.1
Joachim
Gerlach
Design
Example B JPEG
Decoder Writer
Design
Activities
Tool
Support
SystemC 1.1
Joachim
Gerlach
Background
& Basics q Adding (C/C++) assertions/debug outputs to the source code
SystemC 1.0
Design
Example B q Using standard debugging tools (gdb, Purify,...)
Design
Activities
Tool
Support
SystemC 1.1
Joachim
Gerlach
Tool .....
Support }
}
SystemC 1.1
Joachim
Gerlach
Background
& Basics
> ./run motorbike.pgm motorbike2.pgm
SystemC 1.0 SystemC (TM) Version 1.0 --- May 22 2000 14:21:01
ALL RIGHTS RESERVED
Design Copyright (c) 1988-2000 by Synopsys, Inc.
Example A Comment: CREATOR: XV Version 3.10a Rev: 12/29/94
Design
number of zigzags: 1
Example B number of zigzags: 2
number of zigzags: 3
Design number of zigzags: 4
Activities .....
number of zigzags: 1099
Tool
number of zigzags: 1100
Support
number of zigzags: 1101
SystemC 1.1 number of zigzags: 1102
SystemC: simulation stopped by user.
>
Joachim >
Gerlach
Background
void zigzag::do_zigzag() { zigzag.cc
& Basics
.....
SystemC 1.0
static int no_of_zigzags = 0;
Design while(true) {
Example A
.....
Design // zigzag computation
Example B .....
Design no_of_zigzags++;
Activities cout << „cycle: “ << sc_time_stamp();
cout << „ - number of zigzags:“ << no_of_zigzags << endl;
Tool
Support .....
}
SystemC 1.1 }
Joachim
Gerlach
Background
& Basics
> ./run motorbike.pgm motorbike2.pgm
SystemC 1.0 SystemC (TM) Version 1.0 --- May 22 2000 14:21:01
ALL RIGHTS RESERVED
Design Copyright (c) 1988-2000 by Synopsys, Inc.
Example A Comment: CREATOR: XV Version 3.10a Rev: 12/29/94
Design
cycle: 5 - number of zigzags: 1
Example B cycle: 8 - number of zigzags: 2
cycle: 11 - number of zigzags: 3
Design cycle: 14 - number of zigzags: 4
Activities .....
cycle: 3299 - number of zigzags: 1099
Tool
cycle: 3302 - number of zigzags: 1100
Support
cycle: 3305 - number of zigzags: 1101
SystemC 1.1 cycle: 3308 - number of zigzags: 1102
SystemC: simulation stopped by user.
>
Joachim >
Gerlach
Background
& Basics
int sc_main( int argc, char *argv[] ) jpeg.cc
{
SystemC 1.0 .....
Background
& Basics
> ./run motorbike.pgm motorbike2.pgm w
SystemC 1.0 SystemC (TM) Version 1.0 --- May 22 2000 14:21:01
ALL RIGHTS RESERVED
Design Copyright (c) 1988-2000 by Synopsys, Inc.
Example A WARNING: Default time step (1 s) is used for WIF tracing.
Design
Comment: CREATOR: XV Version 3.10a Rev: 12/29/94
Example B SystemC: simulation stopped by user.
>
Design > viewer wave.awif &
Activities >
>
Tool
Support
SystemC 1.1
Joachim
Gerlach
Tool Support
University of Tübingen
Wilhelm-Schickard-Institut
Department of Computer Engineering
University of
Tübingen Synopsys SystemC Compiler
Department of
Computer
Engineering
q SystemC for system modeling
Background
& Basics SystemC
SystemC 1.0
Modeling
Design Constructs
Example A
Design
C/C++ Testbench C/C++ Software
Example B
Design
Activities
C/C++ Hardware/System System
Tool
Support
Background
& Basics
SystemC 1.0
Model using SystemC
Design
Example A
Design
Example B
SystemCTM Compiler
db form
Design db form (This flow is not supported currently)
Activities db or HDL
format
Tool Behavioral synthesis RTL synthesis
Support
SystemC 1.1
Wolfgang
Gate level netlist
Rosenstiel
SystemC 1.0
Design
Refine Structure
Example A • Partition into blocks that will be
independently synthesized/refined
Design
Example B • Refine interfaces for communication
Design
Activities
Tool
Refine Control Refine Data
Support • Specify I/O protocol • Use bit-true types
•Specify clock domains • Select appropriate
SystemC 1.1
• Specify latency, throughput bit widths
• Specify FSM & datapath for RTL
Wolfgang
Rosenstiel
System Implementation
Background yes no
& Basics Behavioral
Code? Timed DB File
Code
SystemC 1.0 Latency/Pipeline
Design SystemC Compiler Remove Constraints
Example A Design
Schedule
Design
Example B no
Initial Constraints SystemC View
Design OK? Reports
Activities yes
Check Design
Tool
Support Cycle-Accurate Cycle-Accurate DB
Time/Area Estimates HDL
SystemC 1.1
HDL Compile
Co-Simulation
Wolfgang Timed DB File Gate Level Netlist
Rosenstiel
Background
& Basics
Functional
SystemC 1.0 Design
Refinement IQ Block
Design (communication,
Example A timing, memories)
Design Architectural SystemC Compiler
Example B Design
Refinement Behavioral Flow
Design (resources, scheduling,
Activities allocation, FSM design)
Tool Controller
Support
RT Level
Design
SystemC 1.1
SystemC Compiler
RTL Flow
Wolfgang
Rosenstiel
Gate Level
Design
Design
– accommodating late spec changes
Example A
Design
m Graphical analysis of design
Example B
m High quality of results
Design
Activities
– tight integration into Synopsys synthesis flow
Tool
Support – flexibility for datapath components
SystemC 1.1
Wolfgang
Rosenstiel
Background
& Basics
SystemC 1.0
Design
Example A
Design
Example B
Design
Activities
Tool
Support
SystemC 1.1
Wolfgang
Rosenstiel
Background
& Basics
SystemC 1.0
Design
Example A
Design
Example B
Design
Activities
Tool
Support
SystemC 1.1
Wolfgang
Rosenstiel
SystemC 1.1
m Fast design exploration and HW/SW partitioning
m Allows for efficient IP reuse and delivery
Wolfgang
Rosenstiel
m Provides synthesis of communication
Design
structures, static pointer
Example A analysis, abstraction, bit-accurate (fixed and floating)
Design
hierarchy simulation libraries
Example B
m output is RT level HDL native C/C++ CSim/System C++
Design (VHDL or Verilog) simulation simulation
Activities
legacy HDL
Background HWhw
& Basics HW
Resource vendor HDL
ANSI resource
Resource
Library
C Library
library
SystemC 1.0
Design
Example A create
edit/compile
edit/compile createarchitecture
architecture
Design
Example B map
maptotoarchitecture
architecture
Design
Activities source code schedule
scheduleoperations
operations architecture
tuning optimization
Tool
Support performance analysis
logic synthesis
Wolfgang
Rosenstiel
FPGA ASIC
SystemC 1.1
Outlook
University of Tübingen
Wilhelm-Schickard-Institut
Department of Computer Engineering
University of
Tübingen SystemC 1.1 Design Flow
Department of
Computer
Engineering
Matlab C++ SDL Esterel ......
Background
& Basics functional
SystemC decomposition
1.1
SystemC 1.0 untimed
UTF functional
Design design exploration
Example A assign
performance analysis „execution time“
hw/sw partitioning
Design timed
Example B TF functional
Design hw/sw partitioning
Activities refine communication
target
cycle
Joachim RTOS/core
RTOS RTL accurate
Gerlach
software hardware
Design
q TF: Timed Functional
Example B m RPC also, but processes may be assigned a run time
Design
Activities
q BCA: Bus Cycle Accurate
Tool
Support
m Abstract ports refined to bus ports with data, adress, control
terminals and communication protocols
SystemC 1.1
Questions
& Answers
University of Tübingen
Wilhelm-Schickard-Institut
Department of Computer Engineering