MES’s College of Engineering, Pune-1

SUBJECT: ELECTRONIC DEVICES AND CIRCUITS (EDC)

NAME:
CLASS: ROLL NO.:
SEMESTER/ YEAR: EXAM NO.:
DATE OF PERFORMANCE: DATE OF SUBMISSION:
EXAMINED:

EXPERIMENT NO. :

TITLE Design a single stage FET Amplifier in CS configuration and verify DC

operating point

Objectives:

1) Calculate values biasing resistors (RD ,RS,RG) to operate FET at a certain

VDS ID
2) Build the circuit with these components
3) Measure VDSQ, IDQ and VGSQ
4) Compare measured quantities with theoretical values

Prerequisite:

1) Study of different Biasing Circuits

2) Study of analytical treatment of self-bias circuit

Apparatus:

.Sr .No. Description Specifications Qty. required.

1 FET BFW10 01
2 DC power supply 30 V,2 A 01
3. DMM 01
4. Connecting wires 10

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Theory:

Biasing in electronics could be the method of establishing predetermined voltages

or currents at various points of an electronic circuit for the purpose of establishing
proper operating conditions in components. Various FET biasing circuits are
discussed below:

Fixed Bias.

Fixed bias-FET

DC bias of a FET device needs setting of gate-source voltage VGS to give

desired drain current ID . For a JFET drain current is limited by the
saturation current IDS. Since the FET has such a high input impedance that
no gate current flows and the dc voltage of the gate set by a voltage divider
or a fixed battery voltage is not affected or loaded by the FET.

Fixed dc bias is obtained using a battery VQG. This battery ensures that the
gate is always negative with respect to source and no current flows through
resistor RG and gate terminal that is IG =0. The battery provides a voltage
VGS to bias the N-channel JFET, but no resulting current is drawn from the
battery VGG. Resistor RG is included to allow any ac signal applied through

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capacitor C to develop across RG. While any ac signal will develop across
RG, the dc voltage drop across RG is equal to IG RG i.e. 0 volt.

The gate-source voltage VGS is then

VGS = – vG – vs = – vGG – 0 = – VGG

The drain -source current ID is then fixed by the gate-source voltage as
determined by equation.

This current then causes a voltage drop across the drain resistor RD and is
given as VRD = ID RD

Output Voltage Vout=VDD- ID RD

Self-Bias.

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FET-Self Bias circuit

This is the most common method for biasing a JFET. Self-bias circuit for N-
channel JFET is shown in figure.

Since no gate current flows through the reverse-biased gate-source, the gate
current IG = 0 and, therefore,

v G = iG R G = 0

With a drain current ID the voltage at the S is Vs= ID Rs

The gate-source voltage is then

VGs = VG – Vs = 0 – ID Rs = – ID Rs

So voltage drop across resistance Rs provides the biasing voltage VGg and no
external source is required for biasing and this is the reason that it is called
self-biasing.

The operating point (that is zero signal ID and VDS) can easily be determined
from equation and equation given below :

VDS = VDD – ID (RD + RS)

Thus dc conditions of JFET amplifier are fully specified. Self biasing of a

JFET stabilizes its quiescent operating point against any change in its
parameters like transconductance. Let the given JFET be replaced by another
JFET having the double conductance then drain current will also try to be
double but since any increase in voltage drop across Rs, therefore, gate-
source voltage, VGS becomes more negative and thus increase in drain
current is reduced.

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Voltage-Divider Biasing.

FET-Voltage-divider-biasing

A slightly modified form of dc bias is provided by the circuit shown in

figure. The resistors RGl and RG2 form a potential divider across drain
supply VDD. The voltage V2 across RG2 provides the necessary bias. The
additional gate resistor RGl from gate to supply voltage facilitates in larger
adjustment of the dc bias point and permits use of larger valued RS.

The gate is reverse biased so that IG = 0 and gate voltage

VG =V2 = (VDD/R G1 + R G2 ) *RG2

And

VGS = vG – vs = VG – ID Rs

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The operating point can be determined as

ID = (V2 – VGS)/ RS

And

VDS = VDD – ID (RD + RS)

Design:

IDSS = 10mA
VP = -3V (From Data Sheet BFW10), VDD=10 V given

Given, Q condition is ID = 2mA, VDS = 5V=VDD/2

𝑉𝐺𝑆 2
𝐼𝐷 = 𝐼𝐷𝑆𝑆 (1 − )
𝑉𝑃

Substituting given values

VGS=-1.65 V

Selection of RS :

ID RS = |VGS|

Calculating RS = 825 Ω Choose RS = 1KΩ

Selection of RD:
VDD = VDS + ID (RS + RD)
10-5= 2m (1K+ RD)
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RD=1.2K Ω Choose RD = 1.5KΩ

Selection of RG:

Igs = 1000nA (From Data Sheet)

Before conduction, minority carriers have to be drained out, for this RG would be
usually very
large. Further input impedance of the amplifier would be equal to RG
itself.
Igs RG = VGS

Substituting RG = 1.6M Ω Choose RG = 1.8 M Ω

Circuit Diagram

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Procedure:

1) Design the self-bias circuit for given specifications

2) Build the circuit as shown in figure on bread board

3) Measure VGS , VDS and ID

Observation:

Parameter Theoretical Practical

Value Value
VGS -1.65 V
VDS 5V
ID 2mA

Conclusion:

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Study Questions

1) Explain need for biasing?

2) List the parameters which will very Q point?

3) Draw DC load line for FET and show operating regions?

4) Enlist different applications of FET?

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