Current Mirrors/Active Loads

SJSU EE223 by Koorosh Aflatooni 1

 Overview
¾ Current mirrors
¾ Active loads
¾ Voltage and current references

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 Current Mirrors
¾ Desired features
ƒ Generate an output current equal to input
current multiplied by desired current gain
factor
ƒ Current gain is independent of input
frequency
ƒ Output current independent of output
voltage to common node
ƒ Input voltage to be zero to let a larger
voltage appear across input current source
¾ In reality
ƒ Variation of output current with voltage
change at output => increase output
resistance in small signal
ƒ Deviation of current gain from ideal number
ƒ Vin is a finite number that need to be
minimized
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 Simple Bipolar Current Mirror

¾ Simplest form of current

mirror
¾ Operation 1
ƒ Diode connecting base to
collector in Q1, operation in
active mode
I
ƒ Vbe1=Vbe2 I C 2 = S 2 I C1
I S1
I C1 IC 2
ƒ Writing KCL for point 1 I IN − I C1 − − =0
βF βF
 
ƒ Current gain defined by  
IS2  1  
I S1 =I S 2
saturation current => emitter I OUT = I IN → I Out ~ I IN
I S1  1 + I S 2 / I S1 
areas 1+ βF 
 
ƒ Systematic error source
( βF
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 Simple Bipolar Current Mirror
(cont.)
¾ In case of finite output
resistance, change of (IS2/IS1) IC1
output voltage changes
IC2
¾ Output current

IS2  V −V 
I IN 1 + CE 2 CE1 
IS2  V −V  I  VA 
I OUT = I C1 1 + CE 2 CE1  = S 1
I S1  VA  1 + I S 2 / I S1
1+
βF

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 Simple MOSFET Current Mirror

¾ Simple current source

¾ Operation
ƒ M1, diode connected,
operates in saturation
ƒ Vgs2=Vgs1

ƒ The current gain is

defined by device sizes
ƒ Error source

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 Beta Helper

¾ Adding another transistor to

reduce the βf source of error
ƒ Common for PNP that has
lower βf 1
¾ Features
ƒ Does not change output
resistance or output voltage
from simple bipolar current
mirror
ƒ Increases the input voltage
by another base-emitter
If Q1 & Q3  2 
voltage I OUT = I IN 1 − 
identical  β ( β + 1) 
ƒ Can be used for multiple F F

output current sources

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 Cascode Current Mirror
Simple case
¾ Achieves very high output
gain
ƒ Each cascode stage
increases the output Ro = ro 2 [1 + ( g m 2 + g mb 2 )ro1 ] + ro1
resistance by (1+gmro)
¾ Minimum input voltage: VIN (min) = 2Vt + 2Vov
ƒ For each stage, we add one
(Vt+Vov) to this minimum
( Challenge for low voltage
design
¾ Minimum output voltage: VOut (min) = Vt + 2Vov
ƒ So VDS1 is a threshold
voltage more than it needs
to be

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 Cascode Current Mirror
Improved Voltage Swing
¾ In order to improve the output
swing, we need to voltage shift
the gate voltage of M2
ƒ In case we use same transistors
for all the devices => VDS1=0
ƒ So we need to find optimum
dimensions to give VDS1=Vov
¾ Output resistance is similar to
simple cascode
¾ The input voltage is worsened
¾ The systematic gain error
worsened, since M1 & M3 form a
current mirror with unequal drain-
source voltages
VDS1 − VDS 3 Vov1 − (Vov1 + Vt ) V
ε= ≈ =− t
VA VA VA
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 Cascode Current Mirror
Sooch Cascode
¾ To improve on mismatch and
some power consumption, we
could fold the level shift into one
transistor
¾ The output resistance:
Ro = ro 2 [1 + ( g m 2 + g mb 2 )ro1 ] + ro1

¾ Minimum input voltage:

VIN (min) = 2Vt + 3Vov

¾ Minimum output voltage:

VOUT (min) ≈ Vt + 2Vov

¾ M4 ensures Q1 & Q3 have

same VDS => systematic gain
error goes to zero
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 Cascode Current Mirror
Low Voltage Cascode
¾ For many low voltage
applications, it is important to
reduce the input voltage of
cascode; this can be
achieved by splitting the
input branches
¾ Two input voltages need to
satisfy:
VIN 1(min) = Vt + 2Vov
VIN 2(min) = Vt + Vov

¾ Therefore can be achieved

with lower supply voltages

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 Wilson Current Source

¾ Goal is reducing the

systematic error and achieve
large output resistance
¾ The output resistance is
given by: Ro = ro 2 [2 + g m 2 ro 3 ]

¾ Minimum input voltage:

VIN (min) = 2Vt + 2Vov
¾ Minimum output voltage:
VOUT (min) ≈ Vt + 2Vov
¾ Systematic error is zero,
since VDS1 = VDS3

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 Active Loads

¾ To achieve a high gain

ƒ Need large load resistance
(Difficult to realize resistor in an integrated circuit
(But it is much cheaper/easier to use resistors =>
Active load
¾ Configurations
ƒ Common source with complementary load
ƒ Common source with diode load
ƒ Differential pair with current mirror load

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 Common Source
with MOS Load
¾ In this case, T2 operation is
mostly defined by T3
¾ Output voltage is given by: VOUT = VDD + Vds 2

¾ In most part, the gain is not

linear. But we can bias it in a
narrow regime that gain stay
constant for short channel
devices V OUT
= − g m1 (r01 || ro 2 )
VIN

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 Common Source
with Diode Connected Load
¾ In this case, the load
resistance is
proportional to 1/gm2
¾ Large signal analysis
shows that the circuit is
operational for V =V o DD − Vt 2 −
(W / L)1
(Vi − Vt1 )
(W / L) 2
ƒ Vin greater than one
threshold voltage
ƒ Vout could only goes to
(VDD-Vt2)
vo (W / L)1
¾ Small signal gain: vi
=−
(W / L) 2

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 Differential Pair with Active Load

¾ Adding current mirror to

differential pair, to achieve
high differential gain
¾ Issue with this circuit:
sensitive common-mode
output voltage to change of
drain currents
ƒ Reducing differential gain or
range of outputs
¾ To avoid this problem, we
need to adjust the sum of M3
& M4 to be equal to sum of
M7 & M8

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 Differential Pair with Active Load
(cont.)
¾ An alternative circuit is shown
here:
ƒ Turning a differential pair into
single ended
¾ Investigating small signal model
shows the transconductance of
actively loaded Diff-Pair is twice
of resistively loaded Gm = g m ( dp ) = g m1
¾ The output resistance
Ro = ro 2 || ro 4
ƒ Large output resistance, requires
next stage also has a large input
resistance
¾ Active load also improves CMRR
by a factor of 2gm1(ro2||ro4)

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 Voltage and Current Sources

¾ Low current biasing techniques for achieving

small bias currents
ƒ Widlar current source
ƒ Peaking current source
¾ Supply insensitive biasing
ƒ Self biasing
¾ Temperature insensitive biasing
ƒ Band gap referenced circuit

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 Mos Widlar Current Sources

¾ Similar to Widlar current

mirror, but addition of
resistor makes output
current less dependent
of input current
¾ Output current depends
on input current and
resistor R2
2 2
− + + 4 R2Vov1
k ' (W / L) 2 k ' (W / L) 2
I out =
2 R2

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 MOS Peaking Current Source

¾ To achieve even lower

current values, the size
of resistors will grow
fast; alternatively we
could use this class of
circuits
¾ The output current is
given;
k ' (W / L) 2
ƒ In saturation: I out = (Vov1 − I in R )2
2
 I R
ƒ In sub-threshold: I out ≈ I in exp − in 
 nVT 

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 Supply Insensitive Biasing

¾ An important aspect in a
design is sensitivity to biases
ƒ Defined by:
VSUP ∂I OUT
SVISUP
OUT
=
I OUT ∂VSup

¾ Self biasing uses the

concept of positive feedback;
the input current is directly
related to output current
¾ Needs an startup circuit to
avoid zero current case
¾ A common approach is VT
referenced self-bias circuit
ln(n)
I out = VT
R
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 Temperature Insensitive Biasing

¾ Designing temperature
independent references
ƒ Band-gap referenced
¾ Using parasitic BJT in
CMOS process, we can
design band-gap
referenced circuit
 R   R 
Vout = VEB 2 + 1 + 2 ∆VEB + 1 + 2 VOS
 R3   R3 
I I 
∆VEB = VT ln 1 S 2 
 I 2 I S1 

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 Summary

¾ Sources and current mirrors

¾ Using active loads instead of plain resistors
¾ Temperature and bias insensitive circuits
¾ Practice questions: 4-5, 4-10, 4-12, 4-23, 4-25

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