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Issue No:01 Rev No: 01 Effective Date: 29/06/2015

Format No. VIIT-ISO-C-04 Date 26-05-2018

LESSON PLAN

DEPARTMENT OF ECE

ACADEMIC YEAR : 2018-19 SEMESTER: 1 (IV B.TECH ECE)

FACULTY NAME : Mr. B. ESHWARARAO
SUBJECT : VLSI DESIGN

S.NO. UNIT TOPIC No. of Classes

1. PART – I :Introduction to VLSI Design
2. Introduction to IC technology & Integrated Circuit ERA
3. MOS and related VLSI Technology
4. Basic MOS Transistor operation in Enhancement Mode
5. Integrated Circuit Production Process
6. N - MOS and P – MOS FET fabrication Process
7. C - MOS FET fabrication Process
8. Bi – CMOS Technology : Advantages and Disadvantages
9. Bi – CMOS Fabrication Process
10. UNIT-1 Comparison between CMOS and Bi- Polar technologies
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11. PART – II: IDS Vs VDS relationship
12. Aspects of MOS transistor Threshold Voltage
13. MOS transistor Transconductance relation with output
14. Figure-of-merit, pass transistor, NMOS inverter
Pull-up and Pull-down ratio for NMOS transistor driven by another
15.
NMOS inverter
16. Alternative forms of pull-up, CMOS inverter, Bi-CMOS inverter
17. Latch-Up in CMOS circuits and BiCMOS latch-up susceptibility
18. MOS layers
19. Stick Diagrams
20. Design Rules and Layout
21. General observations on the design rules
22. UNIT-2 2µm Double Metal, Double Poly, CMOS/BiCMOS rules 08
23. 1.2µm Double Metal, Double Poly, CMOS/BiCMOS rules
24. Layout diagrams of NAND gate and NOR gate
25. Layout diagrams of CMOS Inverter
26. Translation to MASK form
27. PART – I: Sheet Resistance, Sheet Resistance concept applied to
MOS transistors and Inverters
28. Area Capacitance of Layers
29. Standard Unit of capacitance
30. The delay unit, Inverter delays, Propagation delays
31. Wiring capacitances, Fan-In and Fan – Out characteristics
32. Choice of Layers, Transistor switches
33. Realization of gates using NMOS technology
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34. UNIT-3 Realization of gates using PMOS technology
35. Realization of gates using CMOS technology
36. PART – II: Scaling Models, Scaling factors for device parameters
37. Limits due to sub threshold currents
38. Current density limits
39. Current density limits on logic levels and supply voltage due to

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Issue No:01 Rev No: 01 Effective Date: 29/06/2015

noise

40. Architectural Issues

41. Switch Logic
42. Gate Logic : The Inverter, Two-input NMOS, CMOS & BiCMOS
NAND gate
43. Two-input NMOS, CMOS & BiCMOS NOR gate
44. Other forms of CMOS logic : dynamic-CMOS, pseudo-NMOS
45. Unit-4 Clocked CMOS, CMOS domino logic, n-p CMOS logic
46. Examples of structured design : Parity generator 12
47. Bus arbitration logic for n-lines, Multiplexers (Data Selectors)
48. Clocked Sequential circuits: Two-phase clocking, Charge Storage
49. Dynamic Register, Dynamic Shift Register
50. Other System Considerations : BUS lines, Power Dissipation for
CMOS, NMOS and BiCMOS circuits
51. General considerations of subsystem design processes
52. An Illustration of design processes : 4-bit arithmetic processor
53. VLSI Design Issues
54. VLSI Design Trends
55. Design Process
56. Design for Testability
57. UNIT-5 Technology Options
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58. Power Calculations, Package Selection
59. Clock Mechanisms, Mixed Signal design
60. ASIC design flow, FPGA design flow
61. Introduction to SoC
62. Basic FPGA architecture
63. FPGA configuration, Configuration modes
64. FPGA design process
65. FPGA design flow, FPGA families
66. FPGA design examples : STACK Implementation using VHDL
UNIT - 06 09
67. FPGA design examples : QUEUE Implementation using VHDL
68. FPGA design examples : SHIFT REGISTER Implementation using
VHDL
69. Step-by-step approach of FPGA design process on Xilinx
Environment

Text Books:
1. Essentials of VLSI Circuits and Systems By Kamran Eshraghian, Douglas and A. Pucknell and
Sholeh Eshraghian, Prentice-Hall of India Private Limited,2005 Edition.
2. VLSI Design-Black Book By Dr. K.V.K.K. Prasad, Kattula Shyamala, Kogent Learning
Solutions Inc.2012 Edition.
References:
1. VLSI Design By A.Albert Raj & T.Latha,PHI Learning Private Limited,2010.
2. VLSI Design-A.Shanthi and A.Kavita, New Age International Private Limited, 2006 First
Edition.

FACULTY HEAD OF THE DEPARTMENT

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Visakhapatnam -530049 , A.P., India

Issue No:01 Rev No: 01 Effective Date: 29/06/2015

OBJECTIVES:
The student will be introduced to
• Use mathematical methods and circuit analysis models in analysis of CMOS digital electronics
circuits, including logic components and their inter-connects.
• Learn the various fabrication steps of IC and come across basic electrical properties of
MOSFET.
• Apply CMOS technology-specific layout rules in the placement and routing of transistors and
interconnect and to verify the functionality, timing, power and parasitic effects.
• The concepts and techniques of modern integrated circuit design and testing (CMOS VLSI).
• Design static CMOS combinational and sequential logic at the transistor level, including mask
layout.
OUTCOMES:
After going through this course the student will be able to
• Apply the Concept of design rules during the layout of a circuit.
• Model and simulate digital VLSI systems using hardware design language.
• Synthesize digital VLSI systems from register-transfer or higher level descriptions
• Understand current trends in semiconductor technology, and how it impacts scaling and
performance.

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