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Digital System Design Using Verilog

Introduction to Verilog

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Contents
• Verilog HDL History

• Levels of Abstraction Level and Design Methodology

• Basic Language Concepts

• Data Types and Operators

• Examples

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Verilog HDL History
• Invented by Phil Moorby & Prabhu Goel at Gateway Design Automation Systems in
1983/84.
• Later , Cadence took full proprietary in 1990.
• In 1995, Cadence published Verilog for public domain under OVI (Open Verilog
International).
• Verilog-95 – IEEE Standard 1364-1995.
• Verilog 2001 – IEEE Standard 1364-2001.
• Verilog 2005 – IEEE Standard 1364-2005.
• SystemVerilog – Extended from Verilog and C++.
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Levels of Abstraction
Highest Level
• Verilog supports a design at 4 of Abstraction
different levels of abstraction.
Behavioral Level
Dataflow Level
Gate Level
Switch level

Lowest Level
of Abstraction
• Register Transfer Level :
• A combination of Behavioral and Data flow.

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Levels of Abstraction

• Behavioral Level :- Used to model the behavior of a design without describing its
actual hardware structure.
• Data Flow Level :- Describes the flow of data between registers and how a design
processes that data.
• Gate Level :- Describes the logic gates and the connections between logic gates in
a design.
• Switch Level :- Describes the transistors and storage nodes in a device and the
connections between them.

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Design Methodologies

• There are 2 types of design methodologies:

• Top-down design methodology, and

• Bottom-up design methodology.

• In a top-down design methodology, we define the top-level block and identify the
sub-blocks necessary to build the top-level block.

• In a bottom-up design methodology, we first identify the building blocks that are
available to us. We build bigger cells, using these building blocks.

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Design Methodologies (Cont..)

Top-Down Design Methodology

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Design Methodologies (Cont..)

Bottom-Up Design Methodology

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Structure of Module

module <mod name> (<port list>);


<declarations>; // input, output, inout Ex: Half Adder
// wire, register, etc.
module half-adder (I1 , I2 ,
<statements>; // initial, begin, end, always
O1 , O2);
// dataflow statements input I1;
endmodule input I2;
output O1, O2;
assign O1 = I1 ^ I2;
Note: case sensitive language
assign O2 = I1&I2;
endmodule

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Structure of module (Contd..)

• The <module name> is an identifier that uniquely names the module.


• The <port list> is a list of input, inout and output ports which are used to
connect to other modules.
• The <declares> section specifies data objects as registers, memories and
wires as wells as procedural constructs such as functions and tasks.
• The <statements> may be initial constructs, always constructs, continuous
assignments or instances of modules.

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Basic Languages Concepts

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Lexical Conventions
•Similar to those in C
•Verilog contains stream of tokens
•Tokens can be
–Whitespace
–Comments
–Operators
–Numbers (constants)
–Strings
–Identifiers
–Keywords –are in lowercase!!!!!

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Verilog Comments
• Verilog supports 2 type of comment syntaxes
 Single line comment start with //, and end with newline.
 Block comment, start with /*, and end with */. Block comment cannot be
nested.

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Whitespace

•Consists of Example: × Difficult to read


module addbit(a,b,ci,sum,co);
–Blank spaces, tabs and newlines input a,b,ci; output sum co;
wire a,b,ci,sum,co;endmodule

•Whitespace is ignored in Verilog EXCEPT when it separates tokens

•White space not ignored in strings


Ex: \t – tab \n - New line \b- blank space

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Strings

•Enclosed in double quotes

•Sequence of characters

•Has to be contained in one single line –without a return


–i.e –cannot be on multiple lines
–“Hello world”
–“a/b”

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Keywords

•Verilog contains keywords, which are predefined

•They are lowercase and case sensitive

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Identifier
• A letter or _ can be followed by letters, digits, $ and _

Example:
• Max 1024 characters
– myidentifier √
– m_y_identifier √
• First character cannot be digit or $ ($ is reserved for tasks) – _myidentifier$ √
– 3my_identifier X
–$my_identifier X
reg value; //reg–keyword, value –identifier
input clk; //input –keyword, clk–identifier

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Escaped identifier
•Begin with backslash (\) character module \1dff ( q, // Q output
\q~ , // Q_out output
d, // D input
•End with first white space (space, tab or newline) cl$k, // CLOCK input
\reset* // Reset input
–\wire* );
–\busa+index input d, cl$k, \reset* ;
–\-clock output q, \q~ ;

–\***error-condition*** endmodule
–\net1/\net2

NOTE: Verilog does not allow to identifier to start with a numeric character. So if you
really want to use a identifier to start with a numeric value then use a escape character
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Verilog Number Specifications

• Two representations: sized & unsized


• Format:<number of bits><base><number>

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Verilog Numbers Specifications (Contd..)
• Negative numbers: put minus sign before size.
• Format: -<size><base><number>
 <size> field is always +ve.
 Represented by 2‟s complement internally.
• Often _ (Underscore) is used in between digits of the number for readability.

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Verilog Numbers Specifications (Contd..)
• Verilog numbers may have x or z as part of numbers.
• x ? unknown value, z ? high impedance value
• A question mark „?‟ can also be used as an alternative to „z‟.

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Verilog Numbers Specifications (Contd..)

module signed_number;
reg [31:0] a;
initial
begin
a = 14'h1234; Output:
$display ("Current Value of a = %h", a); Current Value of a = 00001234
a = -14'h1234; Current Value of a = ffffedcc
$display ("Current Value of a = %h", a); Current Value of a = deadbeef
Current Value of a = 21524111
a = 32'hDEAD_BEEF;
$display ("Current Value of a = %h", a);
a = -32'hDEAD_BEEF;
$display ("Current Value of a = %h", a);
#10 $finish;
end
endmodule

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Operators
•Are of three types
–Unary -precede the operand
a = ~b; //~ is a unary operator. b is the operand

–Binary –operators appear between two operands


a = b && c; //&& is a binary operator. b and c are operands

–Ternary –have two separate operators that separate three operands


a = cond_expr? true_expr: false_expr//?: -ternary operator.

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Arithmetic Operators
module arithmetic_operators();
Initial
• Binary: +, -, *, /, % (the modulus operator) begin
$display (" 5 + 10 = %d", 5 + 10);
$display (" 5 - 10 = %d", 5 - 10);
• Unary: +, - (This is used to specify the sign) $display (" 10 - 5 = %d", 10 - 5);
$display (" 10 * 5 = %d", 10 * 5);
$display (" 10 / 5 = %d", 10 / 5);
$display (" 10 / -5 = %d", 10 / -5);
• Integer division truncates any fractional part $display (" 10 %3 = %d","%", 10 % 3);
$display (" +5 = %d", +5);
$display (" -5 = %d", -5); 5 + 10 = 15
#10 $finish; 5 - 10 = -5
end 10 - 5 = 5
endmodule 10 * 5 = 50
10 / 5 = 2
10 / -5 = -2
10 % 3 = 1
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-5 = -5
Logical Operators

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Logical Operation Example

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module logical_operators();
initial
Begin
// Logical AND
$display ("1'b1 && 1'b1 = %b", (1'b1 && 1'b1)); 1'b1 && 1'b1 = 1
$display ("1'b1 && 1'b0 = %b", (1'b1 && 1'b0)); 1'b1 && 1'b0 = 0
$display ("1'b1 && 1'bx = %b", (1'b1 && 1'bx)); 1'b1 && 1'bx = x
// Logical OR 1'b1 || 1'b0 = 1
$display ("1'b1 || 1'b0 = %b", (1'b1 || 1'b0)); 1'b0 || 1'b0 = 0
$display ("1'b0 || 1'b0 = %b", (1'b0 || 1'b0)); 1'b0 || 1'bx = x
$display ("1'b0 || 1'bx = %b", (1'b0 || 1'bx)); ! 1'b1 = 0
// Logical Negation ! 1'b0 = 1
$display ("! 1'b1 = %b", (! 1'b1));
$display ("! 1'b0 = %b", (! 1'b0));
#10 $finish;
End
endmodule

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Bitwise Operators

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module bitwise_operators();
Initial
begin
// Bit Wise Negation ~4'b0001 = 1110
$display (" ~4'b0001 = %b", (~4'b0001)); ~4'bx001 = x110
$display (" ~4'bx001 = %b", (~4'bx001)); ~4'bz001 = x110
$display (" ~4'bz001 = %b", (~4'bz001)); 4'b0001 & 4'b1001 = 0001
// Bit Wise AND 4'b1001 & 4'bx001 = x001
$display (" 4'b0001 & 4'b1001 = %b", (4'b0001 & 4'b1001)); 4'b1001 & 4'bz001 = x001
$display (" 4'b1001 & 4'bx001 = %b", (4'b1001 & 4'bx001)); 4'b0001 | 4'b1001 = 1001
$display (" 4'b1001 & 4'bz001 = %b", (4'b1001 & 4'bz001)); 4'b0001 | 4'bx001 = x001
// Bit Wise OR 4'b0001 | 4'bz001 = x001
$display (" 4'b0001 | 4'b1001 = %b", (4'b0001 | 4'b1001)); 4'b0001 ^ 4'b1001 = 1000
$display (" 4'b0001 | 4'bx001 = %b", (4'b0001 | 4'bx001)); 4'b0001 ^ 4'bx001 = x000
$display (" 4'b0001 | 4'bz001 = %b", (4'b0001 | 4'bz001)); 4'b0001 ^ 4'bz001 = x000
// Bit Wise XOR 4'b0001 ~^ 4'b1001 = 0111
$display (" 4'b0001 ^ 4'b1001 = %b", (4'b0001 ^ 4'b1001)); 4'b0001 ~^ 4'bx001 = x111
$display (" 4'b0001 ^ 4'bx001 = %b", (4'b0001 ^ 4'bx001)); 4'b0001 ~^ 4'bz001 = x111
$display (" 4'b0001 ^ 4'bz001 = %b", (4'b0001 ^ 4'bz001));
// Bit Wise XNOR
$display (" 4'b0001 ~^ 4'b1001 = %b", (4'b0001 ~^ 4'b1001));
$display (" 4'b0001 ~^ 4'bx001 = %b", (4'b0001 ~^ 4'bx001));
$display (" 4'b0001 ~^ 4'bz001 = %b", (4'b0001 ~^ 4'bz001));
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#10 $finish; end ;endmodule
Reduction Operators

• Key symbols: &, ~&, |, ~|, ^, ~^, ^~.


• The reduction operators are and, nand, or, nor, xor, xnor and an alternative
xnor. They take one operand and perform a bit-by next- bit operation, starting
with the two leftmost bits, giving a 1-bit result.

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Reduction Operation

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module reduction_operators();
initial
begin & 4'b1001 = 0
// Bit Wise AND reduction & 4'bx111 = x
$display (" & 4'b1001 = %b", (& 4'b1001)); $display (" & 4'bx111 = %b", (& 4'bx111)); & 4'bz111 = x
$display (" & 4'bz111 = %b", (& 4'bz111)); ~& 4'b1001 = 1
// Bit Wise NAND reduction ~& 4'bx001 = 1
$display (" ~& 4'b1001 = %b", (~& 4'b1001)); $display (" ~& 4'bx001 = %b", (~& 4'bx001));
~& 4'bz001 = 1
$display (" ~& 4'bz001 = %b", (~& 4'bz001));
// Bit Wise OR reduction | 4'b1001 = 1
$display (" | 4'b1001 = %b", (| 4'b1001)); $display (" | 4'bx000 = %b", (| 4'bx000)); | 4'bx000 = x
$display (" | 4'bz000 = %b", (| 4'bz000)); | 4'bz000 = x
// Bit Wise OR reduction ~| 4'b1001 = 0
$display (" ~| 4'b1001 = %b", (~| 4'b1001)); $display (" ~| 4'bx001 = %b", (~| 4'bx001)); ~| 4'bx001 = 0
$display (" ~| 4'bz001 = %b", (~| 4'bz001)); ~| 4'bz001 = 0
// Bit Wise XOR reduction ^ 4'b1001 = 0
$display (" ^ 4'b1001 = %b", (^ 4'b1001)); $display (" ^ 4'bx001 = %b", (^ 4'bx001)); ^ 4'bx001 = x
$display (" ^ 4'bz001 = %b", (^ 4'bz001));
^ 4'bz001 = x
// Bit Wise XNOR
$display (" ~^ 4'b1001 = %b", (~^ 4'b1001)); $display (" ~^ 4'bx001 = %b", (~^ 4'bx001)); ~^ 4'b1001 = 1
$display (" ~^ 4'bz001 = %b", (~^ 4'bz001)); ~^ 4'bx001 = x
#10 $finish; ~^ 4'bz001 = x
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Endmodule;
Shift Operators
• Key symbols: >>, <<.
• The shift operators are shift left and shift right. The shift operator takes a vector
and a number indicating the shift.
• The empty bits caused by shifting are filled with zeros.

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module shift_operators();
Initial
begin
// Left Shift
4'b1001 << 1 = 0010
$display (" 4'b1001 << 1 = %b", (4'b1001 << 1));
4'b10x1 << 1 = 0x10
$display (" 4'b10x1 << 1 = %b", (4'b10x1 << 1));
4'b10z1 << 1 = 0z10
$display (" 4'b10z1 << 1 = %b", (4'b10z1 << 1));
4'b1001 >> 1 = 0100
// Right Shift
4'b10x1 >> 1 = 010x
$display (" 4'b1001 >> 1 = %b", (4'b1001 >> 1));
4'b10z1 >> 1 = 010z
$display (" 4'b10x1 >> 1 = %b", (4'b10x1 >> 1));
$display (" 4'b10z1 >> 1 = %b", (4'b10z1 >> 1));
#10 $finish;
End endmodule

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Relational & Equality Operators

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module equality_operators();
initial
begin
// Case Equality
$display (" 4'bx001 === 4'bx001 = %b", (4'bx001 === 4'bx001));
4'bx001 === 4'bx001 = 1
$display (" 4'bx0x1 === 4'bx001 = %b", (4'bx0x1 === 4'bx001));
4'bx0x1 === 4'bx001 = 0
$display (" 4'bz0x1 === 4'bz0x1 = %b", (4'bz0x1 === 4'bz0x1));
4'bz0x1 === 4'bz0x1 = 1
$display (" 4'bz0x1 === 4'bz001 = %b", (4'bz0x1 === 4'bz001));
4'bz0x1 === 4'bz001 = 0
// Case Inequality
4'bx0x1 !== 4'bx001 = 1
$display (" 4'bx0x1 !== 4'bx001 = %b", (4'bx0x1 !== 4'bx001));
4'bz0x1 !== 4'bz001 = 1
$display (" 4'bz0x1 !== 4'bz001 = %b", (4'bz0x1 !== 4'bz001));
5 == 10 = 0
// Logical Equality
5 == 5 = 1
$display (" 5 == 10 = %b", (5 == 10));
5 != 5 = 0
$display (" 5 == 5 = %b", (5 == 5));
5 != 6 = 1
// Logical Inequality
$display (" 5 != 5 = %b", (5 != 5));
$display (" 5 != 6 = %b", (5 != 6));
#10 $finish;
end
endmodule

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EXAMPLES

reg [3:0] a, b; reg [3:0] a, b; reg [7:0] a, b;


a = 4'b1100; a = 4'b1100; a = 8'b1010xzxz;
b = 4'b0110; b = 4'b101x; b = 8'b10010011;
a < b // false - 0 a == 4'b1100 // true - 1 a & b = 8'b100000xx;
a > 8 // true - 1 a != 4'b1100 // false - 0 a | b = 8'b1011xx11;
a <= b // false - 0 a == 4'b1z10 // false - 0 a ^ b = 8'b0011xxxx;
a >= 10 // true - 1 a != 4'b100x // true - 1 a ~^ b = 8'b1100xxxx;
a < 4'b1zzz // unknown - x b == 4'b101x // unknown - x ~ a = 8'b0101xxxx;
a < 4'b1x01 // unknown - x b != 4'b101x // unknown - x
b === 4'b101x // true - 1
b !== 4'b101x // false - 0

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Conditional Operator

• cond_expr ? true_expr : false_expr


• A ternary operator
• Acts like a 2-to-1 mux.

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Concatenation Operator

• {op1, op2, ..}concatenates op1, op2, .. to single number.


• Operands must be sized !!

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Replication Operator

• <no> { <variable/sized_number> }
• <no> is an integer.

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Operator Precedence

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Data types
1. Value Sets:
0 (Logic zero or false condition)
1 (Logic 1 or true condition)
X (unknown logic value)
Z (High impedance state)

2. Wire :
A wire represents a physical wire in a circuit and used to connect gates or module. The value of a wire
can be read but cannot assigned to any function or any block.

Ex: wire c;
wand d;
assign d=a;
assign d=b;
wire [9:0] A;

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Nets
• Wire: simple interconnecting wire module support (a,b,c,f);
input a,b,c;
• wor or trior : wired output OR together output f;
supply0 gnd;
• wand or triand : wired output AND together supply1 vdd;
nand g1( t1,vdd,a,b);
• tri0: pulls down when tri-stated xor g2 (t2,c,gnd);
and g3 (f,t2,t1);
• tri1: pulls up when tri-stated endmodule

• supply0: constant logic 0


• supply1: constant logic 1
• trireg: stores the value when tri-sated

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Registers
• These correspond to variables in the C language.

• Register data types always retain their value until another value is placed on them.

• DO NOT confuse with hardware registers built with flip-flops.


reg a;
reg [7:0] tom;
• A reg type variable is the one that can hold a value. reg [5:0] b,c;

• Unlike nets, registers do not need any drivers.

• In synthesis, the compiler will generate latches or flip-flops for them. However, if
it can be sure their output does not need to be stored it will synthesize them into
wires.
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Rules for reg and wire
• The common rule in Verilog:
“A variable on the Left Hand Side (LHS) of a procedural block
assignment is always declared as a register data type.”All other
variables are of net type.”
• Verilog register data types: reg / time / integer / real / realtime / event (reg is the
most common of all.)

• So, reg is assigned within always or initial blocks.

• A variable is declared of type wire if it appears on the left side of an continuous


assignment statement.

• Structural code continuous assignment statements start with the keyword assign.

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Integers
• A general purpose register data type with default value having all x bits.
Integer j;
reg [3:0] bcq;
• Declared with keyword integer.
j=6; // j has 32’00…….00110
bcq= j;// has 4’b0110
• Usually preferred for arithmetic manipulations over reg. bcq= 4’b0101;
j= bcq; // has 32’b0000…..0101

• Default width: host machine word size (minimum 32 bits). j= -6;has 32’b 111111110101;
bcq= j;

• Differs from reg type as it stores signed quantities as opposed to reg storing
unsigned quantities.

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Real Numbers
• Real number constants declared with a keyword real.

• Real constants have default value of 0.

• Real numbers CANNOT have a range declaration.

• Two notations: Decimal& Scientific notation.

• When a real value is assigned to an integer, the real number is rounded off to the
nearest integer.

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Time & Realtime Data types
• time – A special register data type used mainly to store simulation time.

• time is an unsigned 64-bit by default. Usually, it is used to store the simulation


time.

• realtime is similar to time except that it has initial value of 0.

• Depending upon the timescale specified, realtime provides the simulation time
with the fractional part with given precision.

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Vectors
• Vectors have multiple bits and are often used to represent buses.

• The left most number is an MSB (Most Significant Bit).

• There are 2 representations for vectors:


A little-endian notation: [high# : low#]
A big-endian notation: [low# : high#]

wire [3:0] busA; // little-endian notation


reg [0:15] busC; // big-endian notation
reg [1:4] busB;

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• Vector assignment (by position!!)

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• Variable Vector Part Select
[<starting_bit>+ : <width>]
[<starting_bit>- : <width>]

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Arrays
• Declaration: <type> <vector_size> <ary_name> <ary_size>;

• § <ary_size> is declared as a range.

• Verilog supports multi-dimensional arrays.

• Elements are accessed by: <ary_name> [<index>].

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Arrays (Contd..)

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Parameter
• Parameters allows constant like word length to defined symbolically in one place.

parameter add=2‟b00 , sub= 3‟b111;


parameter n= 4 ;
parameter [3:0] st4= 4‟b1010;


reg [n-1: 0] harry ;

always @ (x)

y= {{ (add- sub) {x}};




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Note.1
• Verilog provides a set of logic gates.
• They respond to inputs (0,1,x or z) in a logical way
Ex: AND
0 & 0 = 0; 0 & 1 = 0; 1 & 1=1; 1 & x = x ; 0 & x= 0; 1 & z= x; z & x = x;

Ex: XOR
0 & 0 = 0; 0 & 1 = 0; 1 & 1=1; 1 & x = x ; 0 & x= x; 1 & z= x; 0 & z = x;
• Primitive logic gates are : and, or, nor, xor, xnor,not,buf
• primitive Tri-state gates: bufif1, bufif0, notif1, notif0

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Note.2:
module reg_map (a, b, c, f1, f2); module reg_map (a, b, c, f1, f2);
input a,b,c; input a,b,c;
output f1,f2; output f1,f2;
wire a,b,c; wire a,b,c;
reg f1,f2; reg f1,f2;

always @ (a or b or c) always @ (a or b or c)
begin begin
f1= ~ ( a & b); The synthesis system f2= f1 ^ c;
f2= f1 ^ c; Will generate a wire f1= ~ ( a & b);
end for f1 end
endmodule endmodule

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Behavioral Level Modelling Examples

module d_ff(q,clk,n_rst,din); module counter_behav ( count,reset,clk); module bcd_count(clk, rst, count);


output q; input clk;
input clk,din,n_rst; input wire reset, clk; input rst;
output [3:0] count;
reg q;
output reg [3:0] count; reg[3:0] count;
always @(posedge clk or negedge always @ (posedge clk)
n_rst) always @(posedge clk) begin
begin if (reset) if(rst)
if(!n_rst) count <= 4'b0000; count = 4'b0000;
q <= 1‟b0; else else if (count ==4’b1001)
else count <= count + 4'b0001; count=4’b0000;
q <= din; else
end count = count+1;
endmodule end
endmodule
endmodule

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Examples for Data Level and Structural Level

module halfadder (a,b,carry,sum); module fadder(A,B,Cin,Carry,Sum); module parladder(x,y,Cin,Sum,Carry);


input a; input Ain; input [3:0] x;
input b; input Bin; input [3:0] y;
output carry; input Cin; input Cin;
output sum; wire c1,c2,c3;
assign sum = a ^ b; wire w1,w2,w3; output Carry;
assign carry = a &b; output Carry; output [3:0] Sum;
endmodule output Sum; fadder L1(x[0],y[0], Cin, Sum[0],c1);
halfadder L1(A, B, w1, w2); fadder L2(x[1], y[1], c1, Sum[1],c2);
halfadder L2 (Cin, w2, w3, Sum); fadder L3(x[2],y[2], c2, Sum[2],c3);
assign Carry = w1|w3; fadder L4(x[3],y[3], c3, Sum[3],Carry);
endmodule endmodule

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THANK
YOU

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