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Introduction to Verilog
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Contents
• Verilog HDL History
• Examples
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Verilog HDL History
• Invented by Phil Moorby & Prabhu Goel at Gateway Design Automation Systems in
1983/84.
• Later , Cadence took full proprietary in 1990.
• In 1995, Cadence published Verilog for public domain under OVI (Open Verilog
International).
• Verilog-95 – IEEE Standard 1364-1995.
• Verilog 2001 – IEEE Standard 1364-2001.
• Verilog 2005 – IEEE Standard 1364-2005.
• SystemVerilog – Extended from Verilog and C++.
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Levels of Abstraction
Highest Level
• Verilog supports a design at 4 of Abstraction
different levels of abstraction.
Behavioral Level
Dataflow Level
Gate Level
Switch level
Lowest Level
of Abstraction
• Register Transfer Level :
• A combination of Behavioral and Data flow.
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Levels of Abstraction
• Behavioral Level :- Used to model the behavior of a design without describing its
actual hardware structure.
• Data Flow Level :- Describes the flow of data between registers and how a design
processes that data.
• Gate Level :- Describes the logic gates and the connections between logic gates in
a design.
• Switch Level :- Describes the transistors and storage nodes in a device and the
connections between them.
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Design Methodologies
• In a top-down design methodology, we define the top-level block and identify the
sub-blocks necessary to build the top-level block.
• In a bottom-up design methodology, we first identify the building blocks that are
available to us. We build bigger cells, using these building blocks.
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Design Methodologies (Cont..)
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Design Methodologies (Cont..)
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Structure of Module
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Structure of module (Contd..)
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Basic Languages Concepts
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Lexical Conventions
•Similar to those in C
•Verilog contains stream of tokens
•Tokens can be
–Whitespace
–Comments
–Operators
–Numbers (constants)
–Strings
–Identifiers
–Keywords –are in lowercase!!!!!
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Verilog Comments
• Verilog supports 2 type of comment syntaxes
Single line comment start with //, and end with newline.
Block comment, start with /*, and end with */. Block comment cannot be
nested.
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Whitespace
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Strings
•Sequence of characters
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Keywords
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Identifier
• A letter or _ can be followed by letters, digits, $ and _
Example:
• Max 1024 characters
– myidentifier √
– m_y_identifier √
• First character cannot be digit or $ ($ is reserved for tasks) – _myidentifier$ √
– 3my_identifier X
–$my_identifier X
reg value; //reg–keyword, value –identifier
input clk; //input –keyword, clk–identifier
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Escaped identifier
•Begin with backslash (\) character module \1dff ( q, // Q output
\q~ , // Q_out output
d, // D input
•End with first white space (space, tab or newline) cl$k, // CLOCK input
\reset* // Reset input
–\wire* );
–\busa+index input d, cl$k, \reset* ;
–\-clock output q, \q~ ;
–\***error-condition*** endmodule
–\net1/\net2
NOTE: Verilog does not allow to identifier to start with a numeric character. So if you
really want to use a identifier to start with a numeric value then use a escape character
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Verilog Number Specifications
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Verilog Numbers Specifications (Contd..)
• Negative numbers: put minus sign before size.
• Format: -<size><base><number>
<size> field is always +ve.
Represented by 2‟s complement internally.
• Often _ (Underscore) is used in between digits of the number for readability.
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Verilog Numbers Specifications (Contd..)
• Verilog numbers may have x or z as part of numbers.
• x ? unknown value, z ? high impedance value
• A question mark „?‟ can also be used as an alternative to „z‟.
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Verilog Numbers Specifications (Contd..)
module signed_number;
reg [31:0] a;
initial
begin
a = 14'h1234; Output:
$display ("Current Value of a = %h", a); Current Value of a = 00001234
a = -14'h1234; Current Value of a = ffffedcc
$display ("Current Value of a = %h", a); Current Value of a = deadbeef
Current Value of a = 21524111
a = 32'hDEAD_BEEF;
$display ("Current Value of a = %h", a);
a = -32'hDEAD_BEEF;
$display ("Current Value of a = %h", a);
#10 $finish;
end
endmodule
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Operators
•Are of three types
–Unary -precede the operand
a = ~b; //~ is a unary operator. b is the operand
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Arithmetic Operators
module arithmetic_operators();
Initial
• Binary: +, -, *, /, % (the modulus operator) begin
$display (" 5 + 10 = %d", 5 + 10);
$display (" 5 - 10 = %d", 5 - 10);
• Unary: +, - (This is used to specify the sign) $display (" 10 - 5 = %d", 10 - 5);
$display (" 10 * 5 = %d", 10 * 5);
$display (" 10 / 5 = %d", 10 / 5);
$display (" 10 / -5 = %d", 10 / -5);
• Integer division truncates any fractional part $display (" 10 %3 = %d","%", 10 % 3);
$display (" +5 = %d", +5);
$display (" -5 = %d", -5); 5 + 10 = 15
#10 $finish; 5 - 10 = -5
end 10 - 5 = 5
endmodule 10 * 5 = 50
10 / 5 = 2
10 / -5 = -2
10 % 3 = 1
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-5 = -5
Logical Operators
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Logical Operation Example
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module logical_operators();
initial
Begin
// Logical AND
$display ("1'b1 && 1'b1 = %b", (1'b1 && 1'b1)); 1'b1 && 1'b1 = 1
$display ("1'b1 && 1'b0 = %b", (1'b1 && 1'b0)); 1'b1 && 1'b0 = 0
$display ("1'b1 && 1'bx = %b", (1'b1 && 1'bx)); 1'b1 && 1'bx = x
// Logical OR 1'b1 || 1'b0 = 1
$display ("1'b1 || 1'b0 = %b", (1'b1 || 1'b0)); 1'b0 || 1'b0 = 0
$display ("1'b0 || 1'b0 = %b", (1'b0 || 1'b0)); 1'b0 || 1'bx = x
$display ("1'b0 || 1'bx = %b", (1'b0 || 1'bx)); ! 1'b1 = 0
// Logical Negation ! 1'b0 = 1
$display ("! 1'b1 = %b", (! 1'b1));
$display ("! 1'b0 = %b", (! 1'b0));
#10 $finish;
End
endmodule
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Bitwise Operators
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module bitwise_operators();
Initial
begin
// Bit Wise Negation ~4'b0001 = 1110
$display (" ~4'b0001 = %b", (~4'b0001)); ~4'bx001 = x110
$display (" ~4'bx001 = %b", (~4'bx001)); ~4'bz001 = x110
$display (" ~4'bz001 = %b", (~4'bz001)); 4'b0001 & 4'b1001 = 0001
// Bit Wise AND 4'b1001 & 4'bx001 = x001
$display (" 4'b0001 & 4'b1001 = %b", (4'b0001 & 4'b1001)); 4'b1001 & 4'bz001 = x001
$display (" 4'b1001 & 4'bx001 = %b", (4'b1001 & 4'bx001)); 4'b0001 | 4'b1001 = 1001
$display (" 4'b1001 & 4'bz001 = %b", (4'b1001 & 4'bz001)); 4'b0001 | 4'bx001 = x001
// Bit Wise OR 4'b0001 | 4'bz001 = x001
$display (" 4'b0001 | 4'b1001 = %b", (4'b0001 | 4'b1001)); 4'b0001 ^ 4'b1001 = 1000
$display (" 4'b0001 | 4'bx001 = %b", (4'b0001 | 4'bx001)); 4'b0001 ^ 4'bx001 = x000
$display (" 4'b0001 | 4'bz001 = %b", (4'b0001 | 4'bz001)); 4'b0001 ^ 4'bz001 = x000
// Bit Wise XOR 4'b0001 ~^ 4'b1001 = 0111
$display (" 4'b0001 ^ 4'b1001 = %b", (4'b0001 ^ 4'b1001)); 4'b0001 ~^ 4'bx001 = x111
$display (" 4'b0001 ^ 4'bx001 = %b", (4'b0001 ^ 4'bx001)); 4'b0001 ~^ 4'bz001 = x111
$display (" 4'b0001 ^ 4'bz001 = %b", (4'b0001 ^ 4'bz001));
// Bit Wise XNOR
$display (" 4'b0001 ~^ 4'b1001 = %b", (4'b0001 ~^ 4'b1001));
$display (" 4'b0001 ~^ 4'bx001 = %b", (4'b0001 ~^ 4'bx001));
$display (" 4'b0001 ~^ 4'bz001 = %b", (4'b0001 ~^ 4'bz001));
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#10 $finish; end ;endmodule
Reduction Operators
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Reduction Operation
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module reduction_operators();
initial
begin & 4'b1001 = 0
// Bit Wise AND reduction & 4'bx111 = x
$display (" & 4'b1001 = %b", (& 4'b1001)); $display (" & 4'bx111 = %b", (& 4'bx111)); & 4'bz111 = x
$display (" & 4'bz111 = %b", (& 4'bz111)); ~& 4'b1001 = 1
// Bit Wise NAND reduction ~& 4'bx001 = 1
$display (" ~& 4'b1001 = %b", (~& 4'b1001)); $display (" ~& 4'bx001 = %b", (~& 4'bx001));
~& 4'bz001 = 1
$display (" ~& 4'bz001 = %b", (~& 4'bz001));
// Bit Wise OR reduction | 4'b1001 = 1
$display (" | 4'b1001 = %b", (| 4'b1001)); $display (" | 4'bx000 = %b", (| 4'bx000)); | 4'bx000 = x
$display (" | 4'bz000 = %b", (| 4'bz000)); | 4'bz000 = x
// Bit Wise OR reduction ~| 4'b1001 = 0
$display (" ~| 4'b1001 = %b", (~| 4'b1001)); $display (" ~| 4'bx001 = %b", (~| 4'bx001)); ~| 4'bx001 = 0
$display (" ~| 4'bz001 = %b", (~| 4'bz001)); ~| 4'bz001 = 0
// Bit Wise XOR reduction ^ 4'b1001 = 0
$display (" ^ 4'b1001 = %b", (^ 4'b1001)); $display (" ^ 4'bx001 = %b", (^ 4'bx001)); ^ 4'bx001 = x
$display (" ^ 4'bz001 = %b", (^ 4'bz001));
^ 4'bz001 = x
// Bit Wise XNOR
$display (" ~^ 4'b1001 = %b", (~^ 4'b1001)); $display (" ~^ 4'bx001 = %b", (~^ 4'bx001)); ~^ 4'b1001 = 1
$display (" ~^ 4'bz001 = %b", (~^ 4'bz001)); ~^ 4'bx001 = x
#10 $finish; ~^ 4'bz001 = x
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Endmodule;
Shift Operators
• Key symbols: >>, <<.
• The shift operators are shift left and shift right. The shift operator takes a vector
and a number indicating the shift.
• The empty bits caused by shifting are filled with zeros.
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module shift_operators();
Initial
begin
// Left Shift
4'b1001 << 1 = 0010
$display (" 4'b1001 << 1 = %b", (4'b1001 << 1));
4'b10x1 << 1 = 0x10
$display (" 4'b10x1 << 1 = %b", (4'b10x1 << 1));
4'b10z1 << 1 = 0z10
$display (" 4'b10z1 << 1 = %b", (4'b10z1 << 1));
4'b1001 >> 1 = 0100
// Right Shift
4'b10x1 >> 1 = 010x
$display (" 4'b1001 >> 1 = %b", (4'b1001 >> 1));
4'b10z1 >> 1 = 010z
$display (" 4'b10x1 >> 1 = %b", (4'b10x1 >> 1));
$display (" 4'b10z1 >> 1 = %b", (4'b10z1 >> 1));
#10 $finish;
End endmodule
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Relational & Equality Operators
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module equality_operators();
initial
begin
// Case Equality
$display (" 4'bx001 === 4'bx001 = %b", (4'bx001 === 4'bx001));
4'bx001 === 4'bx001 = 1
$display (" 4'bx0x1 === 4'bx001 = %b", (4'bx0x1 === 4'bx001));
4'bx0x1 === 4'bx001 = 0
$display (" 4'bz0x1 === 4'bz0x1 = %b", (4'bz0x1 === 4'bz0x1));
4'bz0x1 === 4'bz0x1 = 1
$display (" 4'bz0x1 === 4'bz001 = %b", (4'bz0x1 === 4'bz001));
4'bz0x1 === 4'bz001 = 0
// Case Inequality
4'bx0x1 !== 4'bx001 = 1
$display (" 4'bx0x1 !== 4'bx001 = %b", (4'bx0x1 !== 4'bx001));
4'bz0x1 !== 4'bz001 = 1
$display (" 4'bz0x1 !== 4'bz001 = %b", (4'bz0x1 !== 4'bz001));
5 == 10 = 0
// Logical Equality
5 == 5 = 1
$display (" 5 == 10 = %b", (5 == 10));
5 != 5 = 0
$display (" 5 == 5 = %b", (5 == 5));
5 != 6 = 1
// Logical Inequality
$display (" 5 != 5 = %b", (5 != 5));
$display (" 5 != 6 = %b", (5 != 6));
#10 $finish;
end
endmodule
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EXAMPLES
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Conditional Operator
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Concatenation Operator
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Replication Operator
• <no> { <variable/sized_number> }
• <no> is an integer.
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Operator Precedence
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Data types
1. Value Sets:
0 (Logic zero or false condition)
1 (Logic 1 or true condition)
X (unknown logic value)
Z (High impedance state)
2. Wire :
A wire represents a physical wire in a circuit and used to connect gates or module. The value of a wire
can be read but cannot assigned to any function or any block.
Ex: wire c;
wand d;
assign d=a;
assign d=b;
wire [9:0] A;
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Nets
• Wire: simple interconnecting wire module support (a,b,c,f);
input a,b,c;
• wor or trior : wired output OR together output f;
supply0 gnd;
• wand or triand : wired output AND together supply1 vdd;
nand g1( t1,vdd,a,b);
• tri0: pulls down when tri-stated xor g2 (t2,c,gnd);
and g3 (f,t2,t1);
• tri1: pulls up when tri-stated endmodule
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Registers
• These correspond to variables in the C language.
• Register data types always retain their value until another value is placed on them.
• In synthesis, the compiler will generate latches or flip-flops for them. However, if
it can be sure their output does not need to be stored it will synthesize them into
wires.
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Rules for reg and wire
• The common rule in Verilog:
“A variable on the Left Hand Side (LHS) of a procedural block
assignment is always declared as a register data type.”All other
variables are of net type.”
• Verilog register data types: reg / time / integer / real / realtime / event (reg is the
most common of all.)
• Structural code continuous assignment statements start with the keyword assign.
• Default width: host machine word size (minimum 32 bits). j= -6;has 32’b 111111110101;
bcq= j;
• Differs from reg type as it stores signed quantities as opposed to reg storing
unsigned quantities.
• When a real value is assigned to an integer, the real number is rounded off to the
nearest integer.
• Depending upon the timescale specified, realtime provides the simulation time
with the fractional part with given precision.
always @ (x)
Ex: XOR
0 & 0 = 0; 0 & 1 = 0; 1 & 1=1; 1 & x = x ; 0 & x= x; 1 & z= x; 0 & z = x;
• Primitive logic gates are : and, or, nor, xor, xnor,not,buf
• primitive Tri-state gates: bufif1, bufif0, notif1, notif0
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Note.2:
module reg_map (a, b, c, f1, f2); module reg_map (a, b, c, f1, f2);
input a,b,c; input a,b,c;
output f1,f2; output f1,f2;
wire a,b,c; wire a,b,c;
reg f1,f2; reg f1,f2;
always @ (a or b or c) always @ (a or b or c)
begin begin
f1= ~ ( a & b); The synthesis system f2= f1 ^ c;
f2= f1 ^ c; Will generate a wire f1= ~ ( a & b);
end for f1 end
endmodule endmodule
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Behavioral Level Modelling Examples
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Examples for Data Level and Structural Level
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THANK
YOU
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