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  • Semicustom Back End Flow Lab Workbook PDF

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    Lakshmi Prasad
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    This document describes a semi-custom backend design flow using Mentor Graphics tools including floorplanning, placement, routing, and physical verification. The key steps are: 1) floorplanning using Pyxis, 2) placement using auto placement, 3) routing using Aroute, and 4) physical verification including DRC, LVS, and parasitic extraction (PEX) using Calibre tools.

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    This document describes a semi-custom backend design flow using Mentor Graphics tools including floorplanning, placement, routing, and physical verification. The key steps are: 1) floorplanning using Pyxis, 2) placement using auto placement, 3) routing using Aroute, and 4) physical verification including DRC, LVS, and parasitic extraction (PEX) using Calibre tools.

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    32 visualizzazioni15 pagine

    Semicustom Back End Flow Lab Workbook PDF

    Caricato da

    Lakshmi Prasad
    This document describes a semi-custom backend design flow using Mentor Graphics tools including floorplanning, placement, routing, and physical verification. The key steps are: 1) floorplanning using Pyxis, 2) placement using auto placement, 3) routing using Aroute, and 4) physical verification including DRC, LVS, and parasitic extraction (PEX) using Calibre tools.

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    di 15

    LAB WORKBOOK

    SEMI-CUSTOM BACK-END FLOW USING MENTOR GRAPHICS TOOLS.

    In this lab we will be doing a semi-custom back-end flow using Mentor Graphics Tools.

    SemiCustom (Backend) design flow:

    1. Floorplanning
    2. Placement
    3. Routing
    4. Physical Verification

    1. Floorplanning:
    Step1: Invoke Pyxis layout Design tool
    csh
    source<space><give your cshrc file path >
    ic&

    Step2: Click New-Verilog Button

    SMDP Training Material

    Contact: smdpfae@coreel.com
    Layout cell - cell name < give top level cell name >
    Verilog netlist file – Verilog scan inserted gate level netlist
    Module name - top module name (counter)
    Power – VDD < VSS terminal name >
    Ground – GND < GND terminal name >
    Process - $ADK/technology/ic/process/tsmc018
    Rule - $ADK/technology/ic/process/tsmc018.rules
    Library - $ADK/technology/ic/process/tsmc018
    Then Press OK

    Step3: go to Plan & Place > Floorplaner > Autpfp > OK

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    2. Placement:

    Step4: Auto Placement > StdCell

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    Step5: Ports

    Press OK

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    3. Routing:

    Step6: route > Aroute Setup > option > Advance >

    Check following option


    Check same net spacing
    Fill net gaps
    Route power first
    Allow all directions for stubs
    Center wires on pines
    Pack wires

    Press OK

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    Step7: Aroute commands > run

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    Step8: Right mouse click on layout Edit > add text on ports > OK

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    Step9: File > exports > GDSII

    File > exports > GDSII

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    Now GDSII file Generated

    4. Physical Verification:

    Step10: For DRC check following option

    Tools > Calibre DRC < select option >


    Rules > $ADK/technology/ic/process/tsmc018.rules
    Inputs > /home/HUSSAIN/SMDP/counter_scan.gds < give GDSII File Path >

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    Press Run DRC button

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    Step11: for LVS check first create Verilog gate level net-list to spice net-list file
    Open new terminal. Go to working directory.
    cd SMDP < Working directory Name >
    Source cshrc File
    csh
    source /home/software/cshrc/hep.cshrc
    v2lvs -v counter_scan.v -o counter.spi –l /home/software/FOUNDARY/adk3_1/technology/adk.v –s
    /home/software/FOUNDARY/adk3_0/technology/adk.spi -sk -s0 GND -s1 VDD
    generate spice net-list file <counter.spi>

    Now open Calibre LVS tool


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    Tools > Calibre LVS < select option >
    Rules > $ADK/technology/ic/process/tsmc018.rules

    Inputs > Layout > /home/HUSSAIN/SMDP/counter_scan.gds < give GDSII File Path >

    Inputs > SPICE > /home/HUSSAIN/SMDP/counter_scan.spi

    Press Run LVS

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    Contact: smdpfae@coreel.com
    Step12: For PEX extraction following option

    Tools > Calibre PEX < select option >


    Rules > $ADK/technology/ic/process/tsmc018.rules

    Inputs > Layout > /home/HUSSAIN/SMDP/counter_scan.gds < give GDSII File Path >

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    Inputs > SPICE > /home/HUSSAIN/SMDP/counter_scan.spi

    Outputs >
    Format: - DSPF
    File :- <file name>.dspf

    Run PEX

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    dspf file generated for doing post layout simulation

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