PROJECT 1

POWER ELECTRONICS I

Prepared by:
Saratul Akma Bt Mohamed (11410)
Muhamad Aizat Bin Aluwi (11393)
Introduction of Power MOSFET
Power MOSFETs are used in many electronics applications such as high speed switching
devices and to perform other functions involving high power. They dissipate large values of
power over a very small area resulting in very high heat flux and the thermal design of such
devices becomes very critical. Thermal design for these FETs is very important because the
failure rate of these devices is a function of junction temperature. Most specification require that
junction temperature be kept below 110o C or even lower to meet the system reliability
requirements. The failure rate above this limit increases very rapidly. Conventional heat sink
design for such devices will not be adequate to maintain the junction temperature below that
required by reliability considerations. Immersion cooling with its inherent high heat transfer rates
is required in such cases.

The operating principle of the MOSFET transistor was first described in Lilienfield’s
historical patent issued in 1926. It took another 34 years before Kahng and Atalla successfully
built a working MOSFET in 1960.

For the past 40 years, the semiconductor industry and academia have relentlessly pushed
transistor scaling. Along with scaling, the MOSFET transistor evolved from the P-channel
MOSFET in the 1960’s to the N-channel MOSFET in the 1970’s. A good understanding of gate
oxide quality, such as interface traps, fixed and mobile charges, and a good control of gate oxide
quality in a manufacturing environment enabled industry to make the transition from PMOS
technology to a higher-performing NMOS technology in 1970’s.

Basic Structure of Power Mosfet

Several structures had been explored at the beginning of the 1980s, when the first Power
MOSFETs were introduced. However, most of them have been abandoned (at least until
recently) in favor of the Vertical Diffused MOS (VDMOS) structure (also called Double-
Diffused MOS or simply DMOS).
The cross section of a VDMOS (see figure 1) shows the "verticality" of the device: It can be seen
that the source electrode is placed over the drain, resulting in a current mainly vertical when the
transistor is in the on-state. The "diffusion" in VDMOS refers to the manufacturing process: the
P wells (see figure 1) are obtained by a diffusion process (actually a double diffusion process to
get the P and N+ regions, hence the name double diffused).

Power MOSFETs have a different structure than the lateral MOSFET: as with all power devices,
their structure is vertical and not planar. In a planar structure, the current and breakdown voltage
ratings are both functions of the channel dimensions (respectively width and length of the
channel), resulting in inefficient use of the "silicon estate". With a vertical structure, the voltage
rating of the transistor is a function of the doping and thickness of the N epitaxial layer (see cross
section), while the current rating is a function of the channel width. This makes possible for the
transistor to sustain both high blocking voltage and high current within a compact piece of
silicon.

It is worth noting that power MOSFETs with lateral structure exists. They are mainly used in
high-end audio amplifiers. Their advantage is a better behavior in the saturated region
(corresponding to the linear region of a bipolar transistor) than the vertical MOSFETs. Vertical
MOSFETs are designed for switching applications, so they are only used in On or Off states.

Fig. 1: Cross section of a VDMOS, showing an elementary cell.

I-V Characteristic of Power Mosfet

Figure 2: N-channel enhancement-mode Power MOSFET I-V Characteristics

It has regions labeled as Ohmic, Current-Saturated and Cut-off. In the Cut-off region, the
gate-source voltage (Vgs) is less than the gate-threshold voltage (Vgs(th)) and the device is
an open-circuit or Off. In the Ohmic region, the device acts as a resistor with almost a constant
on-resistance, (RDS(on)) defined by Vds /Ids. In the current-saturated region, the drain current is
a function of the gate-source voltage and defined by, where K is a parameter depending on the
temperature and device geometry and gfs is the current gain or transconductance of the device.
When the drain voltage (Vds) is increased, the positive drain potential opposes the gate voltage
bias and reduces the surface potential in the channel. The channel inversion layer charge
decreases with increasing Vds and ultimately, it becomes zero when the drain voltage equals to
( ) gs gs(th) V −V . This point is called the channel pinch-off point where the drain current
becomes saturated.
SWITCHING CHARACTERISTICS OF POWER MOSFET

Since power MOSFETs are majority carrier devices, switching performance is their main
characteristic of interest. The switching speed of a power MOSFET is much faster than that of a
bipolar transistor and its high-speed, high-frequency operation is outstanding. This characteristic
is utilized in switching regulators (f = 1 kHz to 1 MHz) and in motor controls. As mentioned
before, two important features of power MOSFETs are that they have no storage time
dependence, and that their capacitance doesn’t depend on temperature; therefore, their switching
characteristics are not hardly influenced by temperature fluctuations.

Figure 4.5 shows a typical switching time measurement circuit and input/output waveforms.
Introduction of IGBT (Insulated Bipolar Junction Transistor )

IGBT or Insulated Gate Bipolar Transistor is a device that combines the Metal Oxide
Semiconductor Field Effect Transistor (MOSFET) gate driving characteristics with the high
current and low saturation voltage of bipolar transistor. It acts as a high frequency, high current
switch which is used in AC/DC Inverter, motor control and in switching mode power supplies
applications. It has lower VCE (Saturation) voltage which allows it to operate with a higher
current density than with bipolar transistor. It can be modeled as a PNP transistor driven by a
Power MOSFET. The normal gate driving voltage used is in the region of 15V where saturation
voltage is obtained so that conduction losses are kept to a minimum. The safe operating area is
critical information that shows the maximum operating current and voltage of the device. It
shows the forward bias SOA(safe operating area) and reverse bias SOA when the gate emitter
junction is forward bias and reversed bias respectively. A typical forward bias SOA is shown in
the figure below. It is almost square for short switching duration. Longer switching duration will
cause the graph to move to a smaller area.

Basic Structure of IGBT

All IGBTs on the market have either a punch-through structure (PT) or non-punch-through
structure (NPT).Fig.5 shows the vertical cross section through one of the elements of the PT and
NPT IGBT structures. In practice an IGBT chip consists of many such elements connected in
parallel. The NPT structure is the most basic one for an IGBT. It consists of a four layer
sandwich of n+pn-p+, very similar to a thyristor structure except the gate consists of a
polysilicon layer which is separated by an oxide layer grown on the top surface of the silicon
wafer. The polysilicon layer is arranged such that it overlaps the n+ and n- regions. On the top,
the emitter contact is made by aluminium which overlaps the n+ and p regions. On the other side
of the wafer the collector contact is made by aluminium contact on the p+ region can be grown
and so this type of structure is limited to voltages less than 1200V.The NPT structure is
fabricated by starting with a uniformly doped (n-) silicon wafer. The emitter and MOSFET are
formed by diffusion on the top side of the wafer and the p+ collector is formed by an
implantation method on the other side of the wafer. With the NPT structure it is currently
possible to achieve forward blocking voltages as high as 4.5kV. The static and dynamic
characteristics of the PT and the NPT IGBTs are different and these will be discussed later. The
reverse breakdown voltage between emitter and collector is characterized by the reverse
breakdown of the un- terminated collector to base junction (n+ in PT structure and n- in NPT
structure). This has a typical value of 10V. In many applications an anti parallel diode is used
with an IGBT switch and so it has to withstand only the forward voltage drop of this diode in the
reverse breakdown mode. However the transient forward voltage drop of a diode can be
significantly higher than the steady state value and it is likely that this junction is broken down
transiently by the diode’s transient forward voltage. This has no serious detrimental effect as
long as the duration is short and the magnitude of the resultant transient power is within the
device avalanche power rating.
 Fig 5: The structure of IGBTs

I-V Characteristic of IGBT

Fi
gure I-V characteristics of an IGBT

A distinguishing feature of the characteristics is the 0.7V offset from the origin. The
entire family of curves is translated from the origin by this voltage magnitude. It may be recalled
that with a P+ collector, an extra P-N junction has been incorporated in the IGBT structure. This
P-N junction makes its function fundamentally different from the power MOSFET.

SWITCHING CHARACTERISTICS OF IGBT

The biggest limitation to the turn-off speed of an IGBT is the lifetime of the minority
carriers in the N- epi, i.e., the base of the PNP. Since this base is not accessible, external drive
circuitry cannot be used to improve the switching time. It should be remembered, though, that
since the PNP is in a pseudo-Darlington connection, it has no storage time and its turn-off time is
much faster than the same PNP in heavy saturation. Even so, it may still be inadequate for many
high frequency applications.

The charges stored in the base cause the characteristic “tail” in the current waveform of
an IGBT at turn-off (Figure 3). As the MOSFET channel stops conducting, electron current
ceases and the IGBT current drops rapidly to the level of the hole recombination current at the
inception of the tail.

This tail increases turn-off losses and requires an increase in the deadtime between the
conduction of two devices in a half-bridge. Traditional lifetime killing techniques and/or an N+
buffer layer to collect the minority charges at turn-off are commonly used to speed-up
recombination time. Insofar as they reduce the gain of the PNP, these techniques increase the
voltage drop. Pushed to the extreme, minority lifetime killing causes a quasi-saturation condition
at turn-on, as shown in Figure 4, where the turn-on losses have become larger than the turn-off
losses.
 Thus, the gain of the PNP is constrained by conduction and turn-on losses on one hand,
and by latching considerations on the other, as explained in the next session. Like all minority
carrier devices, the switching performance of an IGBT degrades with temperature.

IGBTs operated in zero current switching may exhibit quasi-saturation losses at turn-on
that are somewhat higher than in switchmode circuits. The low di/dt that is characteristic of this
mode of operation emphasizes the "switchback" phenomenon described in the previous section.
Similarly, with zero-voltage turn-off, the IGBT may experience a short burst of current if the
complementary device is turned on soon after the current has ceased in the one that was
conducting.

This is due to the fact that the turn-on of the complementary device causes the supply
voltage to appear across the first IGBT, thereby depleting its base region and causing a final
sweep-out of minority carriers that were still left there. There is, however, a component of
current that is due to the charging of the device capacitances and is totally unrelated to minority
carriers.