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David Villamarin Rivera
College San Francisco de Quito

Abstract—At present the world is surrounded by nanometric make them advantageous, even on occasions with respect to
devices where it is manufactured with CMOS technology of 90 the bipolar transistor:
nm standards, for high frequency applications, in this work we 1.- The manufacturing process is simple (fewer steps)
have considered designing a NAND gate with mosfets that has
a reliable model and that dissipates powers extremely low for 2.- Reduced size, which lead to high integration densities.
microwave applications, since every day it is more essential to 3.- The use of resistances can be avoided, because their
design integrated circuits to contribute to research, where the behavior can be model using circuit techniques.
present work will modify the lengths and widths of the mosfet 4.- Reduced energy consumption (lower power consumption).
with an alpha relationship that allows us to have better time 5.- Both analog and digital and / or mixed functions can be
implemented within the same chip.

I. I NTRODUCTION The MOS (Metal Oxide Semiconductor) transistor is the

most promising active component for VLSI silicon circuits
The metal-oxide-semiconductor field effect transistor or today
MOSFET is a transistor used to amplify or switch electronic
signals. It is the most used transistor in the nanoelectronic II. DESING OF THE NAND GATE
industry, either in analog or digital circuits. Currently, com- With the help of the spice software that is for the design of
mercial microprocessors are based on MOSFET transistors. integrated circuits we realize a NAND gate that its logic is to
The MOSFET is a device of four terminals called source (S, deliver a low output when all its inputs are high and a high
Source), drain (D, Drain), gate (G, Gate) and substrate (B, output while there is at least one low to any of them then in
Bulk). However, the substrate is usually connected internally Figure 1 shows the table of the nand gate.
to the source terminal and for this reason you can find three-
terminal MOSFET devices
From the physical point of view, the principle of operation
focuses on the action of a electric field over electric charges,
causing its displacement and, therefore, the current electrical
Hence its generic name of: FET - Field Effect Transistor.
Various structures of FET transistors have been developed,
depending on the technology and / or needs The most impor-
tant are those implemented with technologies on Silicon (Si)
Fig. 1. Gate Nand
as the JFET, or Junction FET, and the MOSFET, or Metal-
Oxide-Semiconductor FET. [1] The NAND gate is constituted of several mosfet, for our
In technologies of Arsenide of Gallium (AsG) have been case a static and dynamic gate will be analyzed. Figure 2
implemented transistors MESFET or Metal-Semiconductor shows the simulation of a static NAND gate.
FET. The current development of silicon technologies is very
high. Not so in the case of AsGa, which are still in the
research and experimentation phase with a degree of relative
reliability, and sometimes not commercially available. Most
current ICs are performed on Si technologies [1]. Among
them, the MOSFET transistor is widely the most used over
the others (JFET) for possessing certain characteristics that
The characteristics that it presents are:
• number of transistors is N + 2 (versus 2N for static
complementary CMOS)
• should be smaller in area than static complementary
• Full swing outputs (VOL = GND and VOH = VDD)
• Non ratioed - sizing of the devices is not important for
proper functioning (only for performance)
• Faster switching speeds and reduced load capacitance due
to lower number of transistors per gate (Cint) so a reduced
logical effort
• Reduced load capacitance due to smaller fan-out (Cext)
no Isc, so all the current provided by PDN goes into
discharging CL
• Ignoring the influence of precharge time on the switching
speed of the gate, tpLH = 0 but the presence of the
evaluation transistor slows down the tpHL
Fig. 2. Gate Nand Static
Now we will proceed to create the layout for the NAND
gate (static and dynamic). Where the 90nm library will be used
The characteristics that it presents are: to start with the design without forgetting that the minimum
• Logic levels not dependent upon the relative device sizes; gate width will be 0.21um this entire gate design process is
ratio less integrated in the Spice software.
• Always a path to Vdd or Gnd in steady state; low output If you can see in figure 2, it corresponds to the static gate
impedance that is constituted by two gates pmos and two nmos where it
• Extremely high input resistance; nearly zero steadystate had an alpha ratio of 2 for that reason the w of the transistors
input current pmos is equal to 0.8um and the nmos of 0.5um so that the
• No direct path steady state between power and ground; rise and fall times are as similar as possible. From these data,
no static power dissipation the layout could be designed as shown in figure 4.
• Propagation delay function of load capacitance and resis-
tance of transistors
• Full rail-to-rail swuing; high noise margins VOH and VOL
are at and GND,respectively
In the figure 3 you can see the simulation of a dynamic
NAND gate.

Fig. 4. Layout of the Gate Nand Static

If you can see in figure 3, it corresponds to the dynamic

gate that is constituted by a gates pmos and two nmos where
it had an alpha relation of 3 for that reason the w of the
transistors pmos is equal to 0.21um and the nmos of 0.63
um , an important detail is that in the dynamic gates does
not depend on the width of the transistor its timing operation.
From these data, the layout could be designed as shown in
Fig. 3. Gate Nand Dynamic figure 5.
To obtain the power that is occupying the circuit, we will
deal with equation 1. Where it is necessary to integrate the
current with respect to time in a period of time.
Z Tf
P =f∗ V dd.I(t) dt (1)

With equation 1 we can obtain the simulated power for our

static and dynamic NAND gate to check with the theory we
will occupy equation 2 to obtain the theoretical power for a
capacitance of 100 fF.

P = Cl.V dd.f [W ] (2)

In my case I am going to work in a period of 20nS with a

load capacitor of 100 fF and Vdd of 1.2 Volts with this data
we will proceed to calculate the theoretical power.

Fig. 5. Layout of the Gate Nand Dynamic

P = 20∗10−9 = 7.2uW


In this section we will perform an analysis between the In figure 8 the following data can be analyzed:
static and dynamic curves obtained to see which has better
• It is a simulation without taking into account the external
performance in delay times and power that dissipates when
effects (Parasitic capacitances)
making the calls, it is important to know that the spice
• The precharge time is 214 ps and the value is 210 ps.
software allows to have a simulation with the parasitic
• The power that dissipates this NAND gate is 7.53 uW.
capacitances It is obtained by having it manufactured on a
silicon wafer.

In Figure 6 and 7 you can see both static and dynamic

encapsulations to proceed with the simulation must be taken
into account that two simulations are produced one that is with
the schematic and the other with parasitic capacitances.


In figure 9 the following data can be analyzed:

• It is a simulation that takes into account the parasite
capacitances that occur in the silicon wafer
• The precharge time is 230 ps and the value is 207 ps
Fig. 6. static gate encapsulation • The power that dissipates this NAND gate is 8.13 uW.


Fig. 7. encapsulation dynamic gate
In the following figure 10 you can see how the curves
depend on the clock plus the current curve was obtained as
seen in the figure in the simulation VDD is sent to the logical
input A and B was put a pulse source to observe the logic
table of the gate.

Fig. 10. DYNAMIC NAND GATE AND CURRENT It was concluded that the dynamic design is better than the
static one for the following reasons.
In figure 11 the following data can be analyzed:
• In this simulation parasitic capacitances are not taken into In the design of the layout the structure is more compact than
account but it depends on a clock for its operation known the static one in other words its size is smaller. The power
as dynamic gate. that dissipates the dynamic circuit is more efficient than the
• The precharge time is 237 ps and the value is 781 ps dynamic with an error of 4.16 percent that is very acceptable
• The power that dissipates this dynamic NAND gate is for the theory power. In the case of the delay the static in
6.1143 uW. this case turned out to be more efficient than the dynamic
one as can be seen in the section of the comparison tables.
[1] J. P. Colinge, ”Multi-gate SOl MOSFETs,” Microelectronic Engineering,
vol. 84,no. 9-10,p p. 2071-2076,2007.
[2] Marc0 Lanuzza, ”Slides provided in classes”


In figure 12 the following data can be analyzed:

• It is a simulation that takes into account the parasite
capacitances that occur in the silicon wafer
• The precharge time is 232 ps and the value is 772 ps
• The power that dissipates this dynamic NAND gate is