Jiaxin Li - Curriculum Vitae

Phone: +1 (515) 708-6533

Email: jiaxin@iastate.edu

Education
Iowa State University Ames, IA

B.S. Electrical Engineering (Expected Graduation May 2019) August 2015-present

Fields of Interest
VLSI system design

Wireless communications & signal processing

Semiconductor devices

Embedded system

Research & Project Experience

 Design fabrications of bicycle speedometer
10/2018-12/2018
Instructor: Gary Tuttle

- Researched the function of Hall-effect sensor for calculating moving speed and distance.

- Designed code for interfacing Arduino with LCD screen.

- Designed the PCB using ModelSim and Ultiboard.

 Design and test small equipment checkout system for ETG (Electronics Technology Group)
09/2018-12/2018
Instructor: Lee Harker

- Researched intended users, applications, assumptions and limitations.

- Formulated the software system plan for students and administrators.

- Tested the locker control system and door detecting system for hardware part.

- Combined the hardware and software control by using OWFS (One-Wire File system) on raspberry-pi.

 Design and fabrication of control circuit in a laser pointer-based mobile vehicle

 09/2018-11/2018
Instructor: Gary Tuttle

- Designed an appropriate control circuit for the control performance mobile vehicle.

- Designed and manufactured a timing controller for mobile vehicle operation using the 555 Timer IC.

 Fabrication of integrated CMOS circuit on a 3-inch silicon wafer

08/2018 – 11/2018
Instructor: Meng Lu

- Simplified the fabrication procedure of silicon dioxide file using wet oxidation.

- Optimized the alignment process in the photolithography process of the silicon wafer.

- Conducted the p-well process of NMOS using boron deposition.

 Design basic logic gates, buffers, D-Flip-Flops, multiplexers and half/full adder circuits with Virtuoso
02/2018 - 04/2018
Instructor: Randall Geiger

- Designed schematic and layout circuit using Cadence.

- Developed Verilog code and layout for logical function using ModelSim and RTL compiler.

- Utilized Layout vs. Schematic (LVS) to verify the schematic with the layout circiut.

 Design of an 8-bit Booth’s multiplier using the multiple-bit binary number

11/ 2017 - 12/2017
Instructor: Alexander Stoytchev

- Utilized low-bit multiplier’s principle to generate the logical code prototype by Quartus Prime.

- Analyzed various AND, XOR logic gates and Multiplexer.

- Operated the switcher on the DE2-115 Board and displayed the result on the 7-segment display.

 Fabrication of Infrared Ray Communication Processing System in the electric appliance

03/2017 – 04/2017
Instructor: Liang Dong

- Designed Optical Signaling Device using Personal Computer Simulation Program with Integrated
Circuit Emphasis (PSPICE).

- Simplified the design code of Optical Signaling Device circuit.

- Evaluated the functional ability of Infrared Ray Communication Processing System.

Work Experience

 Student Internship CoAdna Photonics, Sunnyvale, CA, USA

06/2018 – 08/2018
- Repaired basic PCB for power supply.

- Calibrated temperature of vacuum thermal chamber using the thermometer, thermistor, and thermal
compound.

- Analyzed PID controller in “H1” heater development for balancing the heating rate on each step of
heating process.

- Designed data acquisition system using LabVIEW.

- Designed and verified Bill of Materials (BOM).

Skills
 Software: MATLAB, Arduino environment, PSS/E, PSPICE, Eclipse, Quartus Prime, Virtuoso,
ModelSim and Ultiboard.

 Programming language: JAVA, Verilog and C.

 Familiar with the principle and process of CMOS fabrication.

Community Outreach
 Department chair in ISU Chinese Students & Scholar Association (CSSA) 08/2016 – 02/2018

- Organized “Offline Three People Basketball” game for international students.

- Designed the new Logo of ISU CSSA card.

- Chaired ISU CSSA dinner party to celebrate Chinese New Year.

- Held several seminars of safety awareness and identification of potential risk in the college
environment.

Presentations

1. Jiaxin Li, Yimin Wang, Caining Wang, Bei Zhao and Fengnan Yang, Small equipment check out
system technical challenges, EE 491 senior design project, Iowa State University, Ames, IA, USA,
October 2018
2. Jiaxin Li, Ryan Hansen, Jaime Zentina, Chufu Zhou and Yimin Wang, Multi-gate field-effect transistor
Fin-FET and 3D transistor, EE 432 final project, Iowa State University, Ames, IA, USA, November
2018

3. Jiaxin Li, Yimin Wang, Caining Wang, Bei Zhao and Fengnan Yang, Small equipment check out
system panel presentation, EE 491 senior design project, Iowa State University, Ames, IA, USA,
December 2018