Module no.

Course contents (Total Detail of course

lectures) (number of lectures)
History and
technology trends,
Overview of CMOS
Clean room
process, Clean room
procedures, IC
fabrication flow.
Crystal structure,
Czochralski, Float-
Crystal growth, Wafer Zone growth
manufacturing methods, Wafer
specification, Crystal
characterization
Wet and Dry
oxidation, Growth
Silicon Oxidation kinetics and Models,
Quality,
Characterization.
Light sources, Optical
lithography,
Photoresist types,
Mask making,
Lithography
Advanced
Lithography
techniques and their
comparison.
Dry and wet etch
techniques. Si
Etching etching , Plasma
etching, Reactive Ion
Etching.
Diffusion equations
and profiles,
Diffusion Modeling
concentration
dependent diffusion.
Chemical Vapor
Deposition, Molecular
Beam epitaxy,
Thin film deposition Epitaxial defects, low
and high dielectric
deposition, Poly
deposition.
Ion channeling,
Ion Implantation Implant damage,
Annealing.
Physical and chemical
vapor deposition, Al
Metallization
and Cu metallization,
Silicide formation.
Process Integration, Introduction to
Yield Bipolar, BICMOS,

Introduction
Review of IC technology, device modeling and
layout
Basic analog subcircuits
Noise analysis and modeling
Basic operational amplifier (opamp) design
Comparators
Integrated filters
Introduction to data converters
Introduction
CMOS Devices
Integrated Circuit Interconnect
CMOS Inverter Logic Function
CMOS Combinational Logic Design
o Mux/DeMux), Static and Dynamic Design, DC
and MEMS
technology,
Planarization, Multi-
chip modules and
packaging.
CAD tools and methodology, Notations, symbols,
and terminology, Example of analog signal
processing and analog ICs.
Modeling of BJT and MOS devices, BJT and MOS
fabrication technology, Basic IC layout and passive
components
MOS switch and resistor, Current sources/sinks and
current mirrors, Design of basic amplifiers, Current
and voltage references
Time and frequency-domain analysis, Noise models
for IC devices, Noise analysis examples
Non-ideal characteristics of opamps, Design of two-
stage opamps, Stability and frequency compensation
Characterization of a comparator, Bipolar
comparators, CMOS Comparators
Opamp-RC filters, MOSFET-C filters, Gm-C filters,
Switched-capacitor filters
Characterization and definition of data converters,
Nyquist-Rate Digital-to-Analog Converters,
Oversampled Converters
Historical Review, Issues Integrated Circuit
Design, Quality Metrics
MOS Capacitor, MOS Diode, NFET and PFET
Large Signal I-V Relations, DC and Transient
Modeling and Simulation, Device Scaling
o RLC Characteristics of Interconnect
o Modeling (lumped RC, distributed RC,
transmission line), DC and Transient Modeling
and Simulation Scaling
DC Transfer Functions, Static and Dynamic
Characteristics, DC and Transient Modeling and
Simulation, Logic Design Prototypes (CMOS,
pseudo-NMOS, Diode), Design Optimization
(noise margin, area, power, delay)
Single Output /Multiple Input (NAND, NOR,
XOR), Multiple Output/Multiple Input (Adder,
Transfer Functions, Static and Dynamic
Characteristics, DC and Transient Modeling and

CMOS Sequential Logic Design
o Monostable and Astable Circuits, Static and
o
o Introduction
o Verilog/VHDL:
o Logic synthesis
o Physical design automation
Simulation, Design Optimization (logic style,
noise margin, area, power, delay), Next
Generation and Scaling
o CMOS Latches and Flips-Flops,
Dynamic Design, DC Transfer Functions, Static
and Dynamic Characteristics, DC and Transient
Modeling and Simulation, Design Optimization
(logic style, clocking, setup time, hold time,
area, power, delay), Next Generation and
Scaling
o
o VLSI design flow, challenges.
o introduction and use in synthesis,
modeling combinational and sequential logic,
writing test benches.
o Two-level and multilevel gate-
level optimization .
o Binary decision diagrams. Basic
concepts of high-level synthesis, partitioning,
scheduling, allocation and binding. Technology
mapping.
o VLSI design styles, full-custom,
standard-cell, gate-array and FPGA, Physical
design automation algorithms, floor-planning,
placement, routing, compaction, design rule
check, power and delay
o estimation, clock and power
routing, Special considerations for analog and
mixed-signal designs.
 Digital domain

Succesive Digital Time- Time-domain

approximation Deltasigma calibration interleaving processing

SAR Offset Without

compensation Switched current
Oversampling calibration (cao et reference source (yang
(Flynn et al) al, 2009) SAR & sharpeshkar, 2005,
2006).

With background
calibration (alpman
et al., 2009)
Recursive
Additional successive
comparators with approximation
background algorithm in the
calibration (kijima, time domain
ito et al. 2009) Input reference (jimenez-irastorza
generation from et al. 2011)
comparator offset
(sundström &
alvandpour, 2009)

N-bit flash quantizer

replaced by asynchronous
comparator ((Colodro &
Torralba, 2008). )
 Analog reduction
Switched op-amp Op-amp sharing Op-amp less
4th order band-pass
Op-amp for two
ΣΔ modulator using adjacent stages in
two switched op-
successive alternative
amps (kuo & liu, phases(hashemi &
2004).
shoaei, 2007; sasidhar,
2009)
Biasing
Inverter based ΔΣ
modulators
Assisted op-amp and
helper techniques
CBSC (comparator
based switched
capacitors) Hybrid ΣΔ modulator
technique(fiorenza et
fabricated in 65nm
al., 2006) CMOS technology
(van veldhoven et al.,
2008)
Pipelined ADC based
on zero-crossing
detector (shin et al.
2008; brooks & lee,
2009)
(Chae & han, 2009)
the inverter behavior
used as an extremely
ADC array using simple amplifier
charge redistribution
architecture
(draxelmayr, 2004)
Comparator based
flash ADC structure
(van der plas, 2006)
FA FA

FA

FA FA

FA

FA FA

FA

FA FA
 T15 T14 T13 b3
T12
T11
T10
c1
T9
d0
T8 b2
T7 Bit3 (MSB)
T6
c0
T5
T4
T3
T2 b1
T1 c1c0 Bit2
T0

b3
b0 b2 b1 b0
Bit1

T15T13T11 T9 T7 T5 T3 T1

Bit0 (LSB)

Bit3 = d0
Bit2 = c0 + c1
Bit1 = b0 + b1 + b2 + b3
Bit0 = T1 + T3 + T5 + T7 + T9 + T11 + T13 + T15

V+
Vin
00000000111111111

(2n-1) to n n -bit
encoder

V-

Resistor string Thermometer

Comparator array Thermometer code to binary encoder
 IC
Fundamental theorey , Process indepth analysis
Fabrication

Analog IC Digital IC
VLSI CAD
Custom IC design skills, Digital IC design skills, Programming skills
design Design

Projects
Comprehensive design practice
 1.0

0.9

0.8
 Vm

0.7

0.6

0.5

0.4
0.01 0.1 1 10 100

Wp/Wn aspect ratio