Vlsi Formatted Lab Manual

VLSI DESIGN FLOW
BASIC DESIGN FLOW

Expt.No:
STUDY OF SIMULATION TOOLS
Date :
AIM:
To study the Simulation tools.
THEORY:
Creating a Test Bench for Simulation:

In this section, you will create a test bench waveform containing input stimulus you can use to simulate
the counter module. This test bench waveform is a graphical view of a test bench. It is used with a simulator
to verify that the counter design meets both behavioral and timing design requirements. You will use the
Waveform Editor to create a test bench waveform (TBW) file.
1. Select the counter HDL file in the Sources in Project window.

2. Create a new source by selecting Project _ New Source.
3. In the New Source window, select Test Bench Waveform as the source type, and type test bench in
the File Name field.
4. Click Next.
5. The Source File dialog box shows that you are associating the test bench with the source file: counter.
Click Next.
6. Click Finish. You need to set initial values for your test bench waveform in the Initialize Timing dialog
box before the test bench waveform editing window opens.
7. Fill in the fields in the Initialize Timing dialog box using the information below:
 Clock Time High: 20 ns.
 Clock Time Low: 20 ns.
 Input Setup Time: 10 ns.
 Output Valid Delay: 10 ns.
 Initial Offset: 0 ns
 Global Signals: GSR (FPGA)

Leave the remaining fields with their default values.
Fig 1: Waveform Editor - Initialize Timing Dialog Box
8. Click OK to open the waveform editor. The blue shaded areas are associated with each input signal and
correspond to the Input Setup Time in the Initialize Timing dialog box. In this tutorial, the input transitions
occur at the edge of the blue cells located under each rising edge of the CLOCK input.
Fig 2:Waveform Editor - Expected Results
9. In this design, the only stimulus that you will provide is on the DIRECTION port. Make the transitions
as shown below for the DIRECTION port:
 Click on the blue cell at approximately the 300 ns clock transition. The signal switches to high at
this point.
 Click on the blue cell at approximately the 900 ns clock transition. The signal switches back to
low.
 Click on the blue cell at approximately the 1400 ns clock transition. The signal switches to high
again.
10. Select File _ Save to save the waveform. In the Sources in Project window, the TBW file is
automatically added to your project. 11. Close the Waveform Editor window. Adding Expected Results
to the Test Bench Waveform:
In this step you will create a self-checking test bench with expected outputs that correspond to your
inputs. The input setup and output delay numbers that were entered into the Initialize Timing dialog when
you started the waveform editor are evaluated against actual results when the design is simulated. This can
be useful in the Simulate Post- Place & Route HDL Model process, to verify that the design behaves as
expected in the target device both in terms of functionality and timing. To create a self-checking test bench,
you can edit output transitions manually, or you can run the Generate Expected Results process:
1. Select the testbench.tbwfile in the Sources in Project window.
2. Double-click the Generate Expected Simulation Results process. This process converts the TBW into
HDL and then simulates it in a background process.
3. The Expected Results dialog box will open. Select Yes to post the results in the waveform editor.
4. Click the “+” to expand the COUNT_OUT bus and view the transitions that correspond to the Output
Valid Delay time (yellow cells) in the Initialize Timing dialog box.
5. Select File _ Save to save the waveform.
6. Close the Waveform Editor. Now that you have a test bench, you are ready to simulate your design.
Simulating the Behavioral Model (ISE Simulator):
If you are using ISE Base or Foundation, you can simulate your design with the ISE Simulator. If you wish
to simulate your design with a ModelSim simulator, skip this section and proceed to the “Simulating the
Behavioral Model (ModelSim)” section.
Fig 3:Simulator Processes for Test Bench
Fig 4:Behavioral Simulation in ISE Simulator
To run the integrated simulation processes in ISE:

1. Select the test bench waveform in the Sources in Project window. You can see the Xilinx ISE Simulator
processes in the Processes for Source window.
2. Double-click the Simulate Behavioral Model process. The ISE Simulator opens and runs the simulation
to the end of the test bench.
3. To see your simulation results, select the test bench tab and zoom in on the transitions. You can use the
zoom icons in the waveform view, or right click and select a zoom command.The ISE window, including
the waveform view.
4. Zoom in on the area between 300 ns and 900 ns to verify that the counter is counting up and down as
directed by the stimulus on the DIRECTION port.
5. Close the waveform view window. You have completed simulation of your design using the ISE
Simulator. Skip past the ModelSim section below and proceed to the “Creating and Editing Timing and
Area Constraints”section.
Simulating the Behavioral Model (ModelSim): If you have a ModelSim simulator installed, you can
simulate your design using the integrated ModelSim flow. You can run processes from within ISE which
launches the installed ModelSim simulator. To run the integrated simulation processes in ISE:
1. Select the test bench in the Sources in Project window. You can see ModelSim Simulator processes in
the Processes for Source window in Fig 6.
Fig 5: Simulator Processes for Test Bench
Fig 6:Behavioral Simulation in ModelSim
2. Double-click the Simulate Behavioral Model process. The ModelSim simulator opens and runs your
simulation to the end of the test bench. The ModelSim window, including the waveform, should look like
Fig 7.
To see your simulation results, view the Wave window.
1. Right-click in the Wave window and select a zoom command.
2. Zoom in on the area between 300 ns and 900 ns to verify that the counter is counting up and down as
directed by the stimulus on the DIRECTION port.
3. Close the ModelSim window.

RESULT:
Thus the Simulation tools was studied.

Expt.No:
STUDY OF SYNTHESIS TOOLS
Date :
AIM:
To study the Synthesis tools.
THEORY:
Now that you have created the source files, verified the design‟s behavior with simulation,and added
constraints, you are ready to synthesize and implement the design.

Implementing the Design:
1. Select the counter source file in the Sources in Project window.
2. In the Processes for Source window, click the “+” sign next to Implement Design. The Translate, Map,
and Place & Route processes are displayed. Expand those processes as well by clicking on the “+” sign.
You can see that there are many sub-processes and options that can be run during design implementation.
3. Double-click the top level Implement Design process.ISE determines the current state of your design
and runs the processes needed to pull your design through implementation. In this case, ISE runs the
Translate, Map and PAR processes. Your design is now pulled through to a placed-and-routed state. This
feature is called the “pull through model.”
4. After the processes have finished running, notice the status markers in the Processes for Source window.
You should see green checkmarks next to several of the processes, indicating that they ran successfully. If
there are any yellow exclamation points, check the warnings in the Console tab or the Warnings tab within
the Transcript window. If a red X appears next to a process, you must locate and fix the error before you
can continue.
Verification of Synthesis: Your synthesized design can be viewed as a schematic in the Register Transfer
Level (RTL) Viewer. The schematic view shows gates and elements independent of the targeted Xilinx®
device.
1. In the Processes for Source window, double-click View RTL Schematic found in the Synthesize
- XST process group. The top level schematic representation of your synthesized design opens in
the workspace.
2. Right-click on the symbol and select Push Into the Selected Instance to view the schematic in
detail. The Design tab appears in the Sources in Project window, enabling you to view the design
hierarchy. In the schematic, you can see the design components you created in the HDL source,
and you can “push into” symbols to view increasing levels of detail. 3. Close the schematic window.
Fig 1: Floorplanner View - Detailed View
Fig 2: Design Summary View
RESULT:
Thus the synthesis tools was studied.

Expt.No:
BASIC LOGIC GATES
Date :
AIM:
To implement basic logic gates using Verilog HDL.
APPARATUS REQUIRED:
 PC with Windows XP.

 XILINX, ModelSim software.
 FPGA kit.
 RS 232 cable.
PROCEDURE:
 Write and draw the Digital logic system.

 Write the Verilog code for above system.
 Enter the Verilog code in Xilinx software.
 Check the syntax and simulate the above verilog code (using ModelSim or Xilinx) and verify the
output waveform as obtained.
 Implement the above code in Spartan III using FPGA kit.
PROGRAM:
AND Gate:
AND Gate:
// Module Name: Andgate
module Andgate(i1, i2, out);
input i1; input i2;
output out;
and (out,i1,i2);
endmodule
Output:
OR Gate:
Output:
OR Gate:
// Module Name: Orgate
module Orgate(i1, i2, out);
input i1; input i2;
output out;
or(out,i1,i2);
endmodule
NAND Gate:
Output:
RESULT:
Thus the basic logic gates was implemented and the outputs are verified using Verilog coding.
Expt.No:
HALF ADDER AND FULL ADDER
Date :
AIM:
To implement half adder and full adder using Verilog HDL.
APPARATUS REQUIRED:
 PC with Windows XP
 FPGA kit
 RS 232 cable.
PROCEDURE:

HALF ADDER
A. PROGRAM
module HA(a, b, sum, carry);

input a;
input b;
output sum;
output carry;
xor g1(sum,a,b);
and g2(carry,a,b);
endmodule
B. SYNTHESIS REPORT
====================================================================
* Final Report *
====================================================================
Final Results
RTL Top Level Output File Nam : HA.ngr
Top Level Output File Name : HA
Output Format : NGC
Optimization Goal : Speed
Design Statistics
#IOs :4
Cell Usage :
#BELS :2
#LUT2 :2
#IO Buffers :4
#IBUF :2
#OBUF :2
====================================================================
Device utilization summary:
Selected Device : 3s400pq208-5
Number of Slices: 1 out of 3584 0%
Number of 4 input LUTs: 2 out of 7168 0%
Number of IOs: 4
Number of bonded IOBs: 4 out of 141 2%
====================================================================
TIMING REPORT
Clock Information: No clock signals found in this design

Asynchronous Control Signals Information: No asynchronous control signals found in this
design
Timing Summary:
Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 7.824ns
Timing Detail: All values displayed in nanoseconds (ns)

====================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 4 / 2
-------------------------------------------------------------------------
Delay: 7.824ns (Levels of Logic = 3)
Source: a (PAD)
Destination: carry (PAD)
Data Path: a to carry
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 2 0.715 1.040 a_IBUF (a_IBUF)
LUT2:I0->O 1 0.479 0.681 carry1 (carry_OBUF)
OBUF:I->O 4.909 carry_OBUF (carry)
----------------------------------------
Total 7.824ns (6.103ns logic, 1.721ns route) (78.0% logic, 22.0% route)
====================================================================
CPU: 8.02 / 8.47 s | Elapsed: 8.00 / 8.00 s
Total memory usage is 135284 kilobytes
C. SCHEMATIC DIAGRAM
D. SIMULATION OUTPUT
FULL ADDER
A. PROGRAM:
module FA(a, b, c, sum, carry);

input a,b,c;
output sum,carry;
wire l, m, n;
xor g1(l,a,b);
and g2(m,a,b);
xor g3(sum,l,c);
and g4(n,l,c);
or g5(carry,m,n);
endmodule
B. SYNTHESIS REPORT
====================================================================
* Final Report *
====================================================================
Final Results
RTL Top Level Output File Name : FA.ngr
Top Level Output File Name : FA
Output Format : NGC
Keep Hierarchy : NO
Design Statistics
#IOs :5
Cell Usage :
#BELS :2
#LUT3 :2
#IO Buffers :5
#IBUF :3
#OBUF :2
====================================================================
Number of IOs: 5
====================================================================
TIMING REPORT
design
Timing Summary:
Speed Grade: -5

====================================================================
-------------------------------------------------------------------------
Source: b (PAD)
Destination: carry (PAD)
Data Path: b to carry
Gate Net
---------------------------------------- ------------
IBUF:I->O 2 0.715 1.040 b_IBUF (b_IBUF)
LUT3:I0->O 1 0.479 0.681 carry1 (carry_OBUF)
OBUF:I->O 4.909 carry_OBUF (carry)
----------------------------------------
====================================================================
CPU : 7.59 / 8.00 s | Elapsed : 8.00 / 8.00 s
RESULT:
Thus the half adder and full adder was implemented and the outputs are verified using Verilog coding
Expt.No:
HALF SUBTRACTOR AND FULL SUBTRACTOR
Date :
AIM:
To implement half subtractor and full subtractor using Verilog HDL.
APPARATUS REQUIRED:
 FPGA kit
 RS 232 cable.
PROCEDURE:
Write and draw the Digital logic system.

Write the Verilog code for above system.
Enter the Verilog code in Xilinx software.
Check the syntax and simulate the above verilog code (using ModelSim or Xilinx) and verify the
Implement the above code in Spartan III using FPGA kit.
HALF SUBTRACTOR
A. PROGRAM
module HALF_SUBTRACTOR(diff,borrow,a,b);
output diff,borrow;
input a,b;
wire w;
xor g1(diff,a,b);
not g2(w,a);
and(borrow,w,b);
endmodule
B. SYNTHESIS REPORT
=====================================================================
* Final Report *
=====================================================================
Final Results
RTL Top Level Output File Name : HALF_SUBTRACTOR.ngr
Top Level Output File Name : HALF_SUBTRACTOR
Output Format : NGC
Design Statistics
#IOs :4
Cell Usage :
#BELS :2
#LUT2 :2
#IO Buffers :4
#IBUF :2
#OBUF :2
=====================================================================
Number of IOs: 4
=====================================================================
TIMING REPORT

Asynchronous Control Signals Information: No asynchronous control signals found in this design
Timing Summary:
Speed Grade: -5
=====================================================================
-------------------------------------------------------------------------
Source: b (PAD)
Destination: diff (PAD)
Data Path: b to diff
Gate Net
---------------------------------------- ------------
IBUF:I->O 2 0.715 1.040 b_IBUF (b_IBUF)
LUT2:I0->O 1 0.479 0.681 Mxor_diff_Result1 (diff_OBUF)
OBUF:I->O 4.909 diff_OBUF (diff)
----------------------------------------
=====================================================================
CPU : 7.89 / 8.33 s | Elapsed : 8.00 / 8.00 s
D. SIMUALATION OUTOUT
FULL SUBTRACTOR
A. PROGRAM
module FS(a,b,c,diff,borrow);
input a,b,c;
output diff,borrow;
wire l,m,n,o,p;
xor x1(l,a,b);
xor x2(diff,l,c);
not n1(m,a);
and a1(n,m,b);
and a2(o,m,c);
and a3(p,b,c);
or o1(borrow,n,o,p);
endmodule
B. SYNTHESIS REPORT
=====================================================================
* Final Report *
=====================================================================
Final Results
RTL Top Level Output File Name : FS.ngr
Top Level Output File Name : FS
Output Format : NGC
Design Statistics
# IOs :5
Cell Usage :
# BELS :2
# LUT3 :2
# IO Buffers :5
# IBUF :3
#OBUF :2
=====================================================================
Number of IOs: 5
=====================================================================
TIMING REPORT:
Asynchronous Control Signals Information: No asynchronous control signals found in this design
Timing Summary:
Speed Grade: -5
Minimum period: No path found3333
=====================================================================
-------------------------------------------------------------------------
Source: a (PAD)
Destination: diff (PAD)
Data Path: a to diff
Gate Net
---------------------------------------- ------------
IBUF:I->O 2 0.715 1.040 a_IBUF (a_IBUF)
LUT3:I0->O 1 0.479 0.681 FS_0_xo<1>1 (diff_OBUF)
OBUF:I->O 4.909 diff_OBUF (diff)
----------------------------------------
=====================================================================
CPU : 8.02 / 8.48 s | Elapsed : 8.00 / 9.00 s
RESULT
Thus the half subtractor and full subtractor was implemented and the outputs are verified using
Verilog coding.
Expt.No:
MULTIPLEXER AND DE MULTIPLEXER
Date :
AIM:
To implement multiplexer and de multiplexer using Verilog HDL.
APPARATUS REQUIRED:
PC with Windows XP
XILINX, ModelSim software.
FPGA kit
RS 232 cable.
PROCEDURE:

MUX
A. PROGRAM
module MUX(out,i0,i1,i2,i3,s1,s0);
input i0,i1,i2,i3,s1,s0;
output out;
reg out;
always@(s1 or s0 or i0 or i1 or i2 or i3)
case({s1,s0})
2'b00:out=i0;
2'b01:out=i1;
2'b10:out=i2;
2'b11:out=i3;
endcase
endmodule
B. SYNTHESIS REPORT
==================================================================
* Final Report *
==================================================================
RTL Top Level Output File Name : MUX.ngr
Top Level Output File Name : MUX
Output Format : NGC
Design Statistics
# IOs :7
Cell Usage :
# BELS :3
# LUT3 :2
#MUXF5 :1
#IO Buffers :7
#IBUF :6
#OBUF :1
==================================================================
Number of IOs: 7
==================================================================
TIMING REPORT
design
Timing Summary:
Speed Grade: -5
==================================================================
Source: s0 (PAD)
Destination: out (PAD)
Data Path: s0 to out
Gate Net
---------------------------------------- ------------
IBUF:I->O 2 0.715 1.040 s0_IBUF (s0_IBUF)
LUT3:I0->O 1 0.479 0.000 s0 (N21)
MUXF5:I1->O 1 0.314 0.681 Mmux_out_f5 (out_OBUF)
OBUF:I->O 4.909 out_OBUF (out)
----------------------------------------
==================================================================
CPU : 7.55 / 7.97 s | Elapsed : 7.00 / 8.00 s
DEMUX
A. PROGRAM
module DEMUX(din,sel,y);
input din;
input [1:0]sel;
output [3:0]y;
reg [3:0]y;
always@(sel)
begin
case(sel)
2'b00:begin y[0]=din;y[1]=0;y[2]=0;y[3]=0;end
2'b01:begin y[0]=0;y[1]=din;y[2]=0;y[3]=0;end
2'b10:begin y[0]=0;y[1]=0;y[2]=din;y[3]=0;end
2'b11:begin y[0]=0;y[1]=0;y[2]=0;y[3]=din;end
endcase
end
endmodule
B. SYNTHESIS REPORT
==================================================================
* Final Report *
==================================================================
Final Results
RTL Top Level Output File Name : DEMUX.ngr
Top Level Output File Name : DEMUX
Output Format : NGC
Design Statistics
# IOs :7
Cell Usage :
#BELS :4
#LUT3 :4
#IO Buffers :7
#IBUF :3
#OBUF :4
==================================================================
Number of IOs: 7
==================================================================
TIMING REPORT
design
Timing Summary:
Speed Grade: -5
==================================================================
Source: sel<0> (PAD)
Destination: y<3> (PAD)
Data Path: sel<0>to y<3>
Gate Net
---------------------------------------- ------------
IBUF:I->O 4 0.715 1.074 sel_0_IBUF (sel_0_IBUF)
LUT3:I0->O 1 0.479 0.681 Mmux_y<3>11 (y_3_OBUF)
OBUF:I->O 4.909 y_3_OBUF (y<3>)
----------------------------------------
==================================================================
CPU : 6.89 / 7.34 s | Elapsed : 7.00 / 7.00 s
E.SIMULATION OUTPUT
RESULT
Thus the multiplexer and demultiplexer was implemented and the outputs are verified using Verilog
coding.
Expt.No:
ENCODER AND DECODER
Date :
AIM:
To implement encoder and de encoder using Verilog HDL.
APPARATUS REQUIRED:
PC with Windows XP
FPGA kit
RS 232 cable.
PROCEDURE:

ENCODER
A. PROGRAM
module ENCODER(y,i);
input [3:0]i;
output [1:0]y;
reg[1:0]y;
always@(i or y)
begin
case(i)
4'b0001:y=2'b00;
4'b0010:y=2'b01;
4'b0100:y=2'b10;
4'b1000:y=2'b11;
endcase
end
endmodule
B. SYNTHESIS REPORT
====================================================================
* Final Report *
====================================================================
Final Results
RTL Top Level Output File Name : ENCODER.ngr
Top Level Output File Name : ENCODER
Output Format : NGC
Design Statistics
# IOs :6
Cell Usage :
#BELS :3
#LUT4 :3
#FlipFlops/Latches :2
#LD :2
#IO Buffers :6
#IBUF :4
#OBUF :2
====================================================================
Selected Device: 3s400pq208-5
Number of Slice Flip Flops: 2 out of 7168 0%
Number of IOs: 6
IOB Flip Flops: 2
====================================================================
TIMING REPORT

design
Timing Summary:
Speed Grade: -5
Minimum input arrival time before clock: 2.436ns
Maximum output required time after clock: 6.141ns
Maximum combinational path delay: No path found
====================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'y_not0001'
-------------------------------------------------------------------------
Offset: 2.436ns (Levels of Logic = 2)
Source: i<1> (PAD)
Destination: y_0 (LATCH)
Destination Clock: y_not0001 falling
Data Path: i<1> to y_0
Gate Net
---------------------------------------- ------------
IBUF:I->O 3 0.715 1.066 i_1_IBUF (i_1_IBUF)
LUT4:I0->O 1 0.479 0.000 y_mux0000<0>1 (y_mux0000<0>)
LD:D 0.176 y_0
----------------------------------------
Total 2.436ns (1.370ns logic, 1.066ns route)(56.2% logic, 43.8% route)
====================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'y_not0001'
-------------------------------------------------------------------------
Source: y_1 (LATCH)
Destination: y<1> (PAD)
Source Clock: y_not0001 falling
Data Path: y_1 to y<1>
Gate Net
---------------------------------------- ------------
LD:G->Q 1 0.551 0.681 y_1 (y_1)
OBUF:I->O 4.909 y_1_OBUF (y<1>)
----------------------------------------
====================================================================
CPU : 6.78 / 7.24 s | Elapsed : 7.00 / 7.00 s
C. SCEMATIC DIAGRAM
DECODER
A. PROGRAM
module DECODER(d,i);
input [1:0]i;
output [3:0]d;
reg [3:0]d;
always@(i or d)
begin
case(d)
2'b00:d=4'b0001;
2'b01:d=4'b0010;
2'b10:d=4'b0100;
2'b11:d=4'b1000;
endcase
end
endmodule
B. SYNTHESIS REPORT
====================================================================
* Final Report *
====================================================================
Final Results
RTL Top Level Output File Name : DECODER.ngr
Top Level Output File Name : DECODER
Output Format : NGC
Keep Hierarchy : NO
Design Statistics
#IOs :6
Cell Usage :
#BELS :4
#LUT2 :4
#IO Buffers :6
#IBUF :2
#OBUF :4
====================================================================
Number of IOs: 6
====================================================================
TIMING REPORT
design
Timing Summary:
Speed Grade: -5
====================================================================
-------------------------------------------------------------------------
Source: i<0> (PAD)
Destination: d<3> (PAD)
Data Path: i<0> to d<3>
Gate Net
---------------------------------------- ------------
IBUF:I->O 4 0.715 1.074 i_0_IBUF (i_0_IBUF)
LUT2:I0->O 1 0.479 0.681 Mdecod_d31 (d_3_OBUF)
OBUF:I->O 4.909 d_3_OBUF (d<3>)
----------------------------------------
====================================================================
CPU : 6.78 / 7.25 s | Elapsed : 7.00 / 7.00 s
RESULT
Thus the encoder and decoder was implemented and the outputs are verified using Verilog coding
Expt.No:
COUNTERS
Date :
AIM:
To implement counters using Verilog HDL.
APPARATUS REQUIRED:
PC with Windows XP
FPGA kit
RS 232 cable.
PROCEDURE:

COUNTER
A. PROGRAM
module COUNTER(clk,clr,q);
input clk,clr;
output [3:0]q;
reg [3:0]tmp;
always @(posedgeclk or posedgeclr)
begin
if (clr)
tmp = 4'b0000;
else
tmp = tmp + 1'b1;
end
assign q = tmp;
endmodule
B. SYNTHESIS REPORT
==================================================================
* Final Report *
==================================================================
RTL Top Level Output File Name : COUNTER.ngr
Top Level Output File Name : COUNTER
Output Format : NGC
Design Statistics
# IOs :6
Cell Usage :
# BELS :4
#INV :1
#LUT2 :1
#LUT3 :1
#LUT4 :1
# FlipFlops/Latches :4
#Clock Buffers : 1
#BUFGP :1
#IO Buffers :5
#IBUF :1
#OBUF :4
==================================================================
Number of IOs: 6
Number of GCLKs: 1 out of 8 12%
==================================================================
TIMING REPORT
Clock Information:
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP |4 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
-----------------------------------+------------------------+-------+
Control Signal | Buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clr | IBUF |4 |
-----------------------------------+------------------------+-------+
Timing Summary:
Speed Grade: -5
Minimum period: 2.745ns (Maximum Frequency: 364.339MHz)
Maximum combinational path delay: No path found
==================================================================
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 2.745ns (frequency: 364.339MHz)
Source: tmp_0 (FF)
Destination: tmp_0 (FF)
Source Clock: clk rising
Destination Clock: clk rising
Data Path: tmp_0 to tmp_0
Gate Net
---------------------------------------- ------------
FDC:C->Q 5 0.626 0.783 tmp_0 (tmp_0)
INV:I->O 1 0.479 0.681 Mcount_tmp_xor<0>11_INV_0 (Result<0>)
FDC:D 0.176 tmp_0
----------------------------------------
==================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
-------------------------------------------------------------------------
Source: tmp_0 (FF)
Destination: q<0> (PAD)
Source Clock: clk rising
Data Path: tmp_0 to q<0>
Gate Net
---------------------------------------- ------------
FDC:C->Q 5 0.626 0.783 tmp_0 (tmp_0)
OBUF:I->O 4.909 q_0_OBUF (q<0>)
----------------------------------------
==================================================================
CPU : 6.84 / 7.34 s | Elapsed : 7.00 / 7.00 s
ASYNCHRONOUS COUNTER
A. PROGRAM
module counter( clk, count );

input clk;
output[3:0] count;
reg[3:0] count;
wire clk;
initial
count = 4'b0;
always @( negedgeclk )
count[0] <= ~count[0];
always @( negedge count[0] )
endmodule
B. FINAL REPORT
====================================================================
* Final Report *
====================================================================
Final Results
RTL Top Level Output File Name : counter.ngr
Top Level Output File Name : counter
Output Format : NGC
Design Statistics
# IOs :5
Cell Usage :
#BELS :1
# VCC :1
#FlipFlops/Latches :4
#FDR_1 :4
#Clock Buffers :1
#BUFGP :1
#IO Buffers :4
#OBUF :4
====================================================================
Number of IOs: 5
Number of GCLKs: 1 out of 8 12%
====================================================================
TIMING REPORT
Clock Information:
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP |1 |
count_0 | NONE(count_1) |1 |
-----------------------------------+------------------------+-------+
design
Timing Summary:
Speed Grade: -5
Minimum period: 2.289ns (Maximum Frequency: 436.882MHz)
====================================================================
Timing constraint: Default period analysis for Clock 'clk'
-------------------------------------------------------------------------
Source: count_0 (FF)
Destination: count_0 (FF)
Source Clock: clk falling
Destination Clock: clk falling
Data Path: count_0 to count_0
Gate Net
---------------------------------------- ------------
FDR_1:C->Q 3 0.626 0.771 count_0 (count_0)
FDR_1:R 0.892 count_0
----------------------------------------
====================================================================
Timing constraint: Default period analysis for Clock 'count_0'
-------------------------------------------------------------------------
Source Clock: count_0 falling
Destination Clock: count_0 falling
Gate Net
---------------------------------------- ------------
----------------------------------------
====================================================================
-------------------------------------------------------------------------
Gate Net
---------------------------------------- ------------
----------------------------------------
====================================================================
-------------------------------------------------------------------------
Gate Net
---------------------------------------- ------------
----------------------------------------
====================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'count_2'
-------------------------------------------------------------------------
Destination: count<3> (PAD)
Data Path: count_3 to count<3>
Gate Net
---------------------------------------- ------------
OBUF:I->O 4.909 count_3_OBUF (count<3>)
----------------------------------------
====================================================================
-------------------------------------------------------------------------
Gate Net
---------------------------------------- ------------
----------------------------------------
====================================================================
-------------------------------------------------------------------------
Gate Net
---------------------------------------- ------------
----------------------------------------
D. SIMULATIUON OUTPUT
RESULT
Thus the synchronous and asynchronous counters was implemented and the outputs are verified
using Verilog coding
Expt.No:
CARRY LOOK AHEAD ADDER
Date :
AIM:
To implement carry look ahead adder using Verilog HDL.
APPARATUS REQUIRED:
PC with Windows XP
FPGA kit
RS 232 cable.
PROCEDURE:

CARRY LOOK AHEAD ADDER
A. PROGRAM
module CLAA(a, b, cin, s, cout);

input [3:0] a;
input [3:0] b;
input cin;
output [3:0] s;
output cout;
wire[3:0]g;
wire[3:0]p;
wire[3:1]c;
assign g[3:0]=a[3:0]&b[3:0];
assign p[3:0]=a[3:0]^b[3:0];
assign c[1]=g[0]|p[0]&cin;
assign c[2]=g[1]|g[0]&p[1]|p[0]&p[1]&cin;
assign c[3]=g[2]|g[1]&p[2]|g[0]&p[1]&p[2]|p[0]&p[1]&p[2]&cin;
assign
cout=g[3]|g[2]&p[3]|g[1]&p[2]&p[3]|g[0]&p[1]&p[2]&p[3]|cin&p[0]&p[1]&p[2]&p[3];
assign s[0]=p[0]^cin;
assign s[3:1]=p[3:1]^c[3:1];
endmodule
B. SYNTHESIS REPORT
=================================================================
* Final Report *
=================================================================
Final Results
RTL Top Level Output File Name : CLAA.ngr
Top Level Output File Name : CLAA
Output Format : NGC
Keep Hierarchy : NO
Design Statistics
# IOs : 14
Cell Usage :
# BELS :8
# LUT3 :8
# IO Buffers : 14
# IBUF :9
# OBUF :5
=================================================================
Number of IOs: 14
=================================================================
TIMING REPORT
design
Timing Summary:
Speed Grade: -5
-------------------------------------------------------------------------
Source: b<0> (PAD)
Destination: cout (PAD)
Data Path: b<0> to cout
Gate Net
---------------------------------------- ------------
IBUF:I->O 2 0.715 1.040 b_0_IBUF (b_0_IBUF)
LUT3:I0->O 2 0.479 0.804 c_1_or00001 (c<1>)
LUT3:I2->O 2 0.479 0.915 c_2_or0000 (c<2>)
LUT3:I1->O 2 0.479 0.915 c_3_or00001 (c<3>)
LUT3:I1->O 1 0.479 0.681 cout1 (cout_OBUF)
OBUF:I->O 4.909 cout_OBUF (cout)
----------------------------------------
=================================================================
CPU : 6.95 / 7.45 s | Elapsed : 7.00 / 8.00 s
RESULT
Thus the carry look ahead adder was implemented and the outputs are verified using Verilog coding
Expt.No:
Date :
MOORE FSM
AIM
To develop the source code for design the sequential circuit using VHDL and to obtain the
simulation synthesis, phase and route and implement into FPGA.
REQUIREMENTS
XILINX ISE 8.2I.
Model sim 5.7g.
Personal computer.
ALGORITHM
1. XILINX ISE software window is invoked.
2. New file is opened and a file name is given.
3. Source file is selected if any.
4. Addition of existing file is done if any.
5. Finish is clicked.
6. In project, source is selected.
7. Verilog module is selected and a file name is entered.
8. Input and output are set and it is finished.
9. Verilog codes is entered and saved.
10. Source file is selected to behavioral simulation.
11. In the simulation window, the input signals are forced and the output is verified accordingly
PROGRAM
VERILOG CODE
module moore(a, clk, z);

input a;
input clk;
output z;
reg z;
parameter st0=0,st1=1,st2=2,st3=3;
reg[1:0] moore_state;
initial
begin
moore_state=st0;
end
always@(posedge (clk))
case(moore_state)
st0:
begin
z=1;
if(a)
moore_state=st1;
else
moore_state=st0;
end
st1:
begin
z=0;
if(a)
moore_state=st3;
else
moore_state=st1;
end
st2:
begin
z=0;
if(~a)
moore_state=st1;
else
moore_state=st0;
end
st3:
begin
z=1;
if(a)
moore_state=st2;
else
moore_state=st0;
end
endcase
endmodule
OUTPUT WAVEFORM:
RESULT
Thus a Moore FSM is designed and the outputs are verified using Verilog coding
Expt.No:
Date :
MELAY FSM
AIM
To develop the source code for design the sequential circuit using VHDL and to obtain the
simulation synthesis, phase and route and implement into FPGA.
REQUIREMENTS
XILINX ISE 8.2I
Model sim 5.7g.
Personal computer.
ALGORITHM
1. XILINX ISE software window is invoked.
2. New file is opened and a file name is given.
3. Source file is selected if any.
4. Addition of existing file is done if any.
5. Finish is clicked.
6. In project, source is selected.
7. Verilog module is selected and a file name is entered.
8. Input and output are set and it is finished.
9. Verilog codes is entered and saved.
10. Source file is selected to behavioral simulation.
11. In the simulation window, the input signals are forced and the output is verified
accordingly.
PROGRAM:
VERILOG CODE
module melay(a, clk, z);

input a;
input clk;
output z;
reg z;
parameter st0=0,st1=1,st2=2,st3=3;
reg[0:1]melay_state;
initial
begin
melay_state=st0;
end
always @(posedge(clk))
case(melay_state)
st0:
begin
if(a)
begin
z=1;
melay_state=st3;
end
else
z=0;
end
st1:
begin
if(a)
begin
z=0;
melay_state=st0;
end
else
z=1;
end
st2:
begin
if(a)
begin
z=1;
melay_state=st1;
end
else
z=0;
end
st3:
begin
z=0;
if(a)
begin
melay_state=st2;
end
else
melay_state=st1;
end
endcase
endmodule
OUTPUT WAVEFORM:
RESULT
Thus a Melay FSM is designed and the outputs are verified using Verolog coding.
Expt.No:
IMPLEMENTATION OF CMOS INVERTER USING TANNER
Date :
AIM:
To perform the functional verification of the CMOS Inverter through schematic entry.
APPARATUS REQUIRED:
S-Edit using Tanner Tool.
THEORY:
CMOS Inverter consist of nMOS and pMOS transistor in series connected between VDD and GND. The
gate of the two transistors are shorted and connected to the input. When the input to the inverter A = 0,
nMOS transistor is OFF and pMOS transistor is ON. The output is pull-up to VDD. When the input A =
1, nMOS transistor is ON and pMOS transistor is OFF. The Output is Pull-down to GND.
PROCEDURE
1. Draw the schematic of CMOS Inverter using S-edit.

2. Perform Transient Analysis of the CMOS Inverter.
3. Obtain the output waveform from W-edit.
4. Obtain the spice code using T-edit.
RESULT:
Thus the CMOS inveter was implemented using tanner and the output was verified. .
Expt.No:
IMPLEMENTATION OF DIFFERENTIAL AMPLIFIER USING TANNER
Date :
AIM:
To calculate the gain, bandwidth and CMRR of a differential amplifier through schematic entry.
APPARATUS REQUIRED:
Theory :
A differential amplifier is a type of electronic amplifier that multiplies the difference between two
inputs by some constant factor (the differential gain).
Many electronic devices use differential amplifiers internally. The output of an ideal differential
amplifier is given by:
Where and are the input voltages and Ad is the differential gain. In practice, however, the gain is not
quite equal for the two inputs. This means that if and are equal, the output will not be zero, as it would be
in the ideal case. A more realistic expression for the output of a differential amplifier thus includes a
second term.
Ac is called the common-mode gain of the amplifier. As differential amplifiers are often used when it is
desired to null out noise or bias-voltages that appear at both inputs, a low common-mode gain is usually
considered good.
The common-mode rejection ratio, usually defined as the ratio between differential-mode gain and
common-mode gain, indicates the ability of the amplifier to accurately cancel voltages that are common
to both inputs. Common-mode rejection ratio (CMRR):
PROCEDURE
1. Draw the schematic of differential amplifier using S-edit and generate the symbol
2. Draw the schematic of differential amplifier circuit using the generated symbol.
3. Perform AC Analysis of the differential amplifier.
4. Obtain the frequency response from W-edit.
RESULT:
Thus the CMOS differential amplifer was implemented using tanner and the output was verified.
Expt.No:
IMPLEMENTATION OF CMOS NAND GATE USING TANNER
Date :
AIM:
To perform the functional verification of the CMOS NANDthrough schematic entry.
APPARATUS REQUIRED:
THEORY:
If both of the A and B inputs are high, then both the NMOS transistors (bottom half of the diagram) will conduct,
neither of the PMOS transistors (top half) will conduct, and a conductive path will be established between the
output and Vss (ground), bringing the output low. If either of the A or B inputs is low, one of the NMOS transistors
will not conduct, one of the PMOS transistors will, and a conductive path will be established between the output
and Vdd (voltage source), bringing the output high.
PROCEDURE
1. Draw the schematic of CMOS NANDusing S-edit.

2. Perform Transient Analysis of the CMOS NAND.
SCHEMATIC DIAGRAM
OUTPUT
RESULT
Thus the CMOS NAND gate was implemented using tanner and the output was verified.
Expt.No:
IMPLEMENTATION OF CMOS NOR GATE USING TANNER
Date :
AIM
To perform the functional verification of the CMOS NOR through schematic entry.
APPARATUS REQUIRED
THEORY
The NOR gate is a digital logic gate that implements logical NOR - it behaves according to the truth table to the
right. A HIGH output (1) results if both the inputs to the gate are LOW (0); if one or both input is HIGH (1), a
LOW output (0) results. NOR is the result of the negation of the OR operator. It can also be seen as an AND gate
with all the inputs inverted. NOR is a functionally complete operation—combinations of NOR gates can be
combined to generate any other logical function. By contrast, the OR operator is monotonic as it can only change
LOW to HIGH but not vice versa
PROCEDURE
1. Draw the schematic of CMOS NOR using S-edit.

2. Perform Transient Analysis of the CMOS NOR.
SCHEMATIC DIAGRAM
OUTPUT
RESULT
Thus the CMOS NOR gate was implemented using tanner and the output was verified
Expt.No:
IMPLEMENTATION OF LAYOUT OF CMOS INVERTER USING TANNER
Date :
AIM:
To draw the layout of CMOS Inverter using L-Edit and extract the SPICE code.
APPARATUS REQUIRED:
L-Edit & T-SPICE - Tanner Tool.
PROCEDURE
1. Draw the CMOS Inverter layout by obeying the Lamda Rules using L-edit.
i. Poly - 2λ
ii. Active contact - 2 λ
iii. Active Contact – Metal - 1 λ
iv. Active Contact – Active region - 2 λ
v. Active Region – Pselect - 3 λ
vi. Pselect – nWell - 3λ
2. Check DRC to verify whether any region violate the lamda rule.
3. Setup the extraction and extract the spice code using T-spice.
RESULT:
The layout of CMOS Inverter was drawn and generated the SPICE Code.
HARDWARE FUSING AND
TESTING OF FPGA
Expt.No:
HARDWARE FUSING AND TESTING OF 8:1 MULTIPLEXER USING FPGA
Date : KIT
AIM
To implement the multiplexer in FPGA and to verify its output.
APPARATUS REQUIRED
PC With XILINX Software
FPGA KIT
PROCEDURE
Step1:Start the Xilinx project navigator by using the desk top short cut or by using the
startProgramXilinx ISE Project Navigator.
Step2:In the Project navigator window go to file  New  Project  Select Device
Step3:click on the symbol of FPGA device and then right click click on new sourceVHDL
module and give the name mux-8-1define portsfinish
Step 4: Generate behavioral VHDL codes for mux-8-1
Step 5: Check syntax and remove error if present
Step 6: Simulate the design using modelsim
Highlight mux-8-1 and Vnd file in the sources in project window. To run the fundamental
simulation click on the symbol of FPGA device and then right click click on new sourceclick on test
bench waveformGive file nameselect entityfinishgive inputsclick on simulate behavioral
modelsee the output
Step 7: Synthesize the design using XST
Highlight 8:3 encoder Vnd file in the source in project window. To run synthesis right click
on synthesis and choose run synthesis. Double click on synthesis in the process for current source
window. Synthesis will run and green check will appear next to synthesis
Step 8: When it is completed successfully a yellow exclamation mark indicates that a warning
was generated and a red cross indicates an error was generated
Step9: If there are any error you can view the error through the console window otherwise
continue to the next step
Step 10: Write user constraint file window. The FPGA pins are locked as per the Spartan 3
hardware
Step 11: Run the Xilinx implementation tools
Once synthesize is complete you can place and route your design to bit into Xilinx device
and you can also get some post place and route timing information about the design. This produce runs
you through the basic flow for implementation
Step 12: Right click on implementation design and choose run option or double click on
implementation design
Step 13: Double click on configure device to download the bit stream
Click on new sourceclick on test benchgive file nameselect entityfinishgive
inputsclick on simulate behavioral modelsee the output
Step 14: Stnthesize the design using XST
Highlight 2:4 decoder Vnd file in the source in project window. To run synthesis right click
window. Synthesis will run and green check will appear next to synthesis. When it is completed
successfully a yellow exclamation mark indicates that a warning was generated and a red cross
indicates an error was generated.
hardware.
you through the basic flow for implementation.
Step 17: Right click on generate programming file and choose the run option or double click on
left generate programming file. This will generate the bit stream
Step 18: Double click on implement design and choose the run option or double left click on
implement design
Step 20: Apply input through DIP switches and select lines are napped to output displayed on
LEDs
RESULT
Thus the hardware fusing and testing of 8:1 multiplexer using fpga kit was implemented and the
output was verified.
Expt.No:
HARDWARE FUSING AND TESTING OF 8:3 ENCODER USING FPGA KIT
Date :
AIM
To implement the encoder in FPGA and to verify its output.
APPARATUS REQUIRED
FPGA KIT
PROCEDURE
module and give the name encoder-8-3define portsfinish
Step 4: Generate behavioral VHDL codes for encoder-8-3
Highlight encoder-8-3 and Vnd file in the sources in project window. To run the
fundamental simulation click on the symbol of FPGA device and then right click click on new
sourceclick on test bench waveformGive file nameselect entityfinishgive inputsclick on
simulate behavioral modelsee the output
Highlight 8:3 encoder Vnd file in the source in project window. To run synthesis right click
hardware
successfully a yellow exclamation mark indicates that a warning was generated and a red cross indicates
an error was generated.
hardware.
implement design
LEDs
RESULT
Thus the hardware fusing and testing of 8:3 encoder using fpga kit was implemented and the output was
verified.
Expt.No:
HARDWARE FUSING AND TESTING OF 2:4 DECODER USING FPGA KIT
Date :
AIM
To implement the decoder in FPGA and to verify its output.
APPARATUS REQUIRED
FPGA KIT
PROCEDURE
module and give the name decoder-2-4define portsfinish
Step 4: Generate behavioral VHDL codes for decoder-2-4
Highlight decoder-2-4 and Vnd file in the sources in project window. To run the
Highlight 8:3 decoderVnd file in the source in project window. To run synthesis right click
hardware
hardware.
implement design
LEDs
RESULT
Thus the hardware fusing and testing of 2:4 decoder using fpga kit was implemented and the output was
verified.
Expt.No:
HARDWARE FUSING AND TESTING OF FULL ADDER USING FPGA KIT
Date :
AIM
To implement the full adder in FPGA and to verify its output.
APPARATUS REQUIRED
FPGA KIT
PROCEDURE
module and give the name full adder-define portsfinish
Step 4: Generate behavioral VHDL codes for full adder-
Highlight full adder- and Vnd file in the sources in project window. To run the
Highlight 8:3 full adderVnd file in the source in project window. To run synthesis right
click on synthesis and choose run synthesis. Double click on synthesis in the process for current source
hardware
Highlight 2:4 full adderVnd file in the source in project window. To run synthesis right
click on synthesis and choose run synthesis. Double click on synthesis in the process for current source
hardware.
implement design
LEDs
RESULT
Thus the hardware fusing and testing of full adder using fpga kit was implemented and the output was
verified.
Expt.No:
BRAUN MULTIPLIER
Date :
AIM
To design, simulate and synthesize a Braun multiplier.
APPARATUS REQUIRED
 FPGA kit
 RS 232 cable.
PROCEDURE

LOGIC DIAGRAM:
A.PROGRAM
module multi(a, b, p);
input [3:0] a;
input [3:0] b;
output [7:0] p;
wire e;
wire[15:1]t;
wire[10:0]f;
wire[8:1]s;
assign e=1'b0;
and
a01(p[0],a[0],b[0]),
a02(t[1],a[1],b[0]),
a03(t[2],a[2],b[0]),
a04(t[3],a[3],b[0]),
a05(t[4],a[0],b[1]),
a06(t[5],a[1],b[1]),
a07(t[6],a[2],b[1]),
a08(t[7],a[3],b[1]),
a09(t[8],a[0],b[2]),
a10(t[9],a[1],b[2]),
a11(t[10],a[2],b[2]),
a12(t[11],a[3],b[2]),
a13(t[12],a[0],b[3]),
a14(t[13],a[1],b[3]),
a15(t[14],a[2],b[3]),
a16(t[15],a[3],b[3]);
fa
fa1(t[4],e,t[1],p[1],f[0]),
fa2(t[5],e,t[2],s[1],f[1]),
fa3(t[6],e,t[3],s[2],f[2]),
fa4(t[8],f[0],s[1],p[2],f[3]),
fa5(t[9],f[1],s[2],s[4],f[4]),
fa6(t[10],f[2],t[7],s[5],f[5]),
fa7(t[12],f[3],s[4],p[3],f[6]),
fa8(t[13],f[4],s[5],s[7],f[7]),
fa9(t[14],f[5],t[11],s[8],f[8]),
fa10(e,f[6],s[7],p[4],f[9]),
fa11(f[9],f[7],s[8],p[5],f[10]),
fa12(f[10],f[8],t[15],p[6],p[7]);
endmodule
module fa(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
wire l,m,n,o,p;
and g1(l,a,b);
and g2(m,b,c);
and g3(n,c,a);
or g4(o,l,m);
or g5(carry,o,n);
xor g6(p,a,b);
xor g7(sum,p,c);
endmodule
D.SIMULATION OUTPUT
RESULT
Thus a Braun Multiplier is designed and the outputs are verified using Verilog coding.

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VLSI DESIGN FLOW

BASIC DESIGN FLOW

Creating a Test Bench for Simulation:

1. Select the counter HDL file in the Sources in Project window.

 Clock Time Low: 20 ns.

 Input Setup Time: 10 ns.

 Output Valid Delay: 10 ns.

 Global Signals: GSR (FPGA)

Fig 2:Waveform Editor - Expected Results

5. Select File _ Save to save the waveform.

Simulating the Behavioral Model (ISE Simulator):

Fig 3:Simulator Processes for Test Bench

Fig 4:Behavioral Simulation in ISE Simulator

To run the integrated simulation processes in ISE:

Fig 5: Simulator Processes for Test Bench

Fig 6:Behavioral Simulation in ModelSim

To see your simulation results, view the Wave window.

1. Right-click in the Wave window and select a zoom command.

3. Close the ModelSim window.

Thus the Simulation tools was studied.

constraints, you are ready to synthesize and implement the design.

Fig 2: Design Summary View

Thus the synthesis tools was studied.

 PC with Windows XP.

 Write and draw the Digital logic system.

// Module Name: Orgate

module Orgate(i1, i2, out);

input i1; input i2;

 Write and draw the Digital logic system.

module HA(a, b, sum, carry);

Clock Information: No clock signals found in this design

Timing Detail: All values displayed in nanoseconds (ns)

module FA(a, b, c, sum, carry);

Timing Detail: All values displayed in nanoseconds (ns)

Write and draw the Digital logic system.

Clock Information: No clock signals found in this design

Write and draw the Digital logic system.

Write and draw the Digital logic system.

Clock Information: No clock signals found in this design

Write and draw the Digital logic system.

module counter( clk, count );

Write and draw the Digital logic system.

CARRY LOOK AHEAD ADDER

module CLAA(a, b, cin, s, cout);

XILINX ISE 8.2I.

Model sim 5.7g.

1. XILINX ISE software window is invoked.

2. New file is opened and a file name is given.

3. Source file is selected if any.

4. Addition of existing file is done if any.

6. In project, source is selected.

7. Verilog module is selected and a file name is entered.

8. Input and output are set and it is finished.

9. Verilog codes is entered and saved.

10. Source file is selected to behavioral simulation.

module moore(a, clk, z);

XILINX ISE 8.2I

Model sim 5.7g.

1. XILINX ISE software window is invoked.

2. New file is opened and a file name is given.

3. Source file is selected if any.

4. Addition of existing file is done if any.

6. In project, source is selected.