High - Speed Digital IC Design PDF

ECE 225
High-Speed Digital IC Design

Lecture 3
Prof. Kaustav Banerjee

Electrical and Computer Engineering
E-mail: kaustav@ece.ucsb.edu
Lecture 3, ECE 225 Kaustav Banerjee

The Diode
B Al A
SiO2
Cross-section of pn-junction in an IC process
A Al
p A
B B
One-dimensional
representation diode symbol
Mostly occurring as parasitic element in Digital ICs

Diode Current
Current
increases by
a factor of 10
every 60 mV
Ideal diode equation:

ID= diode current, VD=diode bias voltage
IS= saturation current of diode (constant) proportional to diode area, and function of the doping
levels and width of neutral regions
ΦT=thermal voltage =kT/q=26mV at 300K
Diode Model
series resistance due to the

RS neutral regions on both sides
of the junction
VD ID CD = Cj + Cd
-
Non-linear
current source
ID = IS exp[VD/nφT ] – 1
n is called the emission co-efficient = 1 for most common
diodes but can be greater than 1 for others
Secondary Effects
0.1
Reverse bias increases
electric field across the
junction and carriers
crossing the junction get
ID (A)
accelerated and attain

0
high velocity.
At E=Ecrit = 2x105 V/cm,
carriers create e-h pairs
on collision with immobile
Si atoms. These carriers
–0.1 in turn create more
–25.0 –15.0 –5.0 0 5.0 carriers….
VD (V)
Avalanche Breakdown

SPICE Parameters

MOS Transistors -
Types and Symbols
D D
NMOS G G B
S S
NMOS with
Body Contact
D
For NMOS: Body tied to Gnd

PMOS G
For PMOS: Body tied to Vdd
Why?
S

MOS Transistor
Important transistor physical characteristics
Channel length L
Channel width W
Thickness of oxide tox
W
tox

MOS Transistor Operation
Simple case: VD = VS = VB = 0
Operates as MOS capacitor
When VGS<VT0 (but positive) , depletion region forms
No carriers in channel to connect S and D
VT0 is known as the threshold voltage
Vg < VT0
Vs=0 Vd=0
depletion
source drain region
P-substrate
VB = 0
MOS Transistor Operation
When VGS > VT0, inversion layer forms
Source and drain connected by conducting n-
type layer (for NMOS)
Vg > VT0
Vs=0 Vd=0
depletion
source drain region
P-substrate
inversion VB = 0
layer
Physical Parameters that Affect VT0
Threshold voltage (VT0): voltage between
gate and source required for inversion
NMOS Transistor is “off” when VGS < VT0
Components:
Work function difference between gate and
channel (Flat-band voltage)
Gate voltage to change surface potential
Gate voltage to offset depletion region charge
Gate voltage to offset fixed charges in gate oxide
and in silicon-oxide interface

Threshold voltage, summary
If VSB = 0 (no substrate bias):
QB 0 Qox
VT 0 = Φ GC − 2φ F − −
Cox Cox
If VSB ≠ 0 (non-zero substrate bias)

VT = VT 0 + γ ( − 2φ F + VSB − 2φ F )
Body effect (substrate-bias) coefficient:
2qN Aε Si
γ= + for NMOS
Cox - for PMOS
Threshold voltage increases as VSB increases!

Threshold Voltage (NMOS vs. PMOS)
NMOS PMOS
Substrate Fermi potential φF < 0 φF > 0
Depletion charge density QB < 0 QB > 0
Substrate bias coefficient γ>0 γ<0
Substrate bias voltage VSB > 0 VSB < 0
Threshold voltage VT0 > 0 VT0 < 0

(enhancement devices)

Threshold voltage adjustment
Threshold voltage can be changed by doping the
channel region with donor or acceptor ions
For NMOS:
VT increased by adding acceptor ions (p-type)
VT decreased by adding donor ions (n-type)
Opposite for PMOS
Approximate change in VT0:
Density of implanted ions = NI [cm-2]
Assume all implanted impurities are ionized
qN I
∆VT 0 =
Cox
Example: VT0 Adjustment
Consider an NMOS device:
P-type substrate: NA = 2 x 1016 cm-3
Polysilicon gate: ΦGC = -0.92V
tox = 600 Å (1Å = 1 x 10-8 cm)
Nox = 2 x 1010 cm-2
εSi = 11.7 ε0, εox = 3.97 ε0
(a) Find VT0
(b) Find amount and type of channel implant to get

VT0 = 0.4 V

The Body Effect
0.9
0.85
0.8
0.75
0.7
V (V)
0.65
T
0.6
0.55
0.5
0.45
0.4
-2.5 -2 -1.5 -1 -0.5 0
V (V)
BS

Transistor Currents (NMOS)
Cutoff Region: Ids = 0, Vgs<Vt
Ids= Qchannel /carrier velocity(v)

v = µE
Linear Region: Vgs> Vt, Vds< Vgs-Vt E = Vds/L
Ids = µ Cox W/L (Vgs-Vt-Vds/2)Vds β = µ Cox W/L
Saturation Region: Vgs>Vt, Vds > Vgs – Vt

Ids = β/2 (Vgs-Vt)2
Note: for PMOS Vtp = Vtn

µp < µn, hence (W/L)PMOS ~ 2 (W/L)NMOS
NMOS Characteristics
Quadratic
Relationship

PMOS Characteristics

Channel Length Modulation
In saturation, pinch-off point moves
As VDS is increased, pinch-off point moves closer to source
Effective channel length becomes shorter
Current increases due to shorter channel
L = L − ∆L
'
I D = µ nCox (VGS − VTN ) (1 + λVDS )

1 W 2
2
L
λ = channel length modulation coefficient
Summary: MOS I/V
I/V curve for NMOS device:
VDS = VGS-VT
VGS3
with channel-length
Linear VGS2
Drain current IDS
modulation
without channel-
VGS1 length modulation
(λ=0)
Saturation
Drain voltage VDS

Current-Voltage Relations
Short-Channel Transistors
-4
x 10
2.5
VGS= 2.5 V
Early Saturation
2
VGS= 2.0 V
1.5
ID (A)
Linear
1
VGS= 1.5 V Relationship
0.5 VGS= 1.0 V
0
0 0.5 1 1.5 2 2.5
VDS (V)

Velocity Saturation
υ n (m/s)
υsat = 105
Constant velocity
Constant mobility (slope = µ)
ξc = 1.5 ξ (V/µm)
Perspective
ID
Long-channel device
VGS = VDD
Short-channel device
V DSAT VGS - V T VDS

ID versus VGS
-4
x 10 x 10
-4
6 2.5
5
2
4 linear
quadratic 1.5
ID (A)
ID (A)
3
1
2
0.5
1
quadratic
0 0
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5
VGS(V) VGS(V)
Long Channel Short Channel

ID versus VDS
-4 -4
x 10 x 10
6 2.5
VGS= 2.5 V
VGS= 2.5 V
5
2
Resistive Saturation
4 VGS= 2.0 V
VGS= 2.0 V 1.5
ID (A)
ID (A)
3
VDS = VGS - VT 1 VGS= 1.5 V
2
VGS= 1.5 V
0.5 VGS= 1.0 V
1
VGS= 1.0 V
0 0
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5
VDS(V) VDS(V)
Long Channel Short Channel

Simple Model versus SPICE
-4 VDSAT = L vsat/µn
x 10
2.5
VDS=VDSAT
2
Velocity
1.5
Saturated
ID (A)
Linear
1
VDSAT=VGT
0.5
VDS=VGT
Saturated
0 Spice
0 0.5 1 1.5 2 2.5
VDS (V)
A PMOS Transistor (short-channel)
-4
x 10
0
VGS = -1.0V
-0.2
VGS = -1.5V
-0.4
ID (A)
VGS = -2.0V
-0.6 Assume all variables
negative!
-0.8
VGS = -2.5V
-1
-2.5 -2 -1.5 -1 -0.5 0
VDS (V)

Dynamic Behavior of MOS Transistor
G
Oxide Capacitance
Gate to Source overlap CGS CGD
Gate to Drain overlap S D
Gate to Channel/Bulk
CSB CGB CDB
Junction Capacitance
Source to Bulk junction B
Drain to Bulk junction

Oxide capacitances
Overlap
source Ldrawn
drain
XD
Overlap capacitances
gate electrode overlaps source and drain regions
XD is overlap length on each side of channel
Leff = Ld – 2XD
Total overlap capacitance:
Coverlap = CGSO + CGDO = 2CoxWX D

Oxide capacitances
Channel
Channel capacitances Cgs Cgd

source drain
Gate-to-source: Cgs Cgb
Gate-to-drain: Cgd
Gate-to-bulk: Cgb
Cutoff:
No channel connecting source and drain
Cgs = Cgd = 0
Cgb = CoxWLeff
Total channel capacitance CGC = CoxWLeff

Oxide capacitances
Channel
Linear mode
Channel spans from source to drain
Capacitance split equally between S and D
1 1
CGS = C oxWLeff
2
CGD = C oxWLeff
2
CGB = 0
– Total channel capacitance CGC = CoxWLeff
Saturation mode
– Channel is pinched off:
CGD = 0
2
CGS = C oxWLeff CGB = 0
3
– Total channel capacitance CGC = 2/3 CoxWLeff

Gate-to-Channel Capacitance
(summary)
G G G
CGC CGC CGC

S D S D S D
Cut-off CGC = CResistive

gb + Cgs + Cgd Saturation
Resistive

Gate-to-Channel Capacitance
CG C
WLC ox WLC ox CG C
2WLC ox
CG CS 3
WLC ox C G CS = CG CD WLC ox
CGC B
2 2 CGCD
VG S 0 VDS /( VG S-VT) 1
VT
Capacitance as a function of VGS Capacitance as a function of the

(with VDS = 0) degree of saturation
Bottom Line: Cap. components are non-linear

Diffusion Capacitance
Channel-stop implant
N A+
Side wall
Source
W
ND
Bottom
xj Side wall
Channel
LS Substrate N A

Junction Capacitance

Linearizing the Junction Capacitance
Replace non-linear capacitance by
large-signal equivalent linear capacitance
which displaces equal charge
over voltage swing of interest

Capacitances in 0.25 µm CMOS
process

Data Dependency

MOS Cap. Summary

Alpha-Power MOSFET Model
Ids ∝ (Vgs – Vt)α
1<α<2

Subthreshold Leakage
• Dominant leakage
mechanism
• Increases exponentially
with temperature and Vt

Gate Leakage
•Increases with gate oxide

(SiO2) scaling
•High-k gate oxides can be used
to lower gate leakage
•Independent of temperature

Junction Leakage
•Less significant than gate and subthreshold leakage

•Increases with temperature

Temperature Effects
•Mobility decreases with
increase in T
•Vt decreases linearly with T

Temperature Effects

Temperature Effects
Chip Cooling can:

1. Improve Circuit performance
• speed up transistors
• decrease the delay of interconnects since metal resistance
decreases with temperature
• Lowers junction capacitance (increases depletion width)
2. Decrease leakage (mainly subthreshold)

3. Improve reliability of the chip

The Sub-Micron MOS Transistor
Threshold Variations
Subthreshold Conduction/Leakage
Parasitic Resistances

Threshold voltage variation
Until now, threshold voltage assumed constant
VT changed only by substrate bias VSB
In threshold voltage equations, channel depletion
region assumed to be created by gate voltage only
Depletion regions around source and drain
neglected: valid if channel length is much larger than
depletion region depths
In short-channel devices, depletion regions from
drain and source extend into channel

Short-channel effects cause threshold voltage variation:
VT rolloff
As channel length L decreases, threshold voltage decreases
Drain-induced barrier lowering
As drain voltage VDS increases, threshold voltage decreases
Hot-carrier effect
Threshold voltages drift over time
Negative-Bias Temperature Instability (NBTI)
Issue in PMOS transistors
Vt drifts over time
Typical stress temperature 100-150 C
Typical oxide electric fields of 5-6 MV/cm

N+ N+ Drain
source drain depletion
Source
depletion region
region Gate-induced
depletion region
Even with VGS=0, part of channel is already

depleted
Bulk depletion charge is smaller in short-
channel device → VT is smaller
Change in VT0:
xdS, xdD: depth of depletion regions at S, D
xj: junction depth
1 x j ⎡⎛⎜ 2 xdS ⎞ ⎛ 2 x ⎞⎤
∆VT 0 = 2qε Si N A 2φ F • ⎢ 1+ −1⎟ + ⎜ 1+ dD
− 1 ⎟⎥
Cox 2 L ⎢⎜⎝ xj ⎟ ⎜
⎠ ⎝ xj ⎟⎥
⎠⎦
⎣
• ∆VT0 is proportional to (xj/L)

– For short channel lengths, ∆VT0 is large
– For large channel lengths, term approaches 0

Threshold voltage variations
Graphically: VT0 versus channel length L
VT0 Long-channel VT
Lnom L
VT Roll-off:
VT decreases rapidly with channel length

DIBL
Drain-induced barrier lowering (DIBL)
Drain voltage VDS causes change in threshold voltage
As VDS is increased, threshold voltage decreases
Cause: depletion region around drain
Depletion region depth around drain depends on drain
voltage
As VDS is increased, drain depletion region gets deeper and
extends further into channel
For very large VDS, source and drain depletion regions can
meet → punch-through!
Issue: results in uncertainty in circuit design

Threshold Variations
VT VT
Long-channel threshold Low VDS threshold
VDS
L
Threshold as a function of Drain-induced barrier lowering (DIBL)

the length (for low VDS ) (for low L)

Hot-carrier effect
increased electric fields causes increased
electron velocity
high-energy electrons can tunnel into gate
oxide
This changes the threshold voltage
(increases VT for NMOS)
Can lead to long-term reliability problems

Hot electrons
High-velocity electrons can also impact the drain,
dislodging holes
Holes are swept towards negatively-charged
substrate → cause substrate current
Called impact ionization
This is another factor which limits the process
scaling → voltage must scale down as length
scales

Threshold voltage variations
Summary of threshold variations in short-

channel devices
VT rolloff: threshold voltage reduces as channel
length L reduces
DIBL: threshold voltage reduces as VDS increases
Hot-carrier effect: threshold voltage drifts over time
as electrons tunnel into oxide
NBTI—causes Vt increase in PMOS transistors,
strong dependence on Temperature.

Sub-threshold conduction (1)
When VGS < VT, transistor is “off”
However, small drain current ID still flows
Called subthreshold leakage current
Model for subthreshold current: q
( AVGS + BVDS )
I D ( subthreshold ) = I SWe kT
Increases as VGS increases (potential barrier lowered)

Increases as VDS increases (DIBL)

Sub-Threshold Conduction (2)
-2
10 The Slope Factor
Linear qVGS
CD
, n = 1+
-4 nkT
10 I D ~ I 0e
Cox
-6
10 Quadratic
S is ∆VGS for ID2/ID1 =10
ID (A)
-8
10
-10 Exponential
10
-12
VT Typical values for S:
10
0 0.5 1 1.5 2 2.5 60 .. 100 mV/decade
VGS (V)

Sub-Threshold ID vs VGS
qVGS
⎛ qV
− DS ⎞
I D = I 0e nkT ⎜1 − e kT ⎟
⎜ ⎟
⎝ ⎠
VDS from 0 to 0.5V

Sub-Threshold ID vs VDS
qVGS
⎛ qV
− DS ⎞
I D = I 0e nkT ⎜1 − e kT ⎟(1 + λ ⋅ VDS )
⎜ ⎟
⎝ ⎠
VGS from 0 to 0.3V

Leakage
Effect of leakage current
“Wasted” power: power consumed even when
circuit is inactive
Leakage power raises temperature of chip
Can cause functionality problem in some circuits:
memory, dynamic logic, etc.
Reducing transistor leakage
Long-channel devices
Small drain voltage
Large threshold voltage VT

Leakage
Leakage vs. performance tradeoff:
For high-speed, need small VT and L
For low leakage, need high VT and large L
Process scaling
VT reduces with each new process (historically)
Leakage increases ~10X!
One solution: dual-VT process
Low-VT transistors: use in critical paths for high
speed
High-VT transistors: use to reduce power

Latchup
CMOS process contains parasitic bipolar transistors
Under certain conditions, these parasitic transistors
can turn on, shorting power and ground rails and
usually destroying the chip → latchup
Avoiding latchup requires certain layout design rules,
and careful control of process
Latchup was a major problem in early CMOS
processes
Now, latchup is mainly issue for I/O circuits, with high
current demands and possibly noisy voltages

Latchup
substrate tap
n-well tap
NMOS PMOS
Current flowing in well or substrate can forward-bias bipolar

transistor
Positive feedback between transistors: when one turns on, Vdd
and Gnd are connected
Solution: reduce Rnwell and Rpsubs: use many substrate taps in
layout
High-current circuits use guard rings
Parasitic Resistances
Polysilicon gate
Drain
contact
G LD
VGS,eff
W
S D
RS RD
Drain
Problem can be alleviated by silicided

source/drain contacts

© Digital Integrated Circuits2nd
Future Perspectives……
25 nm FINFET MOS transistor (Berkeley)

© Digital Integrated Circuits2nd

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ECE 225

High-Speed Digital IC Design

Prof. Kaustav Banerjee

Lecture 3, ECE 225 Kaustav Banerjee

Cross-section of pn-junction in an IC process

Mostly occurring as parasitic element in Digital ICs

Lecture 3, ECE 225 Kaustav Banerjee

Ideal diode equation:

series resistance due to the

accelerated and attain

Lecture 3, ECE 225 Kaustav Banerjee

Lecture 3, ECE 225 Kaustav Banerjee

For NMOS: Body tied to Gnd

Lecture 3, ECE 225 Kaustav Banerjee

Lecture 3, ECE 225 Kaustav Banerjee

Lecture 3, ECE 225 Kaustav Banerjee

 If VSB ≠ 0 (non-zero substrate bias)

 Threshold voltage increases as VSB increases!

Substrate Fermi potential φF < 0 φF > 0

Depletion charge density QB < 0 QB > 0

Substrate bias coefficient γ>0 γ<0

Substrate bias voltage VSB > 0 VSB < 0

Threshold voltage VT0 > 0 VT0 < 0

Lecture 3, ECE 225 Kaustav Banerjee

 (a) Find VT0

 (b) Find amount and type of channel implant to get

Lecture 3, ECE 225 Kaustav Banerjee

Lecture 3, ECE 225 Kaustav Banerjee

Ids= Qchannel /carrier velocity(v)

Saturation Region: Vgs>Vt, Vds > Vgs – Vt

Note: for PMOS Vtp = Vtn

Lecture 3, ECE 225 Kaustav Banerjee

Lecture 3, ECE 225 Kaustav Banerjee

I D = µ nCox (VGS − VTN ) (1 + λVDS )

Drain voltage VDS

Lecture 3, ECE 225 Kaustav Banerjee

0.5 VGS= 1.0 V

Lecture 3, ECE 225 Kaustav Banerjee

Constant mobility (slope = µ)

V DSAT VGS - V T VDS

Long Channel Short Channel

Lecture 3, ECE 225 Kaustav Banerjee

Long Channel Short Channel

Lecture 3, ECE 225 Kaustav Banerjee

Lecture 3, ECE 225 Kaustav Banerjee

 Gate to Drain overlap S D

 Drain to Bulk junction

Lecture 3, ECE 225 Kaustav Banerjee

Coverlap = CGSO + CGDO = 2CoxWX D

Lecture 3, ECE 225 Kaustav Banerjee

 Channel capacitances Cgs Cgd

Lecture 3, ECE 225 Kaustav Banerjee

Lecture 3, ECE 225 Kaustav Banerjee

CGC CGC CGC

Cut-off CGC = CResistive

Lecture 3, ECE 225 Kaustav Banerjee

Capacitance as a function of VGS Capacitance as a function of the

Bottom Line: Cap. components are non-linear

Lecture 3, ECE 225 Kaustav Banerjee

Lecture 3, ECE 225 Kaustav Banerjee

Lecture 3, ECE 225 Kaustav Banerjee

Lecture 3, ECE 225 Kaustav Banerjee

Lecture 3, ECE 225 Kaustav Banerjee

If VSB ≠ 0 (non-zero substrate bias)

Threshold voltage increases as VSB increases!

(a) Find VT0

(b) Find amount and type of channel implant to get

Gate to Drain overlap S D

Drain to Bulk junction

Channel capacitances Cgs Cgd

Even with VGS=0, part of channel is already

Summary of threshold variations in short-

Increases as VGS increases (potential barrier lowered)

Current flowing in well or substrate can forward-bias bipolar