15/2/2019 Solved: Artix configuration with JTAG serial PROM - Community Forums

Search all content

Community Forums  Forums  Programmable Devices  Configuration


 Artix configuration with JTAG serial PROM

edfield
Adventurer

02-13-2017 12:46 PM

3,523 Views
Registered: 04-01-2010

Artix configuration with JTAG serial PROM Jump to solution

Is it possible to configure an Artix in the "old-fashioned" way, using a serial PROM in series in
the JTAG chain? I cant see why not, but there doesn't seem to be any mention of this method
in any of the configuration documentation, it only talks about downloading to the FPGA via the
Platform-USB cable.

Thanks.

===================
BRING BACK WEBCASE!

 0 Kudos

 Share Reply

All forum topics  Previous Topic Next Topic 

1 Solution 

https://forums.xilinx.com/t5/Configuration/Artix-configuration-with-JTAG-serial-PROM/td-p/748588 1/10
15/2/2019 Solved: Artix configuration with JTAG serial PROM - Community Forums

drjohnsmith
Scholar

02-14-2017 09:37 AM - edited 02-14-2017 09:41 AM

6,233 Views
Registered: 07-09-2009

Re: Artix configuration with JTAG serial PROM 

Must admit I always liked the JTAG proms,

On the JTAG chain they as you say appear as parts to program / test.

and at power up the JTAG prom sends the serial date to the FPGA,

If its the proms Im thinking of from Xilinx,

The proms did use the serial link to the FPGA , SCLK , done etc to configure the FPGA

it was just that they were also on the JTAG bus so the proms themselves could be
programmed.

These are the sort of things were talking about me thinks ?

https://www.xilinx.com/support/documentation/data_sheets/ds026.pdf

any chance of a pdf of the circuit between the prom and the jtag ports of the artex ?

https://forums.xilinx.com/t5/Configuration/Artix-configuration-with-JTAG-serial-PROM/td-p/748588 2/10
15/2/2019 Solved: Artix configuration with JTAG serial PROM - Community Forums

 1 Kudo

 Share Reply

8 Replies

drjohnsmith
Scholar

02-13-2017 01:11 PM - last edited on 02-13-2017 01:21 PM by austin

3,515 Views
Registered: 07-09-2009

Re: Artix configuration with JTAG serial PROM

I can not see why not as far as the Artix is concerned,

BUT

I don't think the old Xilinx JTAG proms are made any more,

and you would need quiet a big size prom.

The way thats replaced that is to hook a SPI prom to the FPGA.

you program the SPI prom via the normal JTAG programmer on the FPGA,

its a function offered in the gui, no other user involvement needed.

Just hook he right SPI prom to the right pins of the FPGA , as per data sheet and all will work

https://forums.xilinx.com/t5/Configuration/Artix-configuration-with-JTAG-serial-PROM/td-p/748588 3/10
15/2/2019 Solved: Artix configuration with JTAG serial PROM - Community Forums

Remember : TCL can fix anything,

 0 Kudos

 Share Reply

gszakacs
Instructor

02-13-2017 02:52 PM

3,497 Views
Registered: 08-14-2007

Re: Artix configuration with JTAG serial PROM

From ug470:

Master Serial Configuration

The Master Serial configuration mode is the same as the Slave Serial configuration mode,
except that the FPGA generates the CCLK. That is, the CCLK is an output in Master serial
mode.
For the 7 series FPGAs, the Master SPI mode is the dominant configuration mode for a
low-pin count configuration from a serial-type flash device.
The 7 series FPGAs support Master Serial mode for configuration from legacy serial
PROMs (when applicable) or for custom, CPLD-based configuration state machines driven
by the FPGA CCLK.

(highlighting was mine)

The real question is why do want this? SPI flash parts are much less expensive than the Xilinx
platform flash parts, and only require a couple more pins. Using indirect programming, there is
no additional hardware required, either. If your intent is to use the absolute minimum of user I/O
for configuration, you might also look at using slave serial mode with an external device like an

https://forums.xilinx.com/t5/Configuration/Artix-configuration-with-JTAG-serial-PROM/td-p/748588 4/10
15/2/2019 Solved: Artix configuration with JTAG serial PROM - Community Forums

MCU or CPLD providing the bitstream. If your system already has an MCU, this approach
might come with no additional cost. It really depends on whether you have the spare GPIO on
the MCU and enough non-volatile memory to hold the bitstream.

-- Gabor

 0 Kudos

 Share Reply

edfield
Adventurer

02-13-2017 11:53 PM - edited 02-13-2017 11:53 PM

3,476 Views
Registered: 04-01-2010

Re: Artix configuration with JTAG serial PROM

Firstly, personally I don't want to do it this way, but my client has designed a board using this
method, and can't get it working!

Secondly, Master Serial mode is not the same as JTAG mode.

Thanks for your replies

Ed

===================
BRING BACK WEBCASE!

 0 Kudos

 Share Reply

drjohnsmith
Scholar

https://forums.xilinx.com/t5/Configuration/Artix-configuration-with-JTAG-serial-PROM/td-p/748588 5/10
15/2/2019 Solved: Artix configuration with JTAG serial PROM - Community Forums

02-14-2017 01:06 AM

3,468 Views
Registered: 07-09-2009

Re: Artix configuration with JTAG serial PROM

I feel your pain

been in similar sorts of situations,

as far as i remember,

the jtag proms are agnostic as to what FPGA they are connected to,

the particular instructions are buried in the file you program into it,

BUT

I seriously doubt if Xilinx ever qualified or specified the JTAG proms to work with Artex,

so its down to scope / logic analyser probes !

not nice I'm afraid, Hopefully its going to be a silly in the board, wrong voltage level etc,

best of luck and get back to us to tell us how you got on,

 0 Kudos

 Share Reply

https://forums.xilinx.com/t5/Configuration/Artix-configuration-with-JTAG-serial-PROM/td-p/748588 6/10
15/2/2019 Solved: Artix configuration with JTAG serial PROM - Community Forums

gszakacs
Instructor

02-14-2017 06:30 AM

3,458 Views
Registered: 08-14-2007

Re: Artix configuration with JTAG serial PROM

"Master Serial mode is not the same as JTAG mode."

Not sure what you're getting at here. Master Serial is the mode required to use a standard
configuration PROM including the latest (although still long in the teeth) Platform Flash serial
configuration devices. Those devices use JTAG to program the PROM, and it cannot be
programmed any other way. SPI flash gets programmed through the FPGA, meaning the FPGA
can also read and write the flash after it's been configured.

In any case, the most common reason for serial configuration not to work is getting the bit order
backwards. The old serial PROM and Platform flash send LSB first. SPI devices send MSB
first. Xilinx bitstreams are generated with the first bit to send in the MSB of each byte, so can
be natively programmed from SPI, but need bit reversal for the older serial configuration
devices.

If you have a JTAG connection to the board, you can read the configuration status to see if the
failure was caused by CRC error, which is typical of the failure when bits are incorrectly ordered.

-- Gabor

 1 Kudo

 Share Reply

edfield
Adventurer

02-14-2017 06:54 AM - edited 02-21-2017 04:12 AM

3,455 Views
Registered: 04-01-2010

https://forums.xilinx.com/t5/Configuration/Artix-configuration-with-JTAG-serial-PROM/td-p/748588 7/10
15/2/2019 Solved: Artix configuration with JTAG serial PROM - Community Forums

Re: Artix configuration with JTAG serial PROM

In the JTAG mode, used before the SPI interface was added, the serial JTAG prom and JTAG
fpga were connected in series in the JTAG chain. Both could be programmed directly from a
JTAG header. The FPGA would automatically reconfigure from the JTAG prom on power-up (or
Program-B), across the JTAG interface. The only configuration connections required were the
JTAG ones. CCLK and D0 were not used.

***** I got this wrong, see later!

===================
BRING BACK WEBCASE!

 0 Kudos

 Share Reply

drjohnsmith
Scholar

02-14-2017 09:37 AM - edited 02-14-2017 09:41 AM

6,234 Views
Registered: 07-09-2009

Re: Artix configuration with JTAG serial PROM 

Must admit I always liked the JTAG proms,

On the JTAG chain they as you say appear as parts to program / test.

and at power up the JTAG prom sends the serial date to the FPGA,

If its the proms Im thinking of from Xilinx,

The proms did use the serial link to the FPGA , SCLK , done etc to configure the FPGA

https://forums.xilinx.com/t5/Configuration/Artix-configuration-with-JTAG-serial-PROM/td-p/748588 8/10
15/2/2019 Solved: Artix configuration with JTAG serial PROM - Community Forums

it was just that they were also on the JTAG bus so the proms themselves could be
programmed.

These are the sort of things were talking about me thinks ?

https://www.xilinx.com/support/documentation/data_sheets/ds026.pdf

any chance of a pdf of the circuit between the prom and the jtag ports of the artex ?

 1 Kudo

 Share Reply

edfield
Adventurer

02-15-2017 12:13 AM

3,424 Views
Registered: 04-01-2010

Re: Artix configuration with JTAG serial PROM

Well it looks like my ageing memory might be playing tricks on me. I was convinced that JTAG
mode (mode pins usually=101) only used the JTAG connections. Somewhere in the
documentation it states that setting this mode DISABLES all other modes. However, I've been
totally unable to find an example of using this mode to configure from a PROM, only from the
JTAG header.

https://forums.xilinx.com/t5/Configuration/Artix-configuration-with-JTAG-serial-PROM/td-p/748588 9/10
15/2/2019 Solved: Artix configuration with JTAG serial PROM - Community Forums

So, my apologies, it looks like the answer to my original question is NO, you cant configure an
Artix from a PROM in JTAG mode, and you never could for any other devices either! Its JTAG
for programming, Master Serial for configuration.

I think I've persuaded my client to modify their boards to use Master Serial anyway. Much more
sensible.

===================
BRING BACK WEBCASE!

 1 Kudo

 Share Reply

© Copyright 2018 Xilinx Inc.

PRIVACY
TRADEMARKS
LEGAL
FEEDBACK
SUPPLY CHAIN TRANSPARENCY

https://forums.xilinx.com/t5/Configuration/Artix-configuration-with-JTAG-serial-PROM/td-p/748588 10/10