Documenti di Didattica
Documenti di Professioni
Documenti di Cultura
strictly use the tools associated with analog circuit design and digital design. All the
Cadence design tools are managed by a software package called the Design Framework II.
This program supervises a common database which holds all circuit information including
schematics, layouts, and simulation data.
Using the LINUX operating system is similar to using other operating systems such
as DOS. LINUX commands are issued to the system by typing them in a “shell”. LINUX
commands are case sensitive so be careful when issuing a command, usually they are given
in lower-case.
The following list summarizes all the basic commands required to manage the data
files you will be creating in this lab course. All LINUX commands are entered from the
shell window (Terminal window).
Caution: Do not use LINUX commands for modifying, deleting, or moving any Cadence
data files.
Commands Description
Lists files in the current directory. ”l” lists with properties and “a”
ls [–la]
also lists hidden files (ones beginning with a “.”).
mv XXXX YYYY Moves file XXXX to YYYY. Also used for rename
ANALOG DESIGN
>virtuoso &
The virtuoso or Command Interpreter Window (CIW) appears at the bottom of
the screen.
3. If the “What’s New…” window appears, close it with the File-Close command.
4. Keep opened CIW window for the labs.
1. In the CIW window click on Tools-Library manager. The library manager window
will be opened.
2. Click File-New-Library. Specify the name for the new library. Click ok.
3. In the next “Technology File for New Library” form, select option Attach an
existing techfile and click ok.
4. In the “Attach Design Library to technology file” form, select gpdk180 from the
cyclic field and click ok
5. After creating a new library you can verify it from the Library manager.
1. In the design window click the Instance fix menu icon to display add instance form.
2. Click on the browse button. This opens up a library browser from which you can
select the components and the symbol view.
3. After you complete the add instance form, move your cursor to the schematic
window and click left to place a component. If you place a component with wrong
parameter values, use the Edit-Properties-Objects command to change the
parameter. Use Edit-Move command if you place components in the wrong
location. You can rotate components using Edit-Rotate command.
4. After entering components, click cancel in the Add instance form or press Esc.
Symbol Creation:
Editing a Symbol:
1. Move the cursor over the automatically generated symbol, until the green rectangle
is highlighted, click left to select it.
2. Click Delete icon in the symbol window, similarly select the red rectangle and delete
that.
3. Execute Create-Shape-Polygon.
4. After creating the shape press ESC key.
5. You can move the pin names according to the location.
6. Execute Create-Selection Box. In the Add Selection Box form, click Automatic. A
new red selection box is automatically added.
7. After creating symbol, click on the save icon in the symbol editor window to save
the symbol. In the symbol editor, execute File-Close to close the symbol view
window.
Simulation with Spectre:
5. Click the Browse button to add gpdk.scs if not added by default as shown in the
Model Library setup form, remember to select the section type as start in front of
gpdk.scs file. Click ok.
6. Click the Choose- Analysis icon .
7. To setup for transient analysis select tran icon, click at the moderate or enabled
button at the bottom, click Apply.
8. To setup for DC analysis select dc, turn on Save Dc Operating Point. Turn on the
Component Parameter. Click the select Component, which takes you to the
schematic window. Select input signal, Vpulse or DC analysis. Select start and stop
voltages. Click Apply and ok.
1. In the simulation window, execute Session- Save State. Set the Save as field and
click ok.
2. In the simulation window execute Session- Load State, set the state name and click
ok.
1. From the schematic window menu execute Launch- Layout XL. A startup Option
form appears.
2. Select Create New option.
3. Check the cell name, View name. Click ok.
Making Interconnection:
Creating Contacts/Vias:
Running DRC:
1. Select Assura-Run DRC from Layout window. The DRC form appears. The
Library and cell name are taken from the current design window, but rule file may be
missing. Select the technology as gpdk180. This automatically loads the rule file.
2. Click ok to start DRC. A progress form will appear. You can click on the watch
clock file to see the Log file.
3. When DRC finishes, a dialog box appears, Click Yes to view the results.
4. If there are any DRC error exits in the design View Layer Window (VLW) and
Error Layer Window (ELW) appears. Also the errors highlight in the design itself.
5. Click View- Summary in the ELW to find the details of errors.
6. You can refer to rule file also for more information, correct all DRC errors and Re –
run the DRC.
7. If there are no errors in the layout then a dialog box appears with No DRC errors
found written in it, Click on close to terminate the DRC run.
ASSURA LVS:
1. Select Assura-Run LVS from the layout window. The Assura Run LVS form
appears, it will automatically load both the schematic and layout view of the cell.
2. Click OK. The LVS begins and a progress form appears.
3. If the schematic and layout matches completely, you will get the form displaying
Schematic and Layout Match.
4. If the schematic and Layout do not matches, a form informs that the LS completed
successfully and results form will appear, click YES in the form.
5. In the LVS debug form, find the details of mismatches and correct all those
mismatches and Re-Run the LVS.
ASSURA RCX:
Configuration View:
6. In the CIW, note the netlisting statistics in the circuit inventory section. This list
includes all nets, design devices, source and loads. There are no parasitic
components.
DIGITAL DESIGN
1. Login to your workstation using the username and password.
The home directory has a cshrc file with paths to the cadence installation.
2. In a terminal window, type csh at the command prompt to invoke C shell.
> csh
> cd cadence_db
> source cshrc_client
> cd Cadence_digital_labs
> cd Workarea
3. Create the directory by USN using a command mkdir USN
4. Enter the directory by using a command cd USN.
5. Create a new directory for each program using command mkdir programname.
6. Enter to the program directory using command cd programname.
7. Create a file to write a code using command vi filename.v Ex: vi inverter.v
8. Create a file to write a testbench using command vi filename_t.v Ex: vi inverter_t.v
9. Use :wq command to save and exit the file.
10 Create the local library directory. Ex mkdir design.lib
11 Create the cds.lib(vi cds.lib) file and make the following entry.
Ex: Define design_lib ./design.lib
12 Create the hdl.var file and make the following entry.
Ex: Define WORK design_lib
Define NCELABOPTS -messages
13. Compile the code using ncvlog filename.v –MESS. Ex: ncvlog inverter.v –MESS
14. Compile the test bench using ncvlog filename_t.v –MESS.
Ex: ncvlog inverter_t.v –MESS
15. Elaborate the testbench once again to place the testcode and snapshot in local library
using command ncelab topmodulename(of test bench) –access +rwc -MESS.
16. Simulate the testbench with gui option: ncsim topmodulename(of test bench) –gui.
17. Once the simulation is done see the waveform window and console window with the
outputs.
1. Move into the rclabs directory inside the Workarea using the command –
cd Cadence_digital_labs/Workarea/rclabs
2. There will be four directories inside rclabs namely – library , rtl , tcl and work , as shown
cd rtl
3. Inside rtl directory, copy the verilog program which has to be synthesized, using the
command –
cp ../../Design1/Codefile1.v Codefile1.v
e.g cp ../../USN/programmename/inverter.v inverter.v
This is required because the synthesis is performed only on the design file, and not on the
test bench. Now, edit the program file and delete all of the compiler directives which are
present in the program file (the commands preceded by `).
As the next step, if switch primitives are present in the program, then they have to be
replaced by the RTL description, because of the fact that, the switch primitives are not
synthesizable. The output of synthesis is a schematic using logic gates. This is called as
“logic synthesis”, which is technology independent.
cd ../
cd tcl
6. Inside tcl directory there is a file named setup.g . Open this file using the command –
8. Next, enter into the directory work . Create a file named Contraints_file.g . The timing
constraints are defined in this file. Example of one such file is as shown –
set_input_delay -max 1.0 [get_ports " A"] -clock [get_clocks " clk "] Input port delay
set_input_delay -max 1.0 [get_ports " B"] -clock [get_clocks " clk "] Input port delay
The port names that are used in the constraint file (bolded) must match with the names that
are used in the Verilog program of the main design module. The constraints are defined for
all the ports in the design.
The tool will be invoked and you will get the rc prompt in the terminal, along with a
synthesis window. Next, the following commands are to be typed in the rc prompt –
1. include ../tcl/setup.g
2. set_attribute library $LIBRARY
3. set SYN_EFF medium
4. set MAP_EFF medium
5. read_hdl $FILE_LIST
6. elaborate $DESIGN
7. read_sdc ./Constraints_file.g
8. synthesize -to_generic -eff $SYN_EFF
9. report timing
10. report area
11. report power
11. The tool will execute each command as and when it is entered. To come out of the
synthesis environment, exit or quit command in the rc prompt is used.
12. The commands of step-10 can be saved in a .tcl file in the work directory, and that
script file can be invoked in the rc prompt, by using the include command. Optionally, the
synthesis can be performed by going to the GUI window and clicking on File, and then
clicking on Source Script, and then selecting the respective script file.
NOTES
1. Linux commands:
2. Command options:
LAB 1: INVERTER
Objective: To design an Inverter with given specifications and verifying the following
1. Schematic:
i) DC Analysis ii) Transient Analysis
2. Layout:
i) DRC ii) LVS iii) RCX
Design:
Saturation
Device Cutoff Non saturation
Vgsp>Vtp Vgsp<Vtp Vgsp<Vtp
Vin < Vtp+Vdd Vin<Vtp+Vdd
P device
Vin > Vtp+Vdd Vdsp>Vgsp-Vtp Vdsp<Vgsp-Vtp
Vout> Vin-Vtp Vout<Vin-Vtp
Vgsn<Vtn Vgsn>Vtn Vgsn>Vtn
Vin> Vtn Vin>Vtn
n device
Vin<Vtn Vdsn<Vgs-Vtn Vdsn>Vgs-Vtn
Vout<Vin-Vtn Vout>Vin-Vtn
Inverter Schematic:
Specifications:
Inverter_test Schematic:
Specifications:
Analysis Values
Transient Stop time = 200ns
Dc Start time =0, stop time =2.
Result
Inverter Layout:
1. Schematic:
i) DC Analysis ii) AC Analysis iii) Transient Analysis
2. Layout:
i) DRC ii) LVS iii) RCX
Design:
r01 || r02
=-
1
gm1
CS Amplifier Schematic:
Specifications:
Library name Cell name Properties Pin Names Direction
gpdk180 pmos W=50µ, L=1µ vin vbias Input
gpdk180 nmos W=10µ, L=1µ vout Output
vdd vss Input
CS Amplifier_test Schematic:
Specifications:
Library name Cell name Properties
AC Magnitude=1, Amplitude=5m,
analoglib Vsin Frequency=1k, offset voltage=0, DC
voltage=0
For Vdd: DC voltage =2.5,
For Vss: DC voltage ==-2.5
analoglib Vdc,Vdc,Vdc
For Vbias: DC voltage ==2.5
analoglib gnd -
Analysis Values
Transient Stop time = 5ms
Dc Start time = -5, stop time = 5.
Ac Start time= 100, stop time= 100M, Points per decade = 20.
Result
CS Amplifier Layout:
1. Schematic:
i) DC Analysis ii) AC Analysis iii) Transient Analysis
2. Layout:
i) DRC ii) LVS iii) RCX
Design:
I1=0;
I2= - gm1 Vgs1 +(gmb1+gds1)Vo
gm1
Av=
gm1 + gmb1 + gds1 + gds 2
CD Amplifier Schematic:
Specifications:
Library name Cell name Properties Pin Names Direction
gpdk180 nmos W=50µ, L=1µ vin vbias Input
gpdk180 nmos W=10µ, L=1µ vout Output
vdd vss Input
CD Amplifier_test Schematic:
Specifications:
Analoglib gnd -
Analysis Values
Transient Stop time = 5ms
Dc Start time = -5, stop time = 5.
Ac Start time= 100,stop time= 100M,points per decade = 20.
CD Amplifier Layout:
1. Schematic:
i) DC Analysis ii) AC Analysis iii) Transient Analysis
2. Layout:
i) DRC ii) LVS iii) RCX
Design:
1 2
rout = or
gds 2 + gds 4 (λ n + λ p ) I 5
gmd
Av =
gds 2 + gds 4
(W/L) 1= (W/L) 2
k '1 Iss w1 / l1
Av =
(λ 2 + λ 4 )( Iss / 2)
(W/L) 3 = (W/L) 4
2I 5
Vgs3 = + Vtn
k ' p (w / l ) 3
2I 5
(W/L) 5 = 2
k ' n Vds5 ( sat )
Vds 5 (sat) = V Ic min – Vss – Vgs1
Specification:
Library
Cell name Properties
name
Model name(NM0, NM1);
gpdk180 nmos Pin Names Direction
W=3µ, L=1µ
Idc, V1, V2 Input
Model name(NM2, NM3);
gpdk180 nmos vout Output
W=4.5µ, L=1µ
Model name(PM0, PM1); vdd vss InputOutput
gpdk180 pmos
W=15µ, L=1µ
Analysis Values
Transient Stop time = 5ms
Result
1. Schematic:
i) DC Analysis ii) AC Analysis iii) Transient Analysis
2. Layout:
i) DRC ii) LVS iii) RCX
Design:
2
W gm1
( )1 =
L k '1 I 5
Where I5 = SR (Cc), gm1 = GB (Cc), Cc= (2.2/10)CL
W I5
( )3 =
L k '3 [Vdd − Vin(max)− | Vto3 | (max) + Vt1 (min)]2
W 2I 5
( )5 =
L k '5 (Vds 5 ) 2
Vds5 = Vin (min) – Vss - √ I5/β1 –Vt1 (max)
W gm6
( )6 =
L k ' 6 Vds 6 ( sat )
gm6 = 2.2(gm2)(CL/Cc)
W W I
( )7 = ( )5 ( 6 )
L L I5
2 gm2 gm6
Av =
I 5 (λ 2 + λ 4 ) I 6 (λ 6 + λ 7 )
OP-AMP Schematic:
Specifications:
OP-AMP_test Schematic:
Specifications:
Library name Cell name Properties
AC Magnitude=1, Amplitude=5µ,
analoglib Vsin
Frequency=1k, offset voltage=0, DC voltage=0
For Vdd: DC voltage =2.5,
analoglib Vdc,Vdc
For Vss: DC voltage ==-2.5
analoglib gnd -
analoglib Idc DC Current=30µ
Analysis Values
Transient Stop time = 5ms
Dc Start time = -5, stop time = 5.
Ac Start time= 100,stop time= 100M,points per decade = 20.
OP-AMP Layout:
1. Schematic:
i) DC Analysis ii) AC Analysis iii) Transient Analysis
2. Layout:
i) DRC ii) LVS iii) RCX
analoglib gnd -
Analysis Values
Transient Stop time = 300ns
Result
DIGITAL DESIGN
LAB 1: INVERTER
Objective: To Compile and simulate the Verilog Code for an inverter circuit and observe
the waveform.
Inverter:
`resetall
`timescale 1 ns / 1 ns
`view vlog
output out;
input in;
supply1 pwr;
supply0 gnd;
pmos (out,pwr,in);
nmos (out,gnd,in);
endmodule
`noview
Inverter_test:
`resetall
`timescale 1 ns / 1 ns
`view vlog
module inv_test;
wire out ;
reg in ;
inverter i ( out, in ) ;
`nouselib
// Display
task display ;
begin
$display ( "time=%0d" , $time , " ns" , " Input=" , in , " Output=", out ) ;
end
endtask
// Apply Stimulus
initial
begin
in = 1'b0 ; #10 ; display ;
in = 1'b1 ; #10 ; display ;
in = 1'bx ; #10 ; display ;
in = 1'bz ; #10 ; display ;
end
endmodule
`noview
Note: The task “display” is used to display the output on the monitor, in the form of a truth
table. For observing the waveforms, the Simvision tool can be invoked.
Truth Table
Input Output
A Y
0 1
1 0
X X
Z X
Result
For synthesis, follow the steps that are mentioned previously. After synthesis, the synthesis
window will be shown as follows –
LAB 2: BUFFER
Objective: To write Verilog Code for the Buffer circuit and Test Bench for
Verification, observe the waveform.
Buffer:
`resetall
`timescale 1 ns / 1 ns
`view vlog
module inverter( Y, A );
output Y;
input A;
supply1 pwr;
supply0 gnd;
pmos (Y,pwr,A);
nmos (Y,gnd,A);
endmodule
output out;
input in;
// Wire Declaration
wire a;
// Instantiate Inverter module
inverter i1 (a,in);
inverter i2 (out,a);
endmodule
`noview
Buffer_test:
`resetall
`timescale 1 ns / 1 ns
`view vlog
// Testbench for Buffer Module
module buf_test;
wire out ;
reg in ;
`nouselib
// Display
task display ;
begin
$display ( "time=%0d" , $time , " ns", " Input=" , in , " Output=", out ) ;
end
endtask
// Apply Stimulus
initial
begin
in = 1'b0 ; #10 ; display ;
in = 1'b1 ; #10 ; display ;
in = 1'bx ; #10 ; display ;
in = 1'bz ; #10 ; display ;
end
endmodule
`noview
Truth Table
Input Output
A Y
0 0
1 1
X X
Z X
Result
When double-clicked inside the blocks shown, the subsystem is displayed as shown –
Objective: To write Verilog Code for the Transmission gate circuit and Test Bench
For Verification, observe the waveform.
TG:
`resetall
`timescale 1 ns / 1 ns
`view vlog
output out;
input in;
input cntrl1,cntrl2;
pmos (out,in,cntrl1);
nmos (out,in,cntrl2);
endmodule
`noview
TG_test:
`resetall
`timescale 1 ns / 1 ns
`view vlog
module trangate_test;
wire out ;
reg in ;
reg cntrl1,cntrl2;
`nouselib
// Display
task display ;
begin
$display ( "time=%0d" , $time , " ns", " Input=" , in, " Output=", out,
" Control1=",cntrl1, " Control2=",cntrl2 ) ;
end
endtask
// Apply Stimulus
initial
begin
in = 1'b0 ; cntrl1 = 1'b0 ; cntrl2 = 1'b1 ; #10 ; display ;
in = 1'b0 ; cntrl1 = 1'b1 ; cntrl2 = 1'b0 ; #10 ; display ;
in = 1'b1 ; cntrl1 = 1'b0 ; cntrl2 = 1'b1 ; #10 ; display ;
in = 1'b1 ; cntrl1 = 1'b1 ; cntrl2 = 1'b0 ; #10 ; display ;
end
endmodule
`noview
Truth Table
Input Cntrl1 Cntrl2 Output
0 0 1 0
0 1 0 Z
1 0 1 1
1 1 0 Z
Result
Objective: To write Verilog Code for the Basic/ Universal gates and Test Bench
For Verification, observe the waveform.
1) AND:
`resetall
`timescale 1 ns / 1 ns
`view vlog
// Declaration of Wires
wire contact;
wire nout
pmos (nout,pwr,in1);
pmos (nout,pwr,in2);
nmos (nout,contact,in2);
nmos (contact,gnd,in1);
pmos (out,pwr,nout);
nmos (out,gnd,nout);
endmodule
`noview
AND_test:
`resetall
`timescale 1 ns / 1 ns
`view vlog
module and_test;
wire out ;
reg in1,in2 ;
`uselib view = vlog
`nouselib
// Display
task display ;
begin
$display ( "time=%0d" , $time , " ns" ," Input1=" , in1 , " Input2=" , in2 ,
" Output=" , out ) ;
end
endtask
// Apply Stimulus
initial
begin
in1 = 1'b0 ; in2 = 1'b0 ; #10 ; display ;
in1 = 1'b0 ; in2 = 1'b1 ; #10 ; display ;
in1 = 1'b1 ; in2 = 1'b0 ; #10 ; display ;
in1 = 1'b1 ; in2 = 1'b1 ; #10 ; display ;
end
endmodule
`noview
Truth Table
Input Output
A B Y
0 0 0
0 1 0
1 0 0
Result 1 1 1
2) OR:
`resetall
`timescale 1 ns / 1 ns
`view vlog
output out;
input in1,in2;
supply1 pwr;
supply0 gnd;
// Declaration of Wires
wire contact;
wire nout;
pmos (contact,pwr,in2);
pmos (nout,contact,in1);
nmos (nout,gnd,in1);
nmos (nout,gnd,in2);
pmos (out,pwr,nout);
nmos (out,gnd,nout);
endmodule
`noview
OR_test:
`resetall
`timescale 1 ns / 1 ns
`view vlog
// Testbench for Nor Gate Module
module or_test;
wire out ;
reg in1,in2 ;
`uselib view = vlog
`nouselib
// Display
task display ;
begin
$display ( "time=%0d" , $time , " ns" ," Input1=" , in1 , " Input2=" , in2 ,
" Output=" , out ) ;
end
endtask
// Apply Stimulus
initial
begin
in1 = 1'b0 ; in2 = 1'b0 ; #10 ; display ;
in1 = 1'b0 ; in2 = 1'b1 ; #10 ; display ;
in1 = 1'b1 ; in2 = 1'b0 ; #10 ; display ;
in1 = 1'b1 ; in2 = 1'b1 ; #10 ; display ;
end
endmodule
`noview
Truth Table
Input Output
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
Result
3) NAND:
`resetall
`timescale 1 ns / 1 ns
`view vlog
output out;
input in1,in2;
supply1 pwr;
supply0 gnd;
// Declaration of Wire
wire contact;
pmos (out,pwr,in1);
pmos (out,pwr,in2);
nmos (out,contact,in2);
nmos (contact,gnd,in1);
endmodule
`noview
NAND_test:
`resetall
`timescale 1 ns / 1 ns
`view vlog
module nand_test;
wire out ;
reg in1,in2 ;
`uselib view = vlog
`nouselib
// Display
task display ;
begin
$display ( "time=%0d" , $time , " ns"," Input1=" , in1 , " Input2=" , in2 ,
" Output=" , out ) ;
end
endtask
// Apply Stimulus
initial
begin
in1 = 1'b0 ; in2 = 1'b0 ; #10 ; display ;
in1 = 1'b0 ; in2 = 1'b1 ; #10 ; display ;
in1 = 1'b1 ; in2 = 1'b0 ; #10 ; display ;
in1 = 1'b1 ; in2 = 1'b1 ; #10 ; display ;
end
endmodule
`noview
Truth Table
Input Output
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
Result
4) NOR:
`resetall
`timescale 1 ns / 1 ns
`view vlog
output out;
input in1,in2;
supply1 pwr;
supply0 gnd;
// Declaration of Wire
wire contact;
pmos (contact,pwr,in2);
pmos (out,contact,in1);
nmos (out,gnd,in1);
nmos (out,gnd,in2);
endmodule
`noview
NOR_test
`resetall
`timescale 1 ns / 1 ns
`view vlog
module nor_test;
wire out ;
reg in1,in2 ;
`uselib view = vlog
`nouselib
// Display
task display ;
begin
$display( "time=%0d" , $time , " ns" , " Input1=" , in1 , " Input2=" , in2 ,
" Output=" , out ) ;
end
endtask
// Apply Stimulus
initial
begin
in1 = 1'b0 ; in2 = 1'b0 ; #10 ; display ;
in1 = 1'b0 ; in2 = 1'b1 ; #10 ; display ;
in1 = 1'b1 ; in2 = 1'b0 ; #10 ; display ;
in1 = 1'b1 ; in2 = 1'b1 ; #10 ; display ;
end
endmodule
`noview
Truth Table
Input Output
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
Result
`resetall
`timescale 1 ns / 1 ns
`view vlog
output out;
input in1,in2;
wire in2bar;
assign in2bar = ~in2;
pmos (out,in2bar,in1);
nmos (out,in2,in1);
pmos (out,in1,in2bar);
nmos (out,in1,in2);
endmodule
`noview
XNOR_test
`resetall
`timescale 1 ns / 1 ns
`view vlog
module xnor_test;
wire out ;
reg in1,in2 ;
`uselib view = vlog
`nouselib
// Display
task display ;
begin
$display ( "time=%0d" , $time , " ns"," Input1=" , in1 ," Input2=" , in2 ,
" Output=" , out ) ;
end
endtask
// Apply Stimulus
initial
begin
in1 = 1'b0 ; in2 = 1'b0 ; #10 ; display ;
in1 = 1'b0 ; in2 = 1'b1 ; #10 ; display ;
in1 = 1'b1 ; in2 = 1'b0 ; #10 ; display ;
in1 = 1'b1 ; in2 = 1'b1 ; #10 ; display ;
end
endmodule
`noview
Truth Table
Input Output
A B Y
0 0 1
0 1 0
1 0 0
1 1 1
Result
`resetall
`timescale 1 ns / 1 ns
`view vlog
output out;
input in1,in2;
wire in2bar;
pmos (out,in2,in1);
nmos (out,in2bar,in1);
pmos (out,in1,in2);
nmos (out,in1,in2bar);
endmodule
`noview
XOR_test:
`resetall
`timescale 1 ns / 1 ns
`view vlog
module xor_test;
wire out ;
reg in1,in2 ;
`uselib view = vlog
`nouselib
// Display
task display ;
begin
$display( "time=%0d" , $time , " ns" , " Input1=" , in1," Input2=" , in2,
" Output=" , out ) ;
end
endtask
// Apply Stimulus
initial
begin
in1 = 1'b0 ; in2 = 1'b0 ; #10 ; display ;
in1 = 1'b0 ; in2 = 1'b1 ; #10 ; display ;
in1 = 1'b1 ; in2 = 1'b0 ; #10 ; display ;
in1 = 1'b1 ; in2 = 1'b1 ; #10 ; display ;
end
endmodule
`noview
Truth Table
Input Output
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
Result
Simulation Result:
Objective: To write Verilog Code for various Flip flop circuits and Test Bench
For Verification, observe the waveform.
1) D-FF:
d q
D
module d_ff(d, rst, clk, q, qb);
clk
input d, rst, clk; FLIP-
output q, qb; rst FLOP qb
reg q,qb;
always@(posedge clk)
begin
if (rst==1)
begin
q=0;
qb=1;
end
else
begin
q=d;
qb=~d;
end
end
endmodule
D-FF_test:
module d_ff_test;
reg clk, d, rst;
wire q,qb, d1, clk1;
d_ff df1 (d, rst, clk, q, qb);
assign d1=d;
assign clk1=clk;
initial
clk = 1'b0;
always
#5 clk = ~clk;
initial
begin
d = 1'b0;
rst = 1'b1;
#30 rst = 1'b0;
#40 d = 1'b1;
#20 d = 1'b0;
#10 ;
end
specify
$setup(d1, posedge clk1, 2);
Truth Table
RESET D Q QBAR
1 X 0 1
0 0 0 1
0 1 1 0
Result
2) JK-ff:
module jk_ff(jk, clk, rst, q, qb);
input [1:0]jk;
input clk,rst;
output q, qb;
reg q, qb;
always @ (posedge clk)
begin
if(rst==1)
begin
q=0;
qb=1;
end
else
begin
case (jk)
2'b00: begin q=q; qb=qb; end
2'b01: begin q=0; qb=1; end
2'b10: begin q=1; qb=0; end
2'b11: begin q=~(q); qb=~(qb); end
endcase
end
end
endmodule
JK-FF_test:
module jk_ff_test;
reg clk,rst;
reg [1:0] jk;
wire q,qb;
wire clk1;
wire [1:0] jk1;
jk_ff jkff(jk, clk, rst, q, qb);
assign clk1=clk;
assign jk1=jk;
initial
clk = 1'b0;
always
#5 clk = ~clk;
initial
begin
jk = 2'b00; rst = 1'b1;
#20 rst = 1'b0;
#20 jk = 2'b01;
#20 jk = 2'b10;
#20 jk = 2'b11;
#20 rst = 1'b1;
#10 ;
end
specify
$setup(j1, posedge clk1, 2);
$setup(k1, posedge clk1, 2);
$hold(posedge clk1, j1, 2);
$hold(posedge clk1, k1, 2);
endspecify
endmodule
Truth Table
RESET J K Q QBAR
1 X X 0 1
0 0 0 Q QBAR
0 0 1 0 1
0 1 0 1 0
0 1 1 ~Q ~QBAR
Result
3) MS-FF:
module ms_jkff(q,q_bar,clk,j,k);
output q,q_bar;
input clk,j,k;
reg tq,q,q_bar;
always @(clk)
begin
if (!clk)
begin
if (j==1'b0 && k==1'b1)
tq <= 1'b0;
else if (j==1'b1 && k==1'b0)
tq <= 1'b1;
else if (j==1'b1 && k==1'b1)
tq <= ~tq;
end
if (clk)
begin
q <= tq;
q_bar <= ~tq;
end
end
endmodule
MS-FF_test:
module tb_ms_jkff;
reg clk,j,k;
wire q,q_bar;
wire clk2,j2,k2;
ms_jkff inst(q,q_bar,clk,j,k);
assign clk2=clk;
assign j2=j;
assign k2=k;
initial
clk = 1'b0;
always #10
clk = ~clk;
initial
begin
j = 1'b0; k = 1'b0;
#60 j = 1'b0; k = 1'b1;
#40 j = 1'b1; k = 1'b0;
#20 j = 1'b1; k = 1'b1;
#40 j = 1'b1; k = 1'b0;
#5 j = 1'b0; #20 j = 1'b1;
#10 ;
end
always
#5 $display($time," clk=%b j=%b k=%b ",clk,j,k);
initial
#200 $finish;
specify
$setup(j2, posedge clk2, 2);
$setup(k2, posedge clk2, 2);
$hold(posedge clk2, j2, 2);
$hold(posedge clk2, k2, 2);
endspecify
endmodule
Truth Table
RESET J K Q QBAR
0 X X 0 1
1 0 0 0 1
1 0 1 0 1
1 1 0 1 0
1 1 1 1 0
Result
4) T-FF:
t q
T
module t_ff(t, clk, rst, q, qb);
input t, clk, rst; clk
FLIP-FLOP
output q, qb;
reg q,qb; rst qb
always @ (posedge clk)
begin
if (rst==1)
begin
q=1’b0;
qb=1’b1;
end
else
begin
case t
1’b0:begin q=q; qb=qb; end
1’b1:begin q=~(q); qb=~(qb); end
endcase
end
end
endmodule
T-FF_test:
module t_ff_t;
reg clk,t,rst;
wire q,qb;
t_ff t1(t, clk, rst, q, qb);
initial
clk = 1'b0;
always
#10 clk = ~clk;
initial
begin
rst = 1'b1; t = 1'b0;
#30 rst = 1'b0;
#10 t = 1'b1;
#30 t = 1'b0;
#20 rst = 1'b1;
#20 ;
end
endmodule
Truth Table
RESET T Q QBAR
1 X 0 1
0 0 Q QBAR
0 1 ~Q ~QBAR
Result
RST
5) RS-FF:
module sr_ff(sr, clk, rst, q, qb);
input [1:0] sr;
input rst, clk; S Q
S-R
output q,qb;
reg q,qb; CLK
FLIP-
always @ (posedge clk)
R FLOP QBAR
begin
if (rst==1)
begin
q=0;
qb=1;
end
else
begin
case (sr)
2'b00: begin q=q; qb=qb; end
2'b01: begin q=0; qb=1; end
2'b10: begin q=1; qb=0; end
2'b11: begin q=1'bx; qb=1'bx; end
endcase
end
end
endmodule
RS-FF_test:
module sr_ff_test;
reg clk,rst;
wire q,qb;
reg [1:0] sr;
wire [1:0] sr1;
wire clk1;
sr_ff sr1(sr, clk, rst, q, qb);
assign sr1=sr;
assign clk1=clk;
initial
clk = 1'b0;
always
#5 clk = ~clk;
initial
begin
sr = 2'b00; rst=1’b1;
#30 rst =1’b0;
#30 sr = 2'b01;
#40 sr = 2'b10;
#30 sr = 2'b11;
#10 ;
end
specify
$setup(s1, posedge clk1, 2);
$setup(r1, posedge clk1, 2);
$hold(posedge clk1, s1, 2);
$hold(posedge clk1, r1, 2);
endspecify
endmodule
Truth Table
INPUTS OUTPUTS
RST S R Q QBAR
1 X X 0 1
0 0 0 Q QBAR
0 0 1 0 1
0 1 0 1 0
0 1 1 X X
Result
1) i) Parallel Adder
module adder4_t ;
reg [3:0] x,y;
reg carryin;
wire [3:0] sum;
wire carryout;
adder4 a1 ( carryin,x,y,sum,carryout);
initial
begin
x = 4'b0000; y= 4'b0000;carryin = 1'b0;
#20 x =4'b1111; y = 4'b1010;
#40 x =4'b1011; y =4'b0110;
#40 x =4'b1111; y=4'b1111;
#50 $finish;
end
endmodule
Result
//sequential block
always @(posedge clock)
if (reset)
y <= G;
else
y <= Y;
//control the shifting process
always @(posedge clock)
if (reset)
count = 8;
else if (run) count = count - 1;
assign run=|count;
endmodule
module serial_adder_t ;
reg [7:0] A,B;
reg reset,clock;
wire [7:0] sum ;
initial
clock = 1'b0;
always
#5 clock =~clock;
serial_adder s1 (A,B,reset,clock,sum);
initial
begin
reset = 1'b0;A = 8'b10101010; B = 8'b11111111;
#20 reset = 1'b1;
#20 reset = 1'b0;
#150 reset = 1'b1; A = 11110000 ; B = 8'b11110011;
#20 reset = 1'b0;
#200 $finish;
end
initial
$monitor ($time, " SUM = %d ", sum);
endmodule
parameter n=8;
input [n-1:0] R;
input L,E,w,clock;
output [n-1:0] q;
reg [n-1:0] q;
integer k;
begin
for (k=n-1;k>0;k=k-1)
q[k-1] <= q[k];
q[n-1] <= w;
end
endmodule
Result
ii)SERIAL ADDER
DESIGN CODE
module adder_serial(
input clk,rst,
input en, // on Enable, addition will start
input a, // 4-bit adder
input b,
output [3:0] result
);
reg [3:0] y;
reg carry;
always@(posedge rst or posedge clk)
begin
if (rst)
begin
y = 4'b0;
carry = 1'b0;
end
else if (en)
begin
y[3] = y[2];
y[2] = y[1];
y[1] = y[0];
{carry,y[0]} = a + b + carry;
end
end
assign result = y;
endmodule
module serial_adder_test;
reg clk,rst,en,a,b;
Wire [3:0] result;
adder_serial U1 (clk,rst,en,a,b,result); //instantiation
Initial
clk=1’b0;
always
#5 clk=~clk;
Initial
begin
Rst =1’b1;en=1’b0;a=0;b=0;
#10 Rst =1’b0;en=1’b1;a=1;b=0;
#10 Rst =1’b0;en=1’b1;a=0;b=1;
#10 Rst =1’b0;en=1’b1;a=1;b=1;
#10 Rst =1’b0;en=1’b1;a=0;b=1;
#10 Rst =1’b0;en=1’b1;a=1;b=0;
#200 $finish;
end
endmodule
Result
1) Asynchronous counter:
module counter_behav ( count,reset,clk);
input wire reset, clk;
output reg [3:0] count;
always @(posedge clk or posedge rst)
begin
if (reset)
count <= 4'b0000;
else
count <= count + 4'b0001;
end
endmodule
Asynchronous counter_test
module mycounter_t ;
wire [3:0] count;
reg reset,clk;
initial
clk = 1'b0;
always
#5 clk = ~clk;
counter_behav m1 ( count,reset,clk);
initial
begin
reset = 1'b0 ;
#15 reset =1'b1;
#30 reset =1'b0;
#300 $finish;
end
initial
$monitor ($time, "Output count = %d ",count );
endmodule
Result
2) Synchronous Counter
Synchronous counter_test
module mycounter_t ;
wire [3:0] count;
reg reset,clk;
initial
clk = 1'b0;
always
#5 clk = ~clk;
counter_behav m1 ( count,reset,clk);
initial
begin
reset = 1'b0 ;
#15 reset =1'b1;
#30 reset =1'b0;
#300 $finish;
end
initial
$monitor ($time, "Output count = %d ",count );
endmodule
Result
Aim: To compile and to simulate the Verilog code for the successive approximation
register.
Design Files:
comp = 1'b0;
else
comp = 1'b1;
end
end
endmodule
module sar_tb;
reg clk,reset,start;
reg [63:0] vref_d,vin_d;
wire done, comp;
wire [3:0] digitalout;
real vref_real = 7.5;
sar s1 (digitalout,done,comp,start,reset,clk);
dac d1 (comp,digitalout,vref_d,vin_d,clk,start);
initial
begin
clk = 1'b1;
start = 1'b1;
#4000 $finish;
end
always #10 clk = ~clk;
initial
begin
#1;reset = 1'b1;
#10; reset = 1'b0;
#1; reset = 1'b1;
end
initial
begin
#10 ;
stimulus (0.0,0.5,vref_real,8'd5);
end
task stimulus (input analog, input step, input reference, input [7:0]delay);
real analog,step;
real reference;
begin
while(analog <= reference)
begin
repeat(delay)
@(posedge clk);
start <= 1'b0;
vref_d = $realtobits (reference);
vin_d = $realtobits (analog);
@(posedge done)
analog = analog + step;
@(posedge clk);
start <= 1'b1;
end
end
endtask
endmodule
Result
Schematic Capture
1. In a terminal window, change directory to the dig_source directory where there are 2
Verilog modules.
sreg.v ------------------------------- Succesive Approximation Register
clock.v ------------------------------ Divider with factor 2, used for SAR input clock
2. In the CIW or Virtuoso window, click File — Import — Verilog A Verilog In form
appears.
3. In the Verilog In form, double-click on the dig_source directory, then click on the
sreg.v file, type myDesignLib in the Target Library Name field (or use the browser to
specify it) and click Add to the right of the Verilog Files To Import field. The full path of
this verilog file appears in the field. Next click clock.v file and click Add next to the same
verilog files to Import field. clock.v will be added to the field after the sreg.v file.
4. Scroll down the form to Structural View Names and change the view name in the
Functional field to verilog.
4. In the Power Net Name field under Global Net Option tab of the Verilog In form,
change VDD! to VDD1! and click OK in the Verilog In form.
5. When the import is complete, a message appears asking if you want to see the log file.
Click Yes to display the log file window.
6. Close the log file window. Click Tools — Library Manager to open the Library
Manager. Click View — Refresh.In the Library column, click myDesignLib to
show all the cells in it. In the Cell column, two new cells (sreg and
Verilog_clock) are generated.
3. Click OK when done. A blank schematic window for the design appears.
4. After entering components, click Cancel in the Add Instance form or press Esc with
your cursor in the schematic window
Use Create – Pin or the menu icon to place the pins on the schematic window.
1. Click the Pin fixed menu icon in the schematic window. You can also execute Create
– Pin or press p. The Add pin form appears.
2. Type the following in the Add pin form in the exact order leaving space between the
pin names.
Make sure that the direction field is set to input/ouput/inputoutput when placing the
input/output/inout pins respectively and the Usage field is set to schematic.
3. Select Cancel from the Add pin form after placing the pins. In the schematic window,
execute View— Fit or press the f bindkey.
1. Click the Check and Save icon in the schematic editor window.
2. Observe the CIW output area for any errors.
4. Click OK. A New Configuration form opens. Enter schematic as the Top Cell View
or click Browse button to select it. Next, click Use Template at the bottom of the
form.
5. Select AMS in the Template Name field and click OK. Click OK on the New
Configuration form as well.
The hierarchy editor is filled with values for global bindings taken from the New
Configuration form. The cells in the design are bound to views depending on
• Which views of the cell exist
• Which existing view comes first in the view list
6. Click File - Save (Needed) to save the configuration. The update icon in the menu
Changes as shown in the hierarchy editor. Click the update icon.
2. Under Open for editing, click yes for configuration “SAR_ADC_Test config” and
click yes for open the Top Cell View “SAR_ADC_Test schematic” and click OK.
Both Configuration and schematic window appears.
3. Execute Launch – ADE L from schematic window to open the Analog Design
Environment (ADE) window.
4. In the ADE window, click Setup Simulator/Directory/Host and set the simulator
to ams in the Simulator cyclic field. Click OK.
In the upper right corner of the ADE window, confirm that simulator is
ams(Spectre).
If not, click Simulation — Solver, change the solver to spectre and click OK.
5. Click Analyses — Choose. Then type 30u in Stop Time field of tran analysis.
Click Enabled and click OK.
6. Click Setup - Model Libraries. In the Model Library Setup form, click Browse
and find the gpdk180.scs file in the ./models/spectre directory. Type NN in
Section field, click Add and click OK.
8. Click Setup — Connect Rules. In the Select Connect Rules form, highlight
ConnRules_18V_full_fast in the List of Connect Rules Used in Simulation and
click Delete to remove the default selection. In the Built-in rules section, click
connectLib. ConnRules_3V_full_fast in the Rules Name cyclic field. Because
the power supply in this SAR is 2.5V, which doesn’t exist in the Built-in rules list,
you need to customize the rule.
9. Click Customize in the above form. In the Customize Built-in Rules form, change the
Description to “This is the description for My_ConnRules_25V_full_fast”In the
Connect Module Declarations list, click on L2E_2. In the Parameters list, click vsup,
change 3.3 to 2.5 in Value field and click Change. Next highlight both E2L_2 and
Bidir_2 and change the values of the following parameters:
E2L_2 vsup=2.5 vthi=1.7 vtlo=0.8
Bidir_2 vsup=2.5 vthi=1.7 vtlo=0.8
Click OK. In the Information form, which reminds you to add the customized connect
rules to the list, click OK.
10.In the Select Connect Rules form, click Add and select the new modified connect
rules. Click Rename and edit the rule name to My_ConnRules_25V_full_fast.
Click OK.
11.In the ADE window, click Outputs — To Be Plotted — Select on Schematic and
click vsin, D0, D1, D2, D3, Vsh, Vcomp, clk, trigg and Vdac in the SAR_ADC
Schematic.
12.In the Schematic window, click Simulation — Netlist — Create. After the netlist
process is finished, click Simulation — Netlist — Display to display the Verilog-
AMS format netlist.
13. Click Session — Save State. In the Saving State form, change the name in State Save
Directory field to artist_states, change the state name to state_ams in the Save As field
and click OK.
14. In the upper right corner of the ADE window, confirm that simulator is ams(Spectre).
Click Simulation — Netlist and Run Options After the simulation finishes running, the
VIVA automatically shows the plotted waveforms.
RESULT:
1. Synchronous FIFO
module syn_fifo (
clk , // Clock input
rst , // Active high reset
wr_cs , // Write chip select
rd_cs , // Read chipe select
data_in , // Data input
rd_en , // Read enable
wr_en , // Write Enable
data_out , // Data Output
empty , // FIFO empty
full // FIFO full
);
// FIFO constants
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 8;
parameter RAM_DEPTH = (1 << ADDR_WIDTH);
// Port Declarations
input clk ;
input rst ;
input wr_cs ;
input rd_cs ;
input rd_en ;
input wr_en ;
input [DATA_WIDTH-1:0] data_in ;
output full ;
output empty ;
output [DATA_WIDTH-1:0] data_out ;
//-----------Internal variables-------------------
end
ram_dp_ar_aw #(DATA_WIDTH,ADDR_WIDTH)DP_RAM (
.address_0 (wr_pointer) , // address_0 input
.data_0 (data_in) , // data_0 bi-directional
.cs_0 (wr_cs) , // chip select
.we_0 (wr_en) , // write enable
.oe_0 (1'b0) , // output enable
.address_1 (rd_pointer) , // address_q input
.data_1 (data_ram) , // data_1 bi-directional
.cs_1 (rd_cs) , // chip select
.we_1 (1'b0) , // Read enable
.oe_1 (rd_en) // output enable
);
Endmodule
module ram_sp_sr_sw (
clk , // Clock Input
address , // Address Input
data , // Data bi-directional
cs , // Chip Select
we , // Write Enable/Read Enable
oe // Output Enable
);
parameter DATA_WIDTH = 8 ;
parameter ADDR_WIDTH = 8 ;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
//--------------Input Ports-----------------------
input clk ;
input [ADDR_WIDTH-1:0] address ;
input cs ;
input we ;
input oe ;
//--------------Inout Ports-----------------------
inout [DATA_WIDTH-1:0] data ;
//--------------Internal variables----------------
reg [DATA_WIDTH-1:0] data_out ;
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
reg oe_r;
QUESTION BANK
1. a) Design an Inverter with given specifications, completing the design flow
mentioned below.
i. Draw the schematic and verify DC analysis and Transient analysis.
ii. Draw the Layout, verify DRC, check for LVS and extract RC.
b) Write Verilog code and test bench for verification, for Parallel / Serial Adder
and observe the waveform.
2. a) Design an Inverter with given specifications, completing the design flow
mentioned below.
i. Draw the schematic and verify DC analysis and Transient analysis.
ii. Draw the Layout, verify DRC, check for LVS and extract RC.
b) Write Verilog code and test bench for verification, for 4-bit Synchronous /
Asynchronous Counter and observe the waveform
3. a) Design a Common Source Amplifier with given specifications, completing the
design flow mentioned below.
i. Draw the schematic and verify AC analysis, DC analysis and
Transient analysis.
ii. Draw the Layout, verify DRC, check for LVS and extract RC.
b) Write Verilog code, their test bench for verification and observe the waveform
for RS Flip Flop
4. a) Design a Common Drain Amplifier with given specifications, completing the
design flow mentioned below.
i. Draw the schematic and verify AC analysis, DC analysis and Transient
analysis.
ii. Draw the Layout, verify DRC, check for LVS and extract RC.
b) Write Verilog code and test bench for verification, for an NAND Gate and
observe the waveform.
5. a) Design a Differential Amplifier with given specifications, completing the
design flow mentioned below.
i. Draw the schematic and verify AC analysis, DC analysis and Transient
analysis.
ii. Draw the Layout, verify DRC, check for LVS and extract RC.
b) Write Verilog code and test bench for verification, for a transmission gate and
observe the waveform.
6. a) Design an Operational Amplifier ( Diff amp + CS amp ) with given
specifications, completing the design flow mentioned below.
i. Draw the schematic and verify AC analysis, DC analysis and Transient
analysis.
ii. Draw the Layout, verify DRC, check for LVS and extract RC.
b) Write Verilog code and test bench for verification and observe the waveform
for D FF.
7. a) Design a 4-bit R-2R based DAC with given specifications, completing the
design flow mentioned below.
i. Draw the schematic and verify the Transient analysis.
ii. Draw the Layout, verify DRC, check for LVS and extract RC.
b) Write Verilog code and test bench for verification, for an inverter and observe
the waveform
8. a) Design a Common Source Amplifier with given specifications, completing the
design flow mentioned below.
14. a) Design an Inverter with given specifications, completing the design flow
mentioned below.
i. Draw the schematic and verify DC analysis and Transient analysis.
ii. Draw the Layout, verify DRC, check for LVS and extract RC.
b) Write Verilog code and test bench for verification, for an XNOR gate and
observe the waveform.
REFERENCES
[1] Design of analog CMOS integrated circuits, B Razavi, First Edition, Mcgraw
Hill 2001
[2] Design, Layout, simulation, R.jacob Baker, Harry W Li, David E Boyci, CMOS
Circuit, PHI edition , 2005.
[3] CMOS Mixed Signal Circuit Design (Vol II of CMOS: Circuit design, Layout
and simulation), R. Jacob. Baker, CMOS-IEEE press and wiley interscience 2002.
[4] CMOS analog circuit design, P E Allen and D R Holberg , Second Edition ,
oxford university press 2002.
[5] Fundamentals of logic design with VHDL, Stephen Brown & Zvonko vranesic,
Tata McGraw-Hill, New Delhi, Second Edition, 2007.
[6] Verilog HDL: A guide to digital design and synthesis, Samir palnitkar, Second
edition