Computer Installation, Maintenance and

Repairing

IT (2012)

for

Second Semester

Sample Question
 1. Explain Hand Drive Physical Installation. (20 Marks)
2. Describe Hard Disk Installation Produces. Explain Hard Drive Physical
Installation. (20 Marks)
3. Describe High-Level (Operating System) Formatting. (10 Marks)
4. Explain FDISK and FORMAT limitations. (10 Marks)
5. Explain BIOS Hardware/Software. (15 marks)
6. Briefly explain ROM, PROM, EPROM, EEPROM /Flash ROM.
(20 marks)
7. Describe system components and explain processor, floppy disk and removable
drives, CD/DVD-ROM drive, keyboard and pointing device (Mouse), Video card
and Display, sound card and speakers. (20 marks)
8. Explain about motherboard installation. (20 marks)
9. Describe connect of the power supply, replacement of the cover and connection of
the external cables. (10 marks)
10. Explain connect I/O and other cable to the motherboard. (20 marks)
11. Explain running the Motherboard BIOS setup program. (CMOS setup)

(20 marks)

12. Explain troubleshooting new installations. (20 marks)

13. How are POST errors displayed? (20 marks)

14. Explain Hardware Diagnostics. (20 marks)

15. Explain Hardware Boot Process. (10 marks)

16. What are sample weekly and monthly maintenance procedures? (10 marks)

17. What are the problems during POST? (10 marks)

Computer Installation, Maintenance and Repairing

IT (2012)

for

Second Semester

Sample Answer & Question

 1. Explain Hand Drive Physical Installation. (20 Marks)
The step-by-step procedures for installing a hard drive are as follows: *
Check computer for an unused IDE connector. Typical Pentium-class and
above PCs have provision for four IDE devices; if you have less, add your drive
to an unused 40-pin connector on an IDE cable.
* Double-check the pin configuration. The colored (normally red or red-
flecked) stripe on one edge of the cable goes to pin 1 of the hard drive’s data
connector. Reverse this, and the drive won’t be capable goes to pin 1 of the hard
drive’s data connector. Reverse this, and the drive won’t be capable of
accepting identify, FDISK, or FORMAT. Most cable will be keyed to prevent
improper installation.
* Slide the drive carefully into a drive bay of the correct size. Most hard
drives, expect for a few very high-capacity SCSI drives meant for servers and
the Quantum Bigfoot series, are 3 1/2 –inch wide and 1-inch high. Some case
designs require that you attach rails to the side of the hard drive. If so, attach
them to the drive using the screws supplied with either the case or the drive.
Then slide the drive into the bay in the case until the rails latch into place.
* Attach the existing data cable connector to the back of the drive. In that
case, attach the cable to the drive before you slide it into the drive bay and
fasten it into place.
* Attach the appropriate power connector to the drive.
* Turn on the computer and listen for the new hard disk to spin up. If you
don’t hear anything from the drive, double-check the data and power cables.
* Restart the computer and access the BIOS setup screens to configure the
new hard disk. At a minimum, you’ll need to detect. If your BIOS has an auto
type setting, I recommend you use it as it will configure most parameters
automatically. For IDE hard drives above 528 million bytes, need to set LBA
translation to access the drive’s full capacity. Many systems have a Peripherals
Configuration screen, which also allows you to set UDMA, PIO, and block
mode configurations for maximum drive performance. See your drive’s
documentation for the correct settings. Save the BIOS configuration, and exit
the BIOS setup screen to continue.
* Restart the computer, and prepare to run FDISK to prepare the hard drive
for formatting and use. Or you can use drive partitioning software.

2. Describe Hard Disk Installation Produces. Explain Hard Drive Physical

Installation. (20 Marks)
To install a hard drive in a PC, you must perform some or all of the
following procedures:
* Configure the drive
* Configure the host adapter
* Physically install the drive
* Configure the system
* Partition the drive
* High-level format the drive.
The step-by-step procedures for installing a hard drive are as follows:
* Check computer for an unused IDE connector. Typical Pentium-class and
above PCs have provision for four IDE devices; if you have less, add your drive
to an unused 40-pin connector on an IDE cable.
* Double-check the pin configuration. The colored (normally red or red-
flecked) stripe on one edge of the cable goes to pin 1 of the hard drive’s data
connector. Reverse this, and the drive won’t be capable goes to pin 1 of the hard
drive’s data connector. Reverse this, and the drive won’t be capable of
accepting identify, FDISK, or FORMAT. Most cable will be keyed to prevent
improper installation.
* Slide the drive carefully into a drive bay of the correct size. Most hard
drives, expect for a few very high-capacity SCSI drives meant for servers and
the Quantum Bigfoot series, are 3 1/2 –inch wide and 1-inch high. Some case
designs require that you attach rails to the side of the hard drive. If so, attach
them to the drive using the screws supplied with either the case or the drive.
Then slide the drive into the bay in the case until the rails latch into place.
* Attach the existing data cable connector to the back of the drive. In that
case, attach the cable to the drive before you slide it into the drive bay and
fasten it into place.
* Attach the appropriate power connector to the drive.
* Turn on the computer and listen for the new hard disk to spin up. If you
don’t hear anything from the drive, double-check the data and power cables.
* Restart the computer and access the BIOS setup screens to configure the
new hard disk. At a minimum, you’ll need to detect. If your BIOS has an auto
type setting, I recommend you use it as it will configure most parameters
automatically. For IDE hard drives above 528 million bytes, need to set LBA
translation to access the drive’s full capacity. Many systems have a Peripherals
Configuration screen, which also allows you to set UDMA, PIO, and block
mode configurations for maximum drive performance. See your drive’s
documentation for the correct settings. Save the BIOS configuration, and exit
the BIOS setup screen to continue.
* Restart the computer, and prepare to run FDISK to prepare the hard drive
for formatting and use. Or you can use drive partitioning software.
3. Describe High-Level (Operating System) Formatting. (10 Marks)
The final step in the installation of a hard disk drive is the high-level
format. The high-level format is specific to the file system. On Windows 9x and
DOS systems, the primary functions of the high-level format is to create a FAT
and a directory system on the disk so the operating system can manage files.
Each drive letter created by FDISK must be formatted before it can be used for
data storage. Usually, you perform the high-level format with the FORMAT.
COM program or the formatting utility in Windows 9x Explorer.
FORMAT.COM uses the following syntax:
 FORMAT C: /S/V
This command high-level formats drive C:, writes the hidden operating
system files in the first part of the partition, and prompts for the entry of a
volume label to be stored on the disk. The FAT high-level format program
performs the following functions and procedures:
1. Scans the disk (read only) for tracks and sectors marked as bad during the
LLF, and notes these tracks as being unreadable.
2. Returns the drive heads to the first cylinder of the partition, and at
cylinder (Head 1, Sector 1) writes a DOS volume boot sector.
3. Writes a FAT at Head 1, Sector 2. Immediately after this FAT, it writes a
second copy of the FAT. These FATs essentially are blank except for
bad-cluster marks noting areas of the disk that were found to be
unreadable during the marked-defect scan.
4. Writes a blank boot directory.
5. If the /S parameter is specified, prompts the user for a volume label,
which is written as the fourth file entry in the root directory.
If the /V parameter is speciafied, prompts the user for a volume label, which
is written as the fourth file entry in the root directory.

4. Explain FDISK and FORMAT limitations. (10 Marks)

For using FDISK with care, but there are other limitations you should keep in
mind:
* FDISK doesn’t provide any help with issues of drive letter changes.
* FDISK requires FORMAT before the drive is ready for use.
* FORMAT must check the entire drive before making it ready for use.
 * FDISK and FORMAT are designed for a single operating system
environment, with no provision for multiboot options (Windows 9x and NT or
Windows 9x and Linux, for example).
* DSISK and FORMAT offer no procedure for migrating data to a new
drive, and XCOPY is tricky to use
* FDISK and FORMAT might cause conflicts with existing CD-ROM
drives, which often use the next available drive letter after the existing hard
drive
Typical features of automatic disk installation programs include the following:
• Replacement for SDISK and FORMAT.
• Database of drive jumpers for major brands and models
• Drive copy function.
• CD-ROM drive letter relocation utility.
• Menu-driven or wizard-driven process for installing new hard drive
Optional override of BIOS limitation of large hard drives.
Explain Floppy Drive Installation Produces. (10 Marks) A floppy drive is one of
the simplest types of drives to install. In most cases, installing a floppy disk
drive is a matter the drive to the computer chassis or case, and then plugging the
power and signal cables into the drive. Some type of bracket and screws are
normally required to attach the drive to the chassis are designed to accept the
drive with no brackets at all. Any brackets, if needed, are normally included
with the chassis or case itself. When you connect a drive, make sure the power
able is installed properly. The cable is normally keyed so you cannot plug it in
backward. Also, install the data and control cable. If there is no key is in this
cable, use the colored wire in the cable as a guide to the position of pin 1. this
cable is oriented correctly when you plug it in so the colored wire is plugged
into the disk drive connector toward the cut-out notch in the drive edge
connector. If the drive LED stays on continuously when the system is running,
that is a sure sign you have the floppy cable on backward.
Chapter 5: BIOS BASICS
5. Explain BIOS Hardware/Software.
(15marks)

6. Briefly explain ROM, PROM, EPROM, EEPROM /Flash ROM.

(20 marks)
ROM ( True or Mask ROM)
Most ROMs were manufactured with the binary data already “cast in” or integrated
into the die. The die represents the actual silicon chips . These are called Mask ROMs
because the data is formed into the mask from which the ROM die is photolithographically
produced.
Mask ROM are exactly to pre recorded CD- ROMs . CD-ROM is fast manufactured
as a blank and then the data is written to it by laser.

PROM
PROMs are a type of ROM that is blank when new and that must be programmed
with data .The PROM has been avabiable in size from 1 KB (8 KB) to 2MB (16MB) or more.
They can be identified by path numbers which are 27 nnnn-where the 27 indecates the TI
type PROM and the nnnn indicates the size of the chips in KB (not bytes) .
Although these chips are blank when new, they are preloaded with binary 1’s
A blank PROM can be programmed . This requires a special machine call a device
programmer .
Each binary 1 –bit can be thought of as a fuse, which is intact. Most chips run on 5
volts, but when a PROM is programmed , a higher voltage is placed at the various addresses
with the chip.
PROM chips are used at OTP chips . The act of programming a PROM takes
anywhere from a few seconds to a few minutes , depending on the size of the chip and the
algorithm used by the programming device. A typical PROM programmer has multiple
sockets .This is called gang programmer and can program several chips at once.
EPROM

An EPROM is a PROM that is erasable. An EPROM chip can be easily recognized by

the clear quartz crystal window set in the chip package over the die.
The purpose of the window is to allow the ultraviolet light to reach the chip die
because the EPROM is exposure to intense UV light. The window is quartz crystal.
The UV light erase the chip by causing a chemical reaction .To work , the UV
exposure must be at a specific wave length (2,537 Angstroms) , at a fairly high intensity
(12,000 uw/cm2) ,in close proximity (2 cm-3cm, or about when 1 inch ) ,unless and last for
between 5 and 15 minutes duration.
Professional type EPROM eraser that can handle up to 50 chips at a time. The quartz
crystal window on an EPROM is covered by type, which prevent accidental exposure to UV
light.

7. Describe system components and explain processor, floppy disk and removable
drives, CD/DVD-ROM drive, keyboard and pointing device (Mouse), Video card
and Display, sound card and speakers. (20 marks)
System Components
The components used in building a typical PC are fuse and power supply,
Motherboard, Processors with heat sink.
Memory Video card and display
Floppy drive Sound card and speakers
Hard disk drive cooling fans
CD-ROM/DVD drive cables
Keyboard Hardware (nuts, bolts, screw and brackets)
Pointing device (mouse) Operation system software

Processors
The motherboard should have one of the following processor sockets or slots:
Super 7: Supports the Intel Pentium, Pentium MMX, AMD K5, K6, K6-2, K6-3 Cyrix
6x86, 6x8xMx and MII Processors.
Socket 370 (also called PGA 370): Supports the socket versions of the Intel Celeron
processor.
Slot 1 (also called SC-242): Support the slot versions of the Intel Celeron, Intel
Pentium II and Pentium III processors
Slot 2 (also called SC-330): Supports the Intel Pentium II Xeon and Pentium Xeon
processors.
Floppy Disk and Removable Drives
Since the advent of the CD-ROM, the floppy disk drive has largely been
relegated to a minor role as an alternative system boot service.
LS-120(Super Disk) drives, which is a floppy drive that can read and write not
only the standard 720kB and 1.44MB formats but a high capacity 120MB format as
well.
Super Disk drive functions don’t need a standard floppy. Zip drive need to
install a conventional floppy for backward compatibility, system configuration and
system maintenance issues.
CD/DVD-ROM Drive
A CD/DVD-ROM drive should be considered a mandatory item in any PC
construction. This is because virtually all software is now being distributed on CD-
ROM, and many newer titles are on DVD. DVD drives can read CD-ROM drives as
well as DVD-ROMs, so they are more flexible.
DVD-ROM is a high-density data storage format that uses a CD sized disc to
store a great deal more data than a CD-ROM from 4.7 – 17GB, depending on the
format.
These drives can read standard drums and audio CDs as well as the higher
capacity DVD data and video discs.
Keyboard and Pointing Device (Mouse)
Two types of keyboard connectors are found in systems today. The purchasing
keyboard must be matched with the connectors on the motherboard.

8. Explain about motherboard installation. (20 marks)

When order the motherboard with a processor or memory, it will normally be
installed on the board but may also be included separately.
Preparing the new motherboard
Before install the new motherboard, it should install the processor and memory.
This normally be much easier to do before the board is installed in the chassis.
Most processors today run hot enough to require to some form of heat sink to
dissipate heat from the processor. To install the heat sink, use the following
prodedures:
1. Take the new motherboard out of the anti-static bag it was supplied in and
set it on the bag or the anti-static mat.
 2. Install the processor. There are two procedures, one for socketed processors,
and the other for slot based processor.
Socketed processors
The procedure is as follows:
Find the pin 1 on the processor. Next, find the corresponding pin 1 of the ZIF
socket for the CUP on the motherboard or there may be a bevel on one corner of the
socket. Insert the CUP into the ZIF socket by lifting the release lever until it is
vertical. Then align the pins on the processor with the holes in the socket and drop it
down into place.
If the processor does not go all the way into socket, check for possible interface
or pin alignment problem but make sure it is fully seated and there is no gap between
the bottom of the processor with the holes in the socket and drop it down into place.
Check for proper alignment and any possibly bent pins. If necessary, use a small
needle nose pliers to carefully straighten to any pins.
Don’t bend them too much or they will break off. When the processor is fully
seated in the socket, push the locking lever on the socket down until it latches to
secure the processor.
Slot based processor
Start by positioning the two universal retention mechanism brackets on either
side of the processor slot so that the holes in the brackets line up with the holes in the
motherboard. Push the included fasteners through the mounting holes in the retention
bracket and motherboard until it snaps into place.
3. If the CPU does not already have a heat sink attached to it, attach it now.
Most heat sinks will either clip directly to the CPU or to the socket with one or more
retainer clips. Be careful when attaching the clip to the socket.
In most cases, it is a good idea to put a dab of heat sink thermal
transfer compound on the CPU before installing the heat sink.
This prevents any air gaps and allows the heat sink to work more efficiently.
4. Refer to the motherboard manufacturer’s to set the jumpers, if any, to match
the CPU going to install. Look for the diagram of the motherboard to find the jumper
location and look for the tables for the right settings for CPU.
If the CPU was supplied already installed on the motherboard, the jumpers
should already be correctly set, but it is still a good idea to check them.
 9. Describe connect of the power supply, replacement of the cover and connection
of the external cables. (10 marks)
To attach the power connector from the power supply to the motherboard, do the
following:
1. If the system uses a single ATX style power connector, plug it in, it can go
on only one way. If two separate six-wire connectors are used, the two black
ground wires on the ends of the connectors must meet in the middle. Align
the power connectors such that the black ground wires are adjacent to each
other and plug in the connectors. Consult the documentation with your board
to make sure the power supply connection is correct.
2. Plug in the power lead for the CPU fan if one is used. The fan will either
connect to the power supply via a disk drive power connector or it may
connect directly to a fan power connector on the motherboard.
Replace the cover and connect external cables
Use the following procedures to complete the assembly:

1. Side the cover onto the case.

2. Before powering up the system, connect any external cabels
3. Plug the 15-pin monitor cable into the video card female connector.
4. Attach the phone cord to the modem.
5. Plug the round keyboard cable into the keyboard connector and plug the
mouse into the mouse port or serial port.

10. Explain connect I/O and other cable to the motherboard. (20 marks)
There are several connections that must be made between a motherboard and the
case. If the motherboard has onboard I/O, use the following procedures to connect the
cables:
1. Connect the floppy cable between the floppy drives and the 34 pin floppy
controller connector to the motherboard.
2. Connect the IDE cables between the hard disk, IDE CD-ROM, and athe 40-
pin primary and secondary IDE connectors on the motherboard.
3. On non-ATA boards, a 25-pin female cable port brackets in normally used
for the parallel port.
4. If the ports don’t have card slot-type brackets, the essential expansion slots
may be port knockouts on the back of the case that can use instead.
 5. Advanced motherboards include a built-in mouse port. The connector for
this port is not built into the back of the motherboard. In that case, plug the
cable into the motherboard mouse connector and then attach the external
mouse connector bracket to the case.
6. Attach the front panel switch, LED, and internal speaker wires from the case
front panel to the motherboard.

11. Explain running the Motherboard BIOS setup program. (CMOS setup)

(20 marks)

Now that everything is connect, the system will also test itself to determine
whether there are any problems:
1. Power on the monitor first, and then the system unit, observe the
operation via the screen and listen for any beeps from the system
speakers.
2. The system should automatically go through a power-on self-test (POST)
consisting of video BIOS checking, RAM testing and usually an installed
component report. If there is a fatal error during the POST, you may not
see anything on screen and the system might beep several times,
indicating a specific problem. Check the motherboard BIOS
documentation to determine what the beep bodes mean.
3. If there are no fatal errors, you should see the POST display on screen.
Depending on the type of motherboard, press a key or series of keys to
interrupt the normal boot sequence and get to the setup program screen
that allow you to enter the important system information. Normally, the
system will indicate via the onscreen display which key to press to
activate the BIOS setup program during the POST, check the
motherboard manual for the key to press to enter the BIOS setup.
4. After the setup program is running, use the setup program menus to enter
the current data and time, your hard drive settings, floppy drive types,
video cards, keyboard settings and so on. Most new motherboard enters
any parameters for it.
 5. Once you gave checked over all the setting in the BIOS setup, follow the
instructions on the screen or in the motherboard manual to save the
settings and exit the setup menu.
12. Explain troubleshooting new installations. (20 marks)

At this point, the system should reset and attempt to boot normally from either a
floppy disk or hard disk. The system should boot from Drive A and either reaches an
installation menu or an A: prompt. If there are any problems, there are some basic
items to check.
If the system won’t power up at all, check the power cord. If the cord is plugged
into a power strip, make sure the strip is switched on. There is usually a power switch
on the front of the case, but some power supplies have a switch on the back as well.
Check to see if the power switch is connected properly inside the case. There is
a connection from the switch to the motherboard, check both ends to see that they are
connected properly.
Check the main power connector from the supply to the board. Make sure the
connection are seated fully and if the motherboard is a Baby-AT type, make sure they
are plugged in with the correct orientation and sequence.
If the system appears to be running but you don’t see anything on the display,
check the monitor to ensure that it is plugged in, turned on, and properly connected to
the video card.
Make sure the monitor cord is securely plugged into the cord. Check the video
card to be sure it is fully seated in the motherboard slot. Remove and reseat the video
card and possibly try a different slot if it is a PCI card.
If the system beeps more than once, the BIOS is reporting a fatal error of some
kind, look in the BIOS section for a table of beep codes.

13. How are POST errors displayed? (20 marks)

The POST-tests normally provided three types of output messages: audio

codes, onscreen text messages, and hexadecimal numeric codes that are sent to

an I/O port address.

POST errors can be displayed in the following three ways:

 • Beep codes – Heard through the speaker attached to the
motherboard
• POST checkpoint codes – A special card plugged into either an ISA
or a PCI card slot is required to view these codes.
• Onscreen messages – Error messages displayed onscreen after the
video adapter is initialized.
BIOS POST Beep Codes

Beep codes are used for fatal errors only, which are errors that occur so

early in the process that the video card and other devices are not yet functional.

Because no display is available, these codes take the form of a series of beeps that

identify the faulty component. When your computer is functioning normally you

should hear one short beep when the system starts up at the completion of the

POST.

BIOS POST Checkpoint Codes

POST checkpoint codes can be used to track the system progress through

the boot process from power-on right up to the point at which the bootstrap

loader runs. When placing a POST code reader card into a slot, during the

POST, will see two digit hexadecimal numbers flash on the card’s display. If the

system stops unexpectedly or hangs, can identify the test that was in progress

during the hang from the two-digit code. This step usually helps to identify the

malfunctioning component.

BIOS POST Onscreen Messages

Onscreen messages are brief messages that attempt to indicate a specific

failure. These messages can be displayed only after the point at which the video

adapter card and display have been initialized.

 Most POST-code cards come with documentation listing the POST

checkpoint code for various BIOS versions. If your BIOS is different from what I

have listed here, consult the documentation for your BIOS or the information

that come with your particular POST card.

14. Explain Hardware Diagnostics. (20 marks)

Many types of diagnostic software are used with specific hardware

products.

SCSI Diagnostics

SCSI is an add-on technology, and most SCSI host adapters contain their

own BIOS that enable you to boot the system from a SCSI hard drive. The SCSI

BIOS contains configuration software for the adapter’s various features and

diagnostics software as well.

For SCSI adapters that use direct memory access (DMA) a Host adapter

diagnostics feature is available which tests the communication between the

adapter and the main system memory array by performing a series of DMA

transfer. It this test fails, you are instructed how to configure the adapter to use a

lower DMA transfer rate.

Network Interface Diagnostics

Network adapters have testing capabilities –

• Register Access test

• EEPROM vital data test
• EEPROM configurable data test
• FIFO loopback test
 • Interrupt test
• Ethernet core loopback test
• Encoder/ Decoder loopback test
• Echo exchange test

15. Explain Hardware Boot Process. (10 marks)

The term boot comes from the word bootstrap and describes the method by

which the PC becomes operational. Just as you pull on a large boot by the small

strap attached to the back, a PC loads a large operating system by first loading a

small program that can then pull the operating system into memory. The chain

of events begins with the application of power and finally results in a fully

functional computer system with software loaded and running. Each event is

triggered by the event before it can initiate the event after it.

Error messages displayed during the boot process and those displayed

during normal system operation can be hard to decipher.

OS Independent OS Dependent

- Motherboard ROM BIOS - System files

- Adapter card ROM BIOS extensions - Device drivers

- Master boot record - Shell program

- Volume boot record - Program run by autoexec.bat, the window

startup group and the Registry

- Window (win.com)
16. What are sample weekly and monthly maintenance procedures? (10 marks)

The following is a sample weekly disk maintenance checklist.

- Backup any data or important files.

- Delete all temporary files, such as .tmp, ~.*, *.chk, web browser history and
temporary Internet files.
- Empty the Recycle Bin.
- Finally run the defragmenting program.

The following are some monthly maintenance procedures should perform:

- Create an operating system startup disk.

- Check for and install any updated drivers for video cards, modems and

other devices.

- Check for and install any operating system updates.

- Check for and install antivirus software updates.

- Clean the system, including the monitor screen, keyboard, CD/DVD drives,

floppy drives, mouse and so on.

- Check that all system fans are operating properly, including the CPU heat

sink, power supply and any chassis fans.

17. What are the problems during POST? (10 marks)

Problems that occur during the POST are usually caused by incorrect

hardware configuration or installation. Actual hardware failure is a far less-

frequent cause. If you have a POST error, check the following:

1. Are all cables correctly connected and secured?

2. Are the configuration settings correct in setup for the devices you have
installed? In particular ensure the processor, memory and hard drive
settings are correct.
3. Are all drives properly installed?
4. Are switches and jumpers on the baseboard correct, if changed from the
default settings?
5. Are all resource settings on add-in boards and peripheral devices set so
that no conflicts exist for example, two add-in boards sharing the same
interrupt?
6. Is the power supply set to the proper input voltage?
7. Are adapter boards and disk drives installed correctly?
8. Is a keyboard attached?
9. Is a bootable hard disk installed?
10. Do the BIOS support the drive you have installed, and if so, are the
parameters entered correctly?
11. Is a bootable floppy disk installed in drive A?
12. Is all memory SIMMs or DIMMs installed correctly? Try reseating
them.
13. Do the operating system properly installed?
Microprocessor Programming

IT (2013)

for

Second Semester

Sample Question
PART (I)

1. Write the short notes about device selection signal. (10marks)

2. (a)What is the read and write signal. (10marks)
(b) Briefly explain about using read and write signals. (10marks)
3. Explain other control signals. (10marks)
4. Design a circuit to generate four active low control signals to allow an 8086
microprocessor to communicate with memory mapped or input/output mapped devices.
The signals should permit the processor to read from or write to these devices
individually. (10 marks)
5. Design a circuit to generate four active low control signals to allow an Z80
microprocessor to communicate with memory mapped or input/output mapped devices.
The signals should permit the processor to read from or write to these devices
individually. (10 marks)
6. Design a circuit to allow a 6800 microprocessor to specify whether it wishes to read
from or / and write to add-on devices. (10 marks)
7. Describe how to device two active-low addressing signals from a microcomputer. Only
one of the two signals needs to be activated at any instant of time and used to address an
add-on device. Assume that the area between locations 8000H and 9FFFH is available for
addressing by 16 address lines. (10 marks)
8. Modify the circuit so that a smaller addressing area is reserve for the two addressing
signals.
8. (a)Assume address
8700H Æ 87FFH
(10 marks)
(b)
Assume address
9FF8 H Æ 9FFF H (10 marks)
9. Design a circuit to provide an 8086 microprocessor with the ability to read from two
add-ons using I/o mapping. Assume that the area between 8700H to 87FFH. (10marks)
10. Derive two active-low device-selection signal to read from two add-ons to 8086
microprocessor by using input/output mapping. Assume that the addressing area between
A7C8H to A7CFH can be used. (10 marks)
11. Discuss for using address decoder and its advantages? (20 marks)
12. Write the short notes folloing anytwo with diagram.
(i) input ports (ii) out put ports (iii) address and data buffers. (20 marks)

PART (II)
13. (a) Why an IT learns Assembly Language? (10-marks)
(b) DEBUG the following simple programs. (10-marks)
1. mov ax,5
2. add ax,10h
3. add ax,20h
4. mov sum, ax
5. int 20
14. What is debugger? Explain the debug commands. (20 marks)
15. Trace the instructions using DEBUG and write down the final contents of AX and
BX registers. (20 marks)
16. Describe the CPU registers and explain the data registers with diagram. (20 marks)
17. (a) What is the Segment Registers? (10 marks)
(b) Describe the Index Registers. (10 marks)
18. Explain the conditions of control flags and status flags. (20 marks)
19. (a) Draw the IBM PC-XT/AT memory map.
(b) Demonstrate the data exchange the two variables from memory. (20-marks)
20. (a) If any of the following MOV statements are illegal, explain why:(10-marks)
(b) What will be the hexadecimal value of the destination operand after each of the
following moves? (If any instruction is illegal, write the word ILLEGAL as the
answer.) (10-marks)
21. (a) What will be the hexadecimal value of the destination operand after each of the
following Statements has executed? You may assume that var1 is a word variable
and that count and var2 are byte variables. If any instruction is illegal, write the
word ILLEGAL as the answer. (10-marks)
(b) As each of the following instructions is executed, fill in the hexadecimal value of
the operand listed on the right-hand side: (10-marks)
22. Explain direct addressing mode and indirect addressing mode. (20 marks)
Microprocessor Interfacing & Programming

IT (2013)

for

Second Semester

Sample Answer & Question

(Part I)
1. Write the short notes about device selection signal.(10marks)

Device-selection signals

When interfacing add-ons to a microcomputer, each add-on needs to be given a

unique address . A logic circuit is required to produce a pulse only when that address is
supplied by the microcomputer . This pulse selects ( enables) an add-on to communicate
with the microcomputer . During communication, the selected add-on supplies
information to the microcomputer, or read information from it.
The microprocessor selects the device it wants to communicate with by
supplying a suitable "device – selection " pulse to the device's enable line. The interface
of add-ons to a microprocessor creates the need for a flexible decoding arrangement to
produce an efficient interface and to permit the use of additional add-ons in future.
Memory mapping is the microcomputer deals with a device as one or more
memory locations . The communication is achieved by executing instructions such as '
move to ' or 'load from ' memory , ( Input/Output mapping , which is support by some ,
but not all, microprocessors . The microprocessor executes IN and OUT instructions to
produce an address of an input or an output device.
There are different ways of deriving selection signals . They depend on the
type of microprocessor and the available ( unused ) addresses . Generating ( device-
selection signals is combining two types of signals produced by a microprocessor. The
first is the device-control signal and the second signal is the addressing signal.
device – control signal + addressing signal = device –selection signal

2. (a)What is the read and write signal.(10marks)

Read and write signals

The read and write signals permit a microprocessor to indicate whether it wishes
to read from an input source or to write to an output destination.
Intel 8086 and 80186 and the zilop z80, the read and write signals appear on two separate
active low lines. In other microprocessors, such as the Motorola 68000, both the read and
write signals are issued from one line. A logic 1 on that line indicates a read command,
and a logic 0 indicates a write command. If required, the two signals can be separated by
using an inverting gate.

Figure: : Separating the read and write signals

2. (b) Briefly explain about using read and write signals. (10marks)

Explain Read & Write siganls are supplied to the Decading circuit
 The microprocessor reads information from device A and write information to
device B. Signal CS, can therefore be active by supplying a unique address and activating
the read line. This signal enables device A to supply information to the data bus. Device
A can be the source of the information, or it can act as carrier can activate signal CS2 in
the same way expect for activating the writing rather than the read line. This resc in
enabling device B to accept information can be used by device B, or passed or an external
circuit or system.

decoding
circuit
address and
control lines
CS2 CS1
microcomputer device
data line A

device
B

Fig. Interfacing devices to a microcomputers

3. Explain other control signals.(10marks)

Other control signals

Some microprocessors include one or two control signals to permite supporting
input / output mapping and memory mapping. It is at a logic 0 state during input/output
mapping and at a logic1 state during memory mapping. In the Intel 8086 and 80186, this
line is called the to/m line. It is at a logic1 state in input/output mapping.
Zilog z80 microprocessor identifies the type of mapping by using two output
lines. The first os the TORQ (Input/Output ReQuest) line which is set to a logic 0 state
when the microprocessor addresses a device using input/output mapping. The second line
is the MEMRQ(memory request) line which is set to a logic 0 when the microprocessor
addresses a memory mapped device. These signal can be included as inputs to a circuit
generating device-selection signals.
The Motorola 68000 microprocessor uses the memory-mapping method and thus
add are addressed in the same way as memory devices. One of the control signals
provided in the same way as 68000, the AS (address strobe) . It is set to a logic 0 state
when the address line contains a valid address. The DTACK (data acknowledge) line, to
accept an acknowledge from external devices.

4. Design a circuit to generate four active low control signals to allow an 8086
microprocessor to communicate with memory mapped or input/output mapped devices.
The signals should permit the processor to read from or write to these devices
individually.(10 marks)
Answer:
The requirement can be satisfied by using three control lines from the processors,
namely RD ,WR and M/IO line is low for input/output mapping and high for memory
mapping The required output signals are normally referred to as:
MEMR (MEMORY READ)
MEMW (MEMORY WRITE )
IOR (INPUT / OUTPUT READ)
IOW(INPUT / OUTPUT WRITE )
The MEMR and MEMW signals are used to identify the aim of the
microprocessor to communicate (read or write) by using the memory-mapping method
.On the other hand ,IOR and IOW signals indicate whether the microprocessor wants to
read from or write to a device by using the input/output-mapping method .The circuit in
figure uses two ICS,
1. 74ls32 (quad 2 input OR gate 2c) and
2. 2.74LS14 (hex schmitt-trigger inverting gates)

RD
MEMR

WR
MEMW
M/IO o

IOR

IOW

.
Fig . Generating device-control signals using the 8086.

5. Design a circuit to generate four active low control signals to allow an Z80
microprocessor to communicate with memory mapped or input/output mapped devices.
The signals should permit the processor to read from or write to these devices
individually.(10 marks)

Answer:
The z80 provides one line for the input/output request(IORQ) and another for the
memory request(MEMRQ) when the z80 wants to receive information from an external
source, it activates either of these lines and sets the read line (RD) to a logic 0 state.
Similarty , writing to an external destination is performed by activating either of these
lines and the write line (WR).
 The required four signals can be produced by using these two lines with the read
and write lines, where all the signals are active-low. So the circuit in figure use only one
TC (1 74LS32 (quad 2input OR gate IC).

RD
MEMR

WR
MEMW
MEMRQ

IOR
IORQ

IOW

.
Fig: Generating device-control signal using the Z80.
Let us now consider generating device-control signals from the 68000 microprocessor.
Answer:
Since 6800 microprocessor uses memory mapping, reading from or writing to
add-one is treated as a memory read or a memory write respectively. Both the read and
write signals are supplied on a single line and can be separated by using a single inverting
gate to produce active low read and write signals.
R/W oR
MEMR

W
MEMW
MEM

Fig: Generating device – control signals using the 68000 microprocessor

6. Design a circuit to allow a 6800 microprocessor to specify whether it wishes to read

from or / and write to add-on devices.(10 marks)

Answer
A simple circuit which can be used to allow the microprocessor to send
information (write) to the add-on. Once the device receives the information, it activates
the DTACK line informing the micro- processor of the reception of data.
If the aim of the interface is to receive data from the add-on (read), then an
inverting gate is required to invert the R/W signal before supplying it to the input of the
OR gate.
 68000

data bus

AS decoding
device
circuit
address bus
En
R o
Ack
DTACK

68000

data bus

AS decoding
device
circuit
address bus
En
W o
Ack
DTACK

Fig. Interfacing to the 68000 microprocessor acknowledgement from device.

7. Describe how to device two active-low addressing signals from a microcomputer. Only
one of the two signals needs to be activated at any instant of time and used to address an
add-on device. Assume that the area between locations 8000H and 9FFFH is available for
addressing by 16 address lines.(10 marks)
Answer
The two addressing signals can be generated by decoding some or all of the 16
address lines to generate two signals, each identifying the area reserved the area reserved
for addressing one of the two devices.
Required address, 8000H 9FFFH

Signal X1 will be low when A15 is high white A14 and A13 are low.
For X1,
100x xxxx xxxx xxxx
8000H 9FFFH
Reserving area is
13
9FFFH – 8000H = 1FFFH = 2 = 8 KB
-Since X1 is low, the state of each output depends on the state of A12
X2 will be low (active) when X1 and A12 are low.
For X2,
1000 xxxx xxxx xxxx
8000H 9FFFH
Reserving area is
8FFFH – 8000H = FFFH = 12bit = 2 12 = 4 KB
X3 will be low (active) when X1 is low and A12 is high
For X3,
1001 xxxx xxxx xxxx
9000H 9FFFH
Reserving area is
12
9FFFH – 9000H = FFFH = 12 bit = 2 = 4 KB

A15 o X1

A14

A13
X2
A12

X3
o

2-input OR -4
Inverter -2

8. Modify the circuit presented in Example 2.4 so that a smaller addressing area is reserve
for the two addressing signals. (10 marks)
8. (a)Assume address
8700H Æ 87FFH
1000 0111 1111 1111
Signal X1 will be low, when A15 and A3 to A10 are high while A11, A12, A13, and A14 are
low.
For X1,
1000 0111 1111 1xxx
87F8H Æ 87FFH
Reserving area is
 87FFH – 87F8H = 7F =111=23= 8 bytes
Since X1 is low , the state of each output depends on the state of A2.

X2 will be low ( active ) when X1 and A2 are low.

For X2,
1000 0111 1111 10xx
87F8H Æ87FB H
Reserving area is
87FBH – 87F8H = 3 H = 11 = 22 = 4 bytes
X3 will be low ( active ) when X1 is low and A2 is high .
For X3,
1000 0111 1111 11xx
87FCH Æ 87FFH
Reserving area is
87FFH – 87FCH = 3H = 11 = 22 = 4 bytes

A14

A13

A12

A11
X1
A10
A9
A8
o

A7
A6 o
A5

A4
A3 o
A15 X2
A2

X3
o
2-input OR -8
3-input NAND - 3
Inverter
 A14 o
A13 o
A12 o
A11
o

A10

A9 X1
A8
o X2

A7
X3
A6
o
A5

A4

A3

A15

A2
2-input OR -2
13-input NAND - 1
Inverter -5

8. (b)
Assume address
9FF8 H Æ 9FFF H

Signal X1 will be low, when A15 and A3 to A12 are high while A13, and A14 are low.
For X1,
1001 1111 1111 1xxx
9FF8 H Æ 9FFF H
Reserving area is
9FFF H Æ 9FF8 H = 7H =111=23= 8 bytes
Since X1 is low , the state of each output depends on the state of A2.

X2 will be low ( active ) when X1 and A2 are low.

For X2,
1001 1111 1111 10xx
9FF8 H Æ 9FFB H
Reserving area is
9FFB H – 9FF8 H = 3 H = 11 = 22 = 4 bytes
X3 will be low when X1 is low and A2 is high .
For X3,
1000 0111 1111 11xx
9FFCH Æ 9FFFH
Reserving area is
9FFFH – 9FFC = 3H = 11 = 22 = 4 bytes
 A15

A14 o
A13 o
A12

A11

A10 X1
A9
o X2

A8
X3
A7
o
A6

A5

A4

A3

A2

To reduce the reserved addressing area, a simpler circuit can be

constructed by connecting lines A15, AA14, …,A3 to the inputs of a 13-input NAND
gate , where lines A14 and A13 are inverted before their connections to the input of the
NAND gate.

9. Design a circuit to provide an 8086 microprocessor with the ability to read from two
add-ons using I/o mapping. Assume that the area between 8700H to 87FFH.(10marks)

Derive Read signal by using Input / Out mapping

R
IOR
IO

Both Read line and Input/output mapping line are zero, IOR is active-low
state.
1 2 input OR gate
Derive addressing signal
Let address locations are between 8700H to 87FFH.
 A15

A14 o
A13 o
A12 o
A11 o
A10 X1
A9
o X2

A8
X3
A7
o
A6

A5

A4

A3

A2

1 13- input NAND gate

2 2-input OR gate
5 inverting gate
For X1,
A3 to A15 are inputs to the 13-input NAND gate,
A11 to A14 are low , so they are inverted before they connected to the input of NAND
gate. A3 to A10 as well as A15 are high.
Locations are
1000 0111 1111 1xxx
( x is don't care )
( 87F8H to 87FFH )
Reserving area are
( 87FFH – 87F8H = 7H = 111 =23 =8 bytes )
A2 is selection time , so X2 and X3 depend on it .
When X2 is low active, both X1 and A2 are low .
Location are
1000 0111 1111 10xx
( 87F8 H to 87FB H )
Reserving area are
(87FB H – 87F8= 3H =11 =22 = 4 bytes)
when A2 is high and X1 is low, X3 is low active .
Location are
1000 0111 1111 11xx
(87FC H to 87FF H )
Reserving area are
( 87FFH – 87FC H = 3H = 11 =22 =4 bytes )
Deriving device – selection signal
X2
CS1

IOR
CS2
o
 X3

2 2 input OR gate
when IOR is low, CS1and CS2 depend on that X2 and X3 Both CS1 and CS2
are low active . The reserved addressing of both CS1 and CS2 are 4 byte.

10. Derive two active-low device-selection signal to read from two add-ons to 8086
microprocessor by using input/output mapping. Assume that the addressing area
between A7C8H to A7CFH can be used.(10 marks)

Assume addressing area between

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
A7CHH = 1 0 1 0 0 1 1 1 1 1 0 0 1 0 0 0
A7CFH = 1 0 1 0 0 1 1 1 1 1 0 0 1 1 1 1
It means 1010 0111 1100 xxxx. So that a circuit to derive addressing signal is

Using A2 line to divide two addressing signal X1 and X2 from X which occupied given
addressing area each. These area are
X = A7C8H to A7CFH = 8 bytes
X1 = A7C8H to A7CBH = 4 bytes and
X2 = A7CCH to A7CFH = 4 bytes occupied.
The given control signals from 8086 up are RD, WR and M/IO. The required control
signal IOR is derived by combining RD and IO signals.
Required device-selection signals can be combined by addressing signals and device
control signal.
 D.S.S = A.S + D.C.S
C.S1 = X1 = IOR and C.S2 = X2 + IOR

The designed circuit is using following ICs.

1. One 74LS133(13 input NAND) IC
2. Two 74LS32 (quad 2 input Ors) ICs and
3. Two 74LS14 (hex inverting gates)ICs.
11. Discuss for using address decoder and its advantagaes ?(20 marks)
Using an address decoder
Producing addressing signals normally requires the use of several logic gates.
Instead of using such gates, one or more address decoder ICs can be employed. 74LS138
3-to-8 line decoder is one of the most widely used decoders. It has six input lines, three of
which ( A,B and C ) are binary. weighted selection lines, and three of which ( G1,G2 and
G3 ) are enable lines. It provides eight output lines ( Y0 to Y7 ), only one of which is
activated ( logic 0 ) at one time . The activated output is the one whose address is the
binary combination of the three selection lines. This can only take place if the output is
enabled by setting G1=1 , G2 = 0, and G3=0. 74LS154 is a 4 – to – 16 lines decoder. It is
a 24 pins to providing four selection lines (A ,B, C and D ) . Two active-low enable lines
( G1 and G2 ) and 16 output lines ( Y0 to Y15 ).
+5V +5V
16 16
Y0 15 Y0 15
A10 1 14A A5 1 A
12 Y1
Y1 14 14
A11 2 B A6 2 B
Y2 13 Y2 13
A12 3 C A7 3 C
Y3 12 Y3 12
A13 6 Y4 11
Y4 11 A8 6 G1
G1
Y5 10
Y5 10 A9 5
A14 5 G2 G2
Y6 9
Y6 9 Y7
A15 4 G3 4 G3
Y7 7

8 OV 8 OV
Fig: Address decoders ( a) two 74LS138 ICS

74LS138 IC is used to produce eight addressing signals Y0 to Y7. Address

lines A13 , A14 and A15 of the controlling microprocessor are connected to the enable
lines G1, G2 and G3 respectively .The decoder is enabled when lines A13,A14 and A15
are 1,0 and 0 respectively. Lines A10,A11 and A12 are used as channel selection lines by
connecting them to inputs A,B and C of the IC. Address ranging from 2000H to 3FFFH,
so reserving area is 3FFFH-2000H =1FFFH =213 =8 kilobytes . For each device reserves
1 kilobyte.

The addressing area reserved for each device is reduced by using a second 74
LS138 decoder which is enabled when A8 is high and both of address line A9 and output
Y0 of the first decoder are low. For Y0 of second decoder the area 2100H to 21FFh . so
reserving area is 21FFH-210FH=FF H =8 bit=28=256 bytes . Each device reserve 32
bytes.
 The addressing area reserved per signal is 1 kilobyte for outputs Y1 to Y7 of
the first decoder and 32 bytes for output Y0 to Y7 of the second decoder.

The advantage of using address decoders: they permit multi-device decoding

without increasing the complexity, cost or size of the interfacing circuit and without
sacrificing addressing area.

12. Write the short notes folloing anytwo with diagram.

(i) input ports (ii) out put ports (iii) address and data buffers.(20 marks)

(i) Input ports

An input port is a 3 state buffer whose output is equal to its input only when
enabled by a controlling device, such as a microprocessor. It consists of several channels.
An input port can be formed from using one of many ICS.74LS244 is an 8 line 3
state buffer which contains two active low enable signals (1G and 2G). Each of these
signals control four buffer lines. Line 1G controls the four lines whose inputs are
A1,A2,A3 and A4whose output are C1,C2,C3and C4. Similarly, line 2G controls the four
lines B1,B2,B3 and B4 whose outputs are D1,D2,D3 and D4.An output line is at the same
logic state as its corresponding input when its control line is activated (logic 0 state)
By supplying the same command signal to both 1G and 2G.Lines, the IC will act
as an 8 bit port. The eight buffers of the IC are non-latching which makes the IC suitable
for use as input parts. An enabled input port supplies information to a data bus which is
time shared by several devices and accepts signals from one device at a time IC is
required for connection to an 8 bit data bus where as a 16 bit data bus requires two such
Ics to receive 16 bit information.
Each of these Ics contains four buffers, each of which can be enabled or disabled
independently of the others. The difference between the two Ics is in the state of the
enable line . It is active low in the 74LS125 and active high in the 74LS126.

1 20
1G VCC
2 19
A1 2G
3 18
D4 C1

4 A2 B4 17

5 D3 C2 16

6 15
A3 B3
7 14
D2 C3
8 13
A4 B2

9 D1 C4 12

10 11
GND B1
 Fig 2.11 These state non latching buffers (a) the 74LS244 octal bufferI

(ii)Output ports

The requirement imposed on an output part is different from that imposed on an

input part. Input part needs to put signals on the data bus only for a very shart period of
time. The output port is supplied with signals from the data bus for a very short time and
is required to latch those signals so that the output will be available as long as the buffer
is supplied with power An output port consists of 3 state latches

A widely used IC is the 74LS374 octal D type latch. It contains eight 3-state edge-
triggered flip-flops and provides two control lines, the first (pin 1) is the output enable
line, while the second (pin11) is the clock line D and Q represent the input and the
output . When the IC is utilized as an output part, the output enable line is connected to
the o-v rails so that the output is always enabled when the clock line changes from a logic
0 to a logic1 state, each of the outputs is latched to the same logic state as its
corresponding input. The IC can be connected to the data bus when the microprocessor
wants to transfer information to the output it delivers the information to the data bus and
alters the state of the clock line to command the 74LS374 IC to accept and latch
information.

1 20
CE VCC
2 19
Q0 Q7
3 18
D0 D7

4 D1 D6 17

5 Q1 Q6 16

6 15
Q2 Q5
7 14
D2 D5
8 13
D3 D4

9 Q3 Q4 12

10 11
GND CU
 The 74LS374 octal 3 state latch

(iii).Address and data buffers

The address and data buses of microcomputers are capable of driving several
external devices in addition to those already connected inside the microcomputer. Buffers
can be introduced to increase the drive capability of the microcomputer.
The address bus is unidirectional; it passes signals from the microprocessor to the
devices. It can be buffered by using the 74LS244 octal buffer IC. It can be buffer up to
eight address lines supplied to its inputs. The IC is enabled by connecting its 1G and 2G
lines to the o.v rail. Control lines, IOR and IOW van also be buffered in the same way.

The data bus is bidirectional; it needs a different type of buffer. It uses the
74LS245 octal bus transceiver IC .Pin 1 is the direction pin and indicates to the IC
whether the microprocessor wants to receive or transmit data. The IC has an enable pin
(pin 19); if that pin is connected to the o.v rail, the IC is enabled .A device selection
signal van be used to enable the IC only when the microprocessor executes a read or a
write to a particular address. Two 74LS245 ICS are required for a 16 bit bus each
connected to eight of the 16 data lines.

+5V _
_ 0V _
10 20
GND VCC

2 18 LSB
D0 A1 B1
_
3 17
D1 A2 B2

D2 4 A3 B3 16
data buffered data
bus 5 15 lines
D3 A4 B4
lines
D4 6 A5 B5 14

D5 7 13
A6 B6
D6 8 12
A7 B7
D7
9 A8 B8 11 MSB
DIR CS

direction 1 19
command

device-selection
signals
 Fig: Using the 74LS245 octal 3-state transceiver

IT (2013) Microprocessor Interfacing and Programming

Part (II)
13. (a) Why an IT learns Assembly Language? (10-marks)

Assembly language is used to learn about the computer’s architecture and

operating system. Because of assembly language’s close relationship to machine
language, it is closely tied to the computer’s hardware and software.
Assembly language’s usefulness as a learning tool should not be
underestimated. By having such intimate contact with the operating system,
assembly language programmers come to know instinctively how the operating
system works. Coupled with a knowledge of hardware and data storage, they gain
a tremendous advantage when tackling unusual programming problems.

(b) DEBUG the following simple programs. (10-marks)

1. mov ax,5
2. add ax,10h
3. add ax,20h
4. mov sum, ax
5. int 20

DEBUG (load the DEBUG.COM program)

-A 100 (begin assembly at location 100)
mov ax, 5 (enter the rest of the program)
add ax, 10
add ax, 20
mov [0120], ax (SUM at the location 0120)
int 20 (end program)
- (press ENTER to end assembly)
-R (display registers)
-T (trace each instruction)
-T
-T
-G (execute the rest of the program)
-Q (quit DEBUG, and return to DOS)

14. What is debugger? Explain the debug commands.(20 marks)

A debugger is a program that allow to examine registers and memory and
to step through a program one statement at a time to see what is going on. In
assembly language, you will depend upon this ability to see what the CPU is doing.
There is a number of debuggers. DEBUG is a simple, easy-to-use debugger supplied
with DOS. The SYMDEB utility is supplied with Microsoft MASM 4.0. The
CODEVIEW debugger was supplied by Microsoft MASM version 5.0.
 Debug commands are:
A 100 Assemble instructions into machine language, beginning at location 100.
G Go (execute) from the current location to the end of the program.
P Procedure trace a single instruction or DOS function call. This prevents
you from having to trace instructions within DOS functions.
Q Quit DEBUG and return to DOS.
R Register display
T Trace a single instruction, and show the contents of the registers after it is
executed.
U Unassemble. Disassemable memory into assembly language instructions.

15. Trace the instructions using DEBUG and write down the final contents of AX and
BX registers.(20 marks)

(a)
mov al, FFFE
sub al, 2
mov bl, 8C
mov bh, 2D
add bx, ax
int 20

(b) (The INC instruction adds 1 to a number, and the DEC instruction
subtracts 1.)
mov ax, 0
dec ax
dec ax
add ax, 2
inc ax
int 20

16. Describe the CPU registers and explain the data registers with diagram.(20 marks)
Registers are special work areas inside the CPU designed to be accessed at
high speed. The registers are 16 bits long, but you have the option of
accessing the upper or lower halves of the four data registers:
Data register 16-bit: AX, BX, CX, DX
8-bit: AH, AL, BH, BL, CH, CL, DH, DL
Segment registers CS, DS, SS, ES
Index registers SI, DI, BP
Special registers IP, SP
Flag registers Overflow, Direction, Interrupt, Trap, Sign, Zero,
Auxiliary Carry, Parity, Carry
Data Register. Four registers, named data registers or general-
purpose registers are used for arithmetic and data movement. Each register
may be addressed as either a 16-bit or 8-bit value. For example, the AX
register is a 16-bit register; its upper 8 bits are called AH, and its lower 8 bits
 are called AL. Bit positions are always numbered from right to left, starting
with 0.

bits: 15 . . . . . . . . . . . . . . . . . . . . . 0
16 bit AX register

AH register AL register

bits: 7. . . . . . . . . . 07 . . . . . . . . . . 0

Instructions may address either 16-bit or 8-bit data registers from the
following list:

AX BX CX DX

AH AL BH BL CH CL DH DL

Each general-purpose register has special attributes:

AX (accumulator). AX is called the accumulator register because it is favored
by the CPU for arithmetic operations. Other operations are also slightly more
efficient when performed using AX.
BX (base). Like the other general-purpose registers, the BX register can
perform arithmetic and data movement, and it has special addressing abilities.
It can hold a memory address that points to another variable. Three other
registers with this ability are SI, DI and BP.
CX (counter). The CX register acts as a counter for repeating or loping
instructions. These instructions automatically repeat and decrement CX and
quit when equals 0.
DX (data). The DX register has a special role in multiply and divide
operations. When multiplying, for example, DX holds the high 16 bits of the
product.

17. (a) What is the Segment Registers?(10 marks)

(b) Describe the Index Registers. (10 marks)

(a) Segment Registers

The CPU contains four segment registers, used as base locations for
program instructions, data, and the stack. In fact, all references to memory on
the IBM-PC involve a segment register used as a base location. The segment
registers are:
CS (code segment). The CS register holds the base location of all executable
instruction (code) in a program.
 DS (data segment). The DS register is the default base location for memory
variables. The CPU calculates the offsets of variables using the current value
of DS.
SS (Stack Segment). The SS register contains the base location for the current
program stack.
ES (extra segment). The ES register is an additional base location for memory
variables.

17. (b) Index Registers

The index registers contains the offsets of variables. The term offset refers
to the distance of a variable, label, or instruction from its base segment. Index
registers speed up processing of strings, arrays, and other data structures
containing multiple elements. The index registers are:
SI (source index). This register takes its name from the 8088's string
movement instructions, where the source string is pointed to by the SI
registers. SI usually contains an offset value from the DS register, but it can
address any variable.
DI (destination index). The DI register acts as the destination for the 8088's
string movement instructions. It usually contains an offset from the DS
register, but it can address any variable.
BP (base pointer). The BP register contains an assumed offset from the SS
register, as does the stack pointer. The BP register is often used by a
subroutine to locate variables that were passed on the stack by a calling
program.

18. Explain the conditions of control flags and status flags.(20 marks)
Control Flags. Individual bits may be set in the Flags register by the
programmer to control the CPU's operations. These are the Direction,
Interrupt and Trap flags. Abbreviations used by DEBUG and CODEVIEW
debugger programs are shown in parentheses.
The Direction flag controls the assumed direction used by string
processing instructions. The flag values are 1 = Up (UP) and 0 = Down (DN).
The programmer controls this flag, using the STD and CLD instructions.
The Interrupt flag makes its possible for the external interrupts are caused
by hardware devices such as the keyboard, disk drives, and the system clock
timer. The Interrupt flag is cleared by the programmer when an important
operation is going to on that must not be interrupted. The flag must be then set
to allow the system to process to process interrupts normally again. The flag
values are 1 = Enabled (EI) and 0 = Disabled (DI), and are controlled by the
CLI and STI instructions.
The Trap flag determines whether the CPU should be halted after each
instruction. Debugging programs use this flag to allow the user to execute one
instruction at a time (called tracing). The flag values are 1 = Trap on and 0 =
Trap off, and the flag may be set by the INT 3 instructions.
 Status Flag. The status flag bits reflect the outcome of arithmetic and logical
operation performed by the CPU. These are the Overflow, Sign, Zero,
Auxiliary Carry, Parity, and Carry flags.
The Carry flag is set when the result of an arithmetic operation is too large
to fit into the destination. For example, if the values 200 and 56 were added
together and placed in an 8-bit destination, the result (256) would be too large
and the Carry flag would be set. The flag values are 1 = Carry (CY) and 0 =
No carry (NC).
The Overflow flag is set when the signed result of an arithmetic operation
may be too large to fit into the destination area. The flag values are 1 =
overflow (OV) and 0 = no overflow (NV).

The Sign flag is set when the result of an arithmetic or logical operation
generates a negative result. Since a negative number always has a 1 in the
highest bit position, the Sign flag is always a copy of the destination's sign bit.
The flag values are Negative (NG) and Positive (PL).
The Zero flag is set when the result of an arithmetic or logical operation
generates a result of zero. The flag is used primarily by jump and loop
instructions, in order to allow branching to a new location in a program based
on the comparison of two values. The flag values are Zero (ZR) and Not Zero
(NZ).
The Auxiliary Carry flag is set when an operation causes a carry from bit 3
to bit 4 (or a borrow from bit 4 to bit 3) of an operand. It is rarely used by the
programmer. The flag values are Aux Carry (AC) and No Aux Carry (NA).
The Parity flag reflects the number of bits, the Parity is even (displayed as
PE). If there is an odd number of bit, the Parity is odd (displayed as PO). This
flag is used by the operation system to verify memory integrity and by
communications software to verify correct transmission of data.

19. (a) Draw the IBM PC-XT/AT memory map.

(b) Demonstrate the data exchange the two variables from memory. (20-marks)
1. mov al, value 1 ; Load value 1 into al
2. xchg al, value2 ; exchange al with value 2
3. mov value 1,al ; store al in value 1
………
………
………
value 1 db 0Ah ; initialized variables
value 2 db 14h
 (a)The IBM PC-XT/AT memory map

640 K

EGA color video (128K)

00000 Interrupt Vector Table

00400 BIOS and DOS data

00600 Resident portion of DOS

User RAM

A0000 EGA color video

B0000 Monochrome video

B8000 Color video

C0000 Reserved ROM (not used)

F0000 Reserved ROM

F6000 ROM BASIC

FE000 ROM BIOS

(b)

On line 1, value 1 is copied to AL;

(memory)

0A
AX: 00 0A (Value 1)

14

On line 2, AL is exchanged to value 2;

(memory)

0A (Value 1)
AX: 00 14
(Value 2)
0A

On line 3, moves AL to value 1, completing the exchange of the two

variables;

(memory)

14 (Value 1)
AX: 00 14
(Value 2)
0A
20. (a) If any of the following MOV statements are illegal, explain why:(10-marks)
a. mov ax, bx
b. mov var_2, al
c. mov ax, bl
d. mov bh, 4A6Fh
e. mov dx, 3
f. mov var_1, bx
g. mov al, var_3
h. mov cs, 0
i. mov ip, ax
j. mov word ptr, var_3, 10
k. mov var_1, var_2
l. mov ds, 1000
m. mov ds,es

(b) mismatching sizes

(c) mismatching sizes
(d) must be a 16-bit register
(h) cannot change CS
(i) cannot change IP
(j) not illegal, but will overwrite next memory byte
(k) memory-to-memory move
(l) immediate value to segment register
(m) segment register to segment register

20. (b). What will be the hexadecimal value of the destination operand after each of the
following moves? (If any instruction is illegal, write the word ILLEGAL as the
answer.) (10-marks)

Instruction Before After

a. mov ax, bx AX=0023 BX=00A5 AX=
b. mov ah,3 AX=06AF AX=
c. mov dl, count DX=8F23 count=1A DL=
d. mov bl, ax BX=00A5 AX=4000 BL=
e. mov di,100h DI=06E9 DI=
f. mov ds,cx DS=0FB2 CX=0020 DS=
g. mov var1,bx var1=0025 BX=A000 var1=
h. mov count, ax count=25 AX=4000 count=
i. mov var1, var2 var1=0400 var2=0500 var1=
var1 and var2 are 16-bit operands, and count is 8 bits long. All numbers
are in hexadecimal format.

a. 00A5h
b. 03AFh
c. 8F1Ah
 d. illegal
e. 0100h
f. 0020h
g. A000h
h. illegal
i. illegal

21.(a) What will be the hexadecimal value of the destination operand after each of the
following Statements has executed? You may assume that var1 is a word variable
and that count and var2 are byte variables. If any instruction is illegal, write the
word ILLEGAL as the answer. (10-
marks)

Instruction Before After

a. mov ah, bl AX=0023 BX=00A5 AX=
b. add ah,3 AX=06AF AX=
c. sub dl, count DX=8F23 count=1A DX=
d. inc bl BX=FFFF BX=
e. add di,100h DI=06E9 DI=
f. dec cx CX=0000 CX=
g. add var1,bx var1=0025 BX=A000 var1=
h. xchg var2, al var2=25 AL=41 var2=
i. sub var1, var2 var1=15A6 var2=B8 var1=
j. dec var2 var2=01 var2=

All numbers are in hexadecimal.

a. A523h
b. 09AFh
c. 8F09h
d. FF00h
e. 07E9h
f. FFFFh
g. A025h
h. 41h
i. illegal
j. 00h

21. (b) As each of the following instructions is executed, fill in the hexadecimal value of
the operand listed on the right-hand side:
(10-marks)

mov ax, array1 ; a. AX=

xchg array2, ax ; b. AX=
dec ax
 sub array2,2 ; c. array2=
mov bx,array2 ; d. AX=
…..
…..
array1 dw 20h,10h
array2 dw 30h,40h

a. 0020h
b. 0030h
c. 001Eh
d. 1E2Fh
22. Explain direct addressing mode and indirect addressing mode. (20 marks)
Direct Addressing
The MASM documentation distinguishes between two types of operands
used jin direct addressing: direct-memory operands and relocatable operands. A direct
memory operand combines a sement value with an offset that represents an absolute
memory address at runtime. A relocatable operand is any label or symbol identifying a
16-bit displacement from a segment register. The syntax for creating a direct-memory
operand is :
Segment: offset
Segment refers to either a segment register or a segment name. its value is unknown at
assembly time, because it depends on where DOS will eventually load the program.
Offset may bbe an integer, symbol, lable, or variable. Eg are:
Mov ax, ds:5 ; segment register and offset
Mov bx, cseg:2Ch : segment name and offset
Mov ax,es:count ; segment register and variable
Relocatable operands are more common. Their location depends on the offset os a lable
from the beginning of a segment. The following segment registers are used by default:
Type of Lable Defalut Segment Register
Program code(instructions) CS
Variables(data) DS

The ES register usually addresses variables, but it can contain the base location of any
segment.

Indirect Addressing Mode

Indirect operands use registers to point to locations in memory. If a register is
used in this way, we can change its value and access different memory locations at
runtime. Two types of registers are used: base register(BX, BP) and index registers(SI,
DI). BP is assumed to contain an offset from the stack segment. SI, DP, and BX contain
offsets from DS, the data segment register.
There are five indirect addressing modes, identified by the types of operands
used:
Addressing Mode Example
Register indirect [bx]
Based table[bx]
Indexed table[si]
Based indexed [bx + si]
Based indexed with displacement [bx + si + 2]

Register Indirect: Indirect operands are particularly powerful when processing lists
of arrays, because a base or indeedx register may be modified at runtime. In the following
example, BX points to two different array elements:
Mov bx, offset array ; point to start of array
Mov al,[bx] ;get first element
Inc bx ; point to next
` mov dl,[bx]
…
…/
Array db 10h,20h, 30h
In the following example, the three bytes in array are added together:
Mov si,offset array ;address of first byte
Mov al,[si] ;move the first byte to AL
Inc si ;point to next byte
Add al,[si] ;add second byte
Inc si
Add al,[si] ;add third byte
Inc si
…
…
Array db 10h,20h,30h
Operation Systems

IT (2014)

for

Second Semester

Sample Question
1. What requirements is memory management intended to satisfy? Discuss ANY
THREE. (20 marks)
2. (a)Discuss about logical organization and physical organization. (20 marks)
(b)Define Best-Fit, First-Fit and Next-Fit. (5 marks)
3. (a) Discuss about the buddy system. (10 marks)
(b) In a fixed-partitioning scheme, what are the advantages and disadvantages of
using unequal-size partitioning? (10 marks)
4. Describe memory management techniques and compare strengths and
weaknesses of these techniques. (20 marks)
5. (a) A 1-Mbyte block of memory is allocated using the buddy system.
(i) Show the results of the following sequence.
Request 70; Request 35; Request 80; Return A; Request 60; Return B; Return
D; Return C;
(ii) Show the binary tree representation following Return B. (10 marks)
(b) Describe the two difficulties with the use of equal-size fixed partitions.
(10 marks)
6. (a) Define First-fit, Best-fit, and Next-fit.
A dynamic partitioning scheme is being used, and the following is the memory
configuration at a given point in time.
20M 20M 40M 60M 20M 10M 60M 40M 20M 30M 40M 40 M

The shaded areas are allocated blocks; the white areas are free blocks. The next
three memory requests are for 40M, 20M, and 10M. Indicate the starting address
for each of the three blocks using the following placement algorithms:
First-fit, Best-fit, Next-fit
Assume the most recently added block is at the beginning of memory.
(10 marks)
6. (b) List and briefly define three versions of load sharing in multiprocessor
scheduling. (10 marks)
7. (a) What elements are typically found in a page table entry?
Briefly define each element. (10 marks)
(b) Explain Trashing. (5 marks)
8. (a) Draw the flowchart to show the use of Translation Lookaside Buffer (TLB).
(10 marks)
(b) Describe the advantages of segmentation to the programmer over a non-
segmented address space. (10 marks)
9. (a) Briefly define the alternative page fetch policies. (10 marks)
(b) What is the difference between Demand Cleaning and Precleaning.
(5 marks)
10. Define Optimal, LRU, FIFO, Clock Policy and illustrates the behavior of Four
Page Replacement Algorithms by using these page address stream.
232152453252 (20 marks)
11. (a) Define Associated Mapping and illustrate Direct Versus Associative Lookup
for Page Table Entries. (10 marks)
 (b) Illustrate Address Translation in a Segmentation/Paging System. (10 marks)
12. (a) What is the purpose of Translation Lookaside Buffer and explain with
illustration. (10 marks)
(b) Illustrate Translation Lookaside Buffer and Cache Operation.
(10 marks)
13. (a) Briefly define round-robin scheduling.
(10 marks)
(b) What is the difference between turnaround time and response time?
(5 marks)
14. (a) Briefly define shortest-process-next scheduling. (10 marks)
(b) Briefly define feedback scheduling. (10 marks)
15. Compute Finish Time, Turnaround Time (Tr), Tr / Ts and Mean for FCFS, RR (
q=1 and q=4 ), SPN scheduling policies. Then illustrate a comparison of these
scheduling policies.
Process A B C D E
Arrival Time 0 2 4 6 8
Service Time (Tr) 3 6 4 5 2
(20 marks)
16. (a) Compute Finish Time, Turnaround Time (Tr), Tr / Ts and Mean for SRT,
Feedback ( q=1 and q=2i ) scheduling policies. Then illustrate a comparison of these
scheduling policies.
Process A B C D E
Arrival Time 0 2 4 6 8
Service Time (Tr) 3 6 4 5 2
(10 marks)
(b) What are the three types of uniprocessor scheduling. Briefly explain them.
(5 marks)
17. List and explain five general areas of requirements for a real-time operating
system. (20 marks)
18. (a) List and briefly define four techniques for thread scheduling.
(10marks)
(b) Illustrate about Address Translation in a Segmentation/Paging System.
(10 marks)
 1

Operating Systems

IT (2014)

for

Second Semester

Sample Answer & Question

 2

1. What requirements is memory management intended to satisfy? Discuss ANY

THREE. (20 marks)
There are five requirements that memory management is intended to satisfy. They
are:
Relocation
Protection
Sharing
Logical organization
Physical organization

Relocation:
In a multiprogramming system, the available main memory is generally shared
among a number of processes. Typically, it is not possible for the programmer to know in
advance which other programs will be resident in main memory at the time of execution
of his or her program. In addition, we will like to be able to swap active processes in and
out of main memory to maximize processor utilization by providing a large pool of ready
processes to execute. Once a program has been swapped out to disk, it would be quite
limiting to declare that when it is next swapped back in, it must be placed in the same
main memory region as before. Instead, we may need to relocate the process to a different
area of memory.

Protection:
Each process should be protected against unwanted interference by other
processes whether accidental or intentional. Because the location of a program in main
memory is unpredictable, it is impossible to check absolute addresses at compile time to
assure protection. Furthermore, most programming languages allow the dynamic
calculation of addresses at run time. Hence all memory references generated by a process
must be checked at run time to ensure that they refer only to the memory space allocated
to that process. The memory protection requirement must be satisfied by the process
(hardware) rather than the operating system (software).

Sharing:
Any protection mechanism must have the flexibility to allow several processes to
access the same portion of main memory. For example, if a number of processes are
executing the same program, it is advantageous to allow each process to access the same
copy of the program rather than have its own separate copy.

Logical Organization:
Main memory in a computer system is organized as a linear, or one-dimensional,
address space. Secondary memory is similarly organized. It does not correspond to the
way in which programs are typically constructed. Most programs are organized into
modules. A number of advantages can be realized:
1. Modules can be written and compiled independently, with all references from one
module to another resolved by the system at run time.
2. With modest additional overhead, different degrees of protection (read only,
execute only) can be given to different modules.
3. It is possible to introduce mechanisms by which modules can be shared among
processes.
The tool that most readily satisfies these requirements is segmentation, which is
one of the memory-management techniques.
 3

Physical Organization:
Computer memory is organized into at least two levels, main memory and
secondary memory. Main memory provides fast access at relatively high cost. It is
volatile. Secondary memory is slower and cheaper than main memory and is usually not
volatile. Thus secondary memory can be provided for long-term storage of programs and
data, main memory holds programs and data currently in use.
The flow of information between main and secondary memory is a major system
concern. The responsibility for this flow could be assigned to the individual programmer,
but his is impractical and undesirable for two reasons:
1. The main memory available for a program plus its data may be insufficient. In that
case, the programmer must engage in a practice known as overlaying, in which the
program and data are organized in such a way that various modules can be
assigned the same region of memory, with a main program responsible for
switching the modules in an out as needed. Even with the aid of compiler tools,
overlay programming wastes programmer time.
2. In a multiprogramming environment, the programmer does not know tat he time
of coding how much space will be available or where that space will be.
The task of moving information between the two levels of memory should be a
system responsibility.

2. (a)Discuss about logical organization and physical organization. (20 marks)

Logical Organization:
Main memory in a computer system is organized as a linear, or one-dimensional,
address space. Secondary memory is similarly organized. It does not correspond to the
way in which programs are typically constructed. Most programs are organized into
modules. A number of advantages can be realized:
4. Modules can be written and compiled independently, with all references from one
module to another resolved by the system at run time.
5. With modest additional overhead, different degrees of protection (read only,
execute only) can be given to different modules.
6. It is possible to introduce mechanisms by which modules can be shared among
processes.
The tool that most readily satisfies these requirements is segmentation, which is
one of the memory-management techniques.

Physical Organization:
Computer memory is organized into at least two levels, main memory and
secondary memory. Main memory provides fast access at relatively high cost. It is
volatile. Secondary memory is slower and cheaper than main memory and is usually not
volatile. Thus secondary memory can be provided for long-term storage of programs and
data, main memory holds programs and data currently in use.
The flow of information between main and secondary memory is a major system
concern. The responsibility for this flow could be assigned to the individual programmer,
but his is impractical and undesirable for two reasons:
3. The main memory available for a program plus its data may be insufficient. In that
case, the programmer must engage in a practice known as overlaying, in which the
program and data are organized in such a way that various modules can be
assigned the same region of memory, with a main program responsible for
 4

switching the modules in an out as needed. Even with the aid of compiler tools,
overlay programming wastes programmer time.
4. In a multiprogramming environment, the programmer does not know tat he time
of coding how much space will be available or where that space will be.
The task of moving information between the two levels of memory should be a
system responsibility.

2. (b) Define Best-Fit, First-Fit and Next-Fit. (5 marks)

Best-fit chooses the block that closet in size to the request.
First-fit begins to scan memory from the beginning and chooses the first available
block that is large enough.
Next-fit begins to scan memory from the location of the last placement, and
chooses the next available block that is large enough.

3. (a) Discuss about the buddy system. (10 marks)

In a buddy system, memory blocks are available of size 2K, L ≤ K ≤ U , where
2L = smallest size block that is allocated
2U = largest size block that is allocated; generally 2U is the size of the entire
memory available for allocation
To begin, the entire space available for allocation is treated as a single block of
size 2U. If a request of size s such that 2U-1 < s ≤ 2U is made, then the entire block is
allocated. Otherwise, the block is split into two equal buddies of size 2U-1.
If 2U-2 <s ≤ 2U-1, then the request is allocated to one of the two buddies.
Otherwise, one of the buddies is split in half again. This process continues until the
smallest block greater than or equal to s is generated and allocated to the request.

3. (b) In a fixed-partitioning scheme, what are the advantages and disadvantages of

using unequal-size partitioning? (10 marks)
The advantage of unequal-size partitions is that processes are always assigned in
such a way as to minimize wasted memory within a partition (internal fragmentation).
The use of unequal-size partitions provides a degree of flexibility to fixed
partitioning. In addition it can be said that fixed-partitioning schemes are relatively
simple and require minimal operating system software and processing overhead.
There are disadvantages:
The number of partitions specified at system generation time limits the number of
active (not suspended) processes in the system.
Because partition sizes are preset at system generation time, small jobs will not
utilize partition space efficiently. In an environment where the main storage requirement
of all jobs is known beforehand, this may be reasonable, but in most cases, it is an
inefficient technique.

4. Describe memory management techniques and compare strengths and weaknesses

of these techniques. (20 marks)

Technique Description Strengths Weakness

 5

Inefficient use of
Main memory is divided into a
memory due to internal
number of static partitions at Simple to implement:
Fixed fragmentation;
system generation time. A process little operating system
Partitioning maximum number of
may be loaded into a partition of overhead.
active processes is
equal or greater size.
fixed.

Inefficient use of
Partitions are created dynamically,
No internal fragmentation: processor due to the
Dynamic so that each process is loaded into a
more efficient use of main need for compaction to
Partitioning partition of exactly the same size as
memory. counter external
that process.
fragmentation.

Main memory is divided into a

number of equal-size frames. Each
process is divided into a number of
Simple equal-size pages of the same length No external A small amount of
Paging as frames. A process is loaded by fragmentation. internal fragmentation.
loading all of its pages into
available, not necessarily
contiguous, frames.

Each process is divided into a No internal fragmentation;

number of segments. A process is improved memory
Simple
loaded by loading all of its utilization and reduced External fragmentation.
Segmentation
segments into dynamic partitions overhead compared to
that need not be contiguous. dynamic partitioning.

As with simple paging, except that No external

Virtual- it is not necessary to load all of the fragmentation; higher
Overhead of complex
Memory pages of a process. Nonresident degree of
memory management.
Paging pages that are needed are brought multiprogramming; large
in later automatically. virtual address space.

As with simple segmentation, No internal fragmentation,

except that it is not necessary to higher degree of
Virtual-
load all of the segments of a multiprogramming; large Overhead of complex
Memory
process. Nonresident segments that virtual address space; memory management.
Segmentation
are needed are brought in later protection and sharing
automatically. support.

5. (a) A 1-Mbyte block of memory is allocated using the buddy system.

(i) Show the results of the following sequence.
Request 70; Request 35; Request 80; Return A; Request 60; Return B; Return
D; Return C;
(ii) Show the binary tree representation following Return B.
(10 marks)
 6

1M

A-Request 70 A=128 K 128 256 K 512 K

B-Request 35 A=128 K B=64 64 256 K 512 K

C-Request 80 A=128 K B=64 64 C=128 128 512 K

Return A 128 K B=64 64 C=128 128 512 K

D-Request 60 128 K B=64 D=64 C=128 128 512 K

Return B 128 K 64 D=64 C=128 128 512 K

Return D 256 K C=128 128 512 K

Return C 1M

(i) Figure. Buddy System Memory Allocation

1M

512 M

256 M

128 M

64 M

128 K 64 D=64 C=128 128 512 K

(ii) Figure. Tree Representation of Buddy System

5. (b) Describe the two difficulties with the use of equal-size fixed partitions.
(10 marks)
The two difficulties with the use of equal-size fixed partitions are as follows;
(i) A program may be too big to fit into a partition. In this case, the programmer must
design the program with the use of overlays so that only a portion of the program need be
in main memory at any one time. When a module is needed that is not present, the user’s
 7

program must load that module into the program’s partition, overlaying whatever
programs or data are there.
(ii) Main memory utilization is extremely inefficient. Any program, no matter how small,
occupies an entire partition. For example, assume that there are fixed partitions with the
size of whose length is less than 2 Mbytes; yet it occupies an 8-Mbytes partition
whenever it is swapped in. This phenomenon, in which there is wasted space internal to a
partition due to that fact that the block of data loaded is smaller than the partition, is
referred to as internal fragmentation.

6. (a) Define First-fit, Best-fit, and Next-fit.

A dynamic partitioning scheme is being used, and the following is the memory
configuration at a given point in time.
20M 20M 40M 60M 20M 10M 60M 40M 20M 30M 40M 40 M

The shaded areas are allocated blocks; the white areas are free blocks. The next
three memory requests are for 40M, 20M, and 10M. Indicate the starting address
for each of the three blocks using the following placement algorithms:
First-fit, Best-fit, Next-fit
Assume the most recently added block is at the beginning of memory.
(10 marks)

First-Fit : First-fit begins to scan memory from the beginning and chooses the first
available block that is large enough.
Requests; 40 M, 20 M, 10 M

20M 40M 10M

20M 20M 40M 60M 20M 10M 60M 40M 20M 30M 40M 40 M

Best-Fit : Best-fit chooses the block that closet in size to the request.
Requests; 40 M, 20 M, 10 M

20M 10M 40M

20M 20M 40M 60M 20M 10M 60M 40M 20M 30M 40M 40 M

Next-Fit : Next-fit begins to scan memory from the location of the last placement, and
chooses the next available block that is large enough.
Requests; 40 M, 20 M, 10 M

40M 20M 10M

20M 20M 40M 60M 20M 10M 60M 40M 20M 30M 40M 40 M
 8

6. (b) List and briefly define three versions of load sharing in multiprocessor
scheduling. (10 marks)

Three different versions of load sharing are First come first served (FCFS),
Smallest number of threads first, Preemptive smallest number of threads first.

First come First served (FCFS): When a job arrives, each of its threads is placed
consecutively at the end of the shared queue. When a processor becomes idle, it picks the
next ready thread, which it executes until completion or blocking.
Smallest number of threads first: The shared ready queue is organized as a priority
queue, with highest priority given to threads from jobs with the smallest number of
unscheduled threads. Jobs of equal priority are ordered according to which job arrives
first. As with FCFS, a scheduled thread is run to completion or blocking.
Preemptive smallest number of threads first: Highest priority is given to jobs with the
smallest number of unscheduled threads. An arriving job with a smaller number of
threads than an executing job will preempt threads belonging to the scheduled job.

7. (a) What elements are typically found in a page table entry?

Briefly define each element. (10 marks)

Each entry in the page table includes the following:

Page number: This is the page number portion of the virtual address.
Process identifier: The process that owns this page. The combination of page number
and process identifier identify a page within the virtual address space of a particular
process.
Control bits: This field includes flags, such as valid, referenced, and modified; and
protection and locking information.
Chain pointer: This field is null (perhaps indicated by a separate bit) if there are no
chained entries for this entry. Otherwise, the field contains the index value (number
between 0 and 2m-1) of the next entry in the chain.

Virtual address
n bits
Page# Offset Control bits
Process
Page# ID Chain
n bits 0

Hash m bits i
Function

Inverted page table (one entry for each

physical memory frame)
Frame# Offset
m m bits
2 -1
Figure. Inverted Page Table structure Real address

7. (b) Explain Trashing. (4 marks)

 9

Thrashing:
When the operating system brings one piece in, it must throw another out. If it
throws out a piece just before it is used, then it will just have to go get that piece again
almost immediately. Too much of this leads to a condition known as thrashing.

8. (a) Draw the flowchart to show the use of Translation Lookaside Buffer (TLB).
(10 marks)
Return to faulted
instruction
Start

CPU checks the TLB

Page table Yes

entry in
TLB?

No
Access page table

OS Instructs CPU Page in

No
to read the page main
from disk memory?

CPU actives I/O Yes

hardware Update TLB

Page transferred
from disk to
CPU generates
main memory
physical address

Yes
Memory full?

No Perform page
replacement

Page tables
updated

Figure. Operation of Paging and Translation Lookaside Buffer (TLB)

8. (b) Describe the advantages of segmentation to the programmer over a non-

segmented address space. (10 marks)

A number of advantages to the programmer over a non-segmented address space:

1. It simplifies the handling of growing data structures. If the programmer does not know
ahead of time how large a particular data structure will become, it is necessary to guess
 10

unless dynamic segment sizes are allowed. With segmented virtual memory, the data
structure can be assigned its own segment, and the operating system will expand or shrink
the segment as needed. If a segment that needs to be expanded is in main memory and
there is insufficient room, the operating system may move the segment to a larger area of
main memory, if available, or swap it out. In the latter case, the enlarged segment would
be swapped back in at the next opportunity.
2. It allows programs to be altered and recompiled independently, without requiring the
entire set of programs to be relinked and reloaded. Again, this is accomplished using
multiple segments.
3. It lends itself to sharing among processes. A programmer can place a utility program or
a useful table of data in a segment that can be referenced by other processes.
4. It lends itself to protection. Because a segment can be constructed to contain a well-
defined set of programs or data, the programmer or system administrator can assign
access privileges in a convenient fashion.

9. (a) Briefly define the alternative page fetch policies.

(10 marks)
The fetch policy determines when a page should be brought into main memory.
The two common alternatives are demand paging and prepaging. With demand paging, a
page is brought into main memory only when a reference is made to a location on that
page. If the other elements of memory-management policy are good, the following should
happen. When a process is first started, there will be a flurry of page faults. As more and
more pages are brought in, the principle of locality suggests that most future references
will be to pages that have recently been brought in. Thus, after a time, matters should
settle down and the number of page faults should drop to a very low level.
With prepaging, pages other than the one demanded by a page fault are brought in.
Prepaging exploits the characteristics of most secondary memory devices, such as disks,
which have seek times and rotational latency. If the pages of a process are stored
contiguously in secondary memory, then it is more efficient to bring in a number of
contiguous pages at one time rather than bringing them in one at a time over an extended
period. Of course, this policy is ineffective if most of the extra pages that are brought in
are not referenced.
The prepaging policy could be employed either when a process first starts up, in
which case the programmer would somehow have to designate desired pages, or every
time a page fault occurs. This latter course would seem preferable because it is invisible
to the programmer. However, the utility of prepaging has not been established.
Prepaging should not be confused with swapping. When a process is sapped out of
memory and put in a suspended state, all of its resident pages are moved out. When the
process is resumed, all of the pages that were previously in main memory are returned to
main memory.

9. (b) What is the difference between Demand Cleaning and Precleaning.

(5 marks)
With demand cleaning, a page is written out to secondary memory only when it
has been selected for replacement. A precleaning policy writes modified pages before
their page frames are needed so that pages can be written out in batches.

10. Define Optimal, LRU, FIFO, Clock Policy and illustrates the behavior of Four
Page Replacement Algorithms by using these page address stream.
232152453252 (20 marks)
 11

Basic replacement algorithms are;

Optimal
Least recently used (LRU)
First-in-first-out (FIFO)
Clock
The optimal policy selects for replacement that page for which the time to the next
reference is the longest. It can be shown that this policy results in the fewest number of
page faults. Clearly, this policy is impossible to implement, because it would require the
operating system to have perfect knowledge of future events. However, it does serve as a
standard against which to judge real-world algorithms.
The least recently used (LRU) policy replaces the page in memory that has not
been referenced for the longest time. By the principle of locality, this should be the page
least likely to be referenced in the near future. And, in fact, the LRU policy does nearly as
well as the optimal policy. The problem with this approach is the difficulty in
implementation. One approach would be to tag each page with the time of its last
reference; this would have to be done at each memory reference, both instruction and
data. Even if the hardware would support such a scheme, the overhead would be
tremendous. Alternatively, one could maintain a stack of page references, again an
expensive prospect.
The first-in-first-out (FIFO) policy treats the page frames allocated to a process as
a circular buffer, and pages are removed in round-robin style. All that is required is a
pointer that circles through the page frames of the process. This is therefore one of the
simplest page replacement policies to implement.
The simplest form of clock policy requires the association of an additional bit with
each frame, referred to as the use bit. When a page is first loaded into a frame in memory,
the use bit for that frame is set to 1.

FIGURE 8.15 Behavior of Four Page Replacement Algorithms

(page 356)

11. (a) Define Associated Mapping and illustrate Direct Versus Associative Lookup
for Page Table Entries. (10 marks)

Because the TLB only contains some of the entries in a full page table, we cannot
simply index into the TLB based on page number. Instead, each entry in the TLB must
include the page number as well as the complete page table entry. The processor is
equipped with hardware that allows it to interrogate simultaneously a number of TLB
entries to determine if there is a match on page number. This technique is referred to as
associative mapping.

FIGURE 8.9 Direct Versus Associative Lookup for Page Table Entries
(page 344)
 12

11. (b) Illustrate Address Translation in a Segmentation/Paging System.

(10 marks)

FIGURE 8.13 Address Translation in a Segmentation/Paging System

(page 350)

12. (a) What is the purpose of Translation Lookaside Buffer and explain with
illustration. (10 marks)
In principle, every virtual memory reference can cause two physical memory
accesses: one to fetch the appropriate page table entry and one to fetch the desired data.
Thus, a straightforward virtual memory scheme would have the effect of doubling the
memory access time. To overcome this problem, most virtual memory schemes make use
of a special high-speed cache for page table entries, usually called a translation lookaside
buffer (TLB).

FIGURE 8.7 Use of Translation Lookaside Buffer

(page 342)

12. (b) Illustrate Translation Lookaside Buffer and Cache Operation.

(10 marks)

FIGURE 8.10 Translation Lookaside Buffer and Cache Operation

(page 345)

13. (a) Briefly define round-robin scheduling.

(10 marks)
A straightforward way to reduce the penalty that short jobs suffer with FCFS is to
use preemption based on a clock. The simplest such policy is round robin. A clock
interrupt is generated at periodic intervals. When the interrupt occurs, the currently
running process is placed in the ready queue, and the next ready job is selected on a FCFS
basis. This technique is also known as time slicing, because each process is given a slice
of time before being preempted.
With round robin, the principal design issue is the length of the time quantum, or
slice, to be used. If the quantum is very short, then short processes will move through the
system relatively quickly. On the other hand, there is processing overhead involved in
handling the clock interrupt and performing the scheduling and dispatching function.
Thus, very short time quanta should be avoided. One useful guide is that the time
 13

quantum should be slightly greater than the time required for a typical interaction or
process function.
Round robin is particularly effective in a general-purpose time-sharing system or
transaction processing system. One drawback to round robin is its relative treatment of
processor-bound and I/O-bound processes.

FIGURE 9.7 Queuing Diagram for Virtual Round-Robin Scheduler

(page 406)

13. (b) What is the difference between turnaround time and response time?
(5 marks)
Turnaround time: This is the interval of time between the submission of a process and
its completion. Include actual execution time plus time spent waiting for resources,
including the processor. This is an appropriate measure for a batch job.

Response time: For an interactive process, this is the time from the submission of a
request until the response begins to be received. Often a process can begin producing
some output to the user while continuing to process the request. Thus, this is a better
measure than turnaround time from the user’s point of view. The scheduling discipline
should attempt to achieve low response time and to maximize the number of interactive
users receiving acceptable response time.

14. (a) Briefly define shortest-process-next scheduling.

(10 marks)
Shortest-Process-Next (SPN):
Another approach to reducing the bias in favor of long processes inherent in FCFS
is the Shortest Process Next (SPN) policy. This is a nonpreemptive policy in which the
process with the shortest expected processing time is selected next. Thus a short process
will jump to the head of the queue past longer jobs.
One difficulty with the SPN policy is the need to know or at least estimate the
required processing time of each process. The simplest calculation would be the
following:
1 n
Sn+1 = ∑ Ti
n i =1
Where
Ti = processor execution time for the ith instance of this process
Si = predicted value for the ith instance
S1 = predicted value for first instance, not calculated.

14. (b) Briefly define feedback scheduling.

(10 marks)
If we have no indication of the relative length of various processed. Then none of
SPN, SRT, and HRRN can be used. Another way of establishing a preference for shorter
jobs is to penalize jobs that have been running longer.
 14

Figure illustrates the feedback scheduling mechanism by showing the path that a
process will follow through the various queues. This approach is know as multilevel
feedback, meaning that the operating system allocates the processor to a process and,
when the process blocks or is preempted, feeds it back into one of several priority queues.

FIGURE 9.10 Feedback Scheduling

(page 412)

15. Compute Finish Time, Turnaround Time (Tr), Tr / Ts and Mean for FCFS, RR (
q=1 and q=4 ), SPN scheduling policies. Then illustrate a comparison of these
scheduling policies.
Process A B C D E
Arrival Time 0 2 4 6 8
Service Time (Tr) 3 6 4 5 2
(20 marks)

Process A B C D E

Arrival Time 0 2 4 6 8

Service Time (Ts) 3 6 4 5 2 Mean

Finish Time 3 9 13 18 20

FCFS Turnaround Time(Tr) 3 7 9 12 12 8.60

Tr / Ts 1.00 1.17 2.25 2.40 6.00 2.56

Finish Time 4 18 17 20 15

RR (q=1) Turnaround Time(Tr) 4 16 13 14 7 10.80

Tr / Ts 1.33 2.67 3.25 2.80 3.50 2.71

Finish Time 3 17 11 20 19
.
RR (q=4) Turnaround Time(Tr) 3 15 7 14 11 10.00

Tr / Ts 1.00 2.5 1.75 2.80 5.50 2.71

Finish Time 3 9 15 20 11

SPN Turnaround Time(Tr) 3 7 11 14 3 7.60

Tr / Ts 1.00 1.17 2.75 2.80 1.50 1.84

Table. A comparison of Scheduling Policies

 15

0 5 10 15 20

A
B
First-come-First- C
Served (FCFS) D
E

A
Round-Robin B
C
(RR), q = 1 D
E

A
Round-Robin B
C
(RR), q = 4 D
E

A
Shortest Process B
Next (SPN) C
D
E

Figure. A comparison of Scheduling Policies

16. (a) Compute Finish Time, Turnaround Time (Tr), Tr / Ts and Mean for SRT,
Feedback ( q=1 and q=2i ) scheduling policies. Then illustrate a comparison of these
scheduling policies.
Process A B C D E
Arrival Time 0 2 4 6 8
Service Time (Tr) 3 6 4 5 2
(10 marks)
Table. A Comparison of Scheduling Policies
Process A B C D E

Arrival Time 0 2 4 6 8

Service Time (Ts) 3 6 4 5 2 Mean

Finish Time 3 15 8 20 10

SRT Turnaround Time(Tr) 3 13 4 14 2 7.20

Tr / Ts 1.00 2.17 1.00 2.80 1.00 1.59

Finish Time 4 20 16 19 11

FB(q=1) Turnaround Time(Tr) 4 18 12 13 3 10.00

Tr / Ts 1.33 3.00 3.00 2.60 1.5 2.29

Finish Time 4 17 18 20 14
.
FB(q=2i ) Turnaround Time(Tr) 4 15 14 14 6 10.60

Tr / Ts 1.33 2.50 3.50 2.80 3.00 2.63

 16

0 5 10 15 20

A
B
Shortest Remaining C
Time (SRT) D
E

A
Feedback B
q=1 C
D
E

A
Feedback B
C
q = 2i D
E

Figure. A Comparison of Scheduling Policies

16. (b) What are the three types of uniprocessor scheduling. Briefly explain them.
(5 marks)
The three types of uniprocessor scheduling are;
Long-term scheduling
Medium-term scheduling
Short-term scheduling
Long-term scheduling is performed when a new process is created. This is a
decision whether to add a new process to the set of processes that are currently active.
Medium-term scheduling is a part of the swapping function. This is a decision
whether to add a process to those that are at least partially in main memory and therefore
available for execution.
Short-term scheduling is the actual decision of which ready process to execute
next.

17. List and explain five general areas of requirements for a real-time operating
system. (20 marks)

Real-time operating systems can be characterized as having unique requirements

in five general areas:
Determinism
Responsiveness
User control
Reliability
Fail-soft operation
An operating system is deterministic to the extent that it performs operations at
fixed, predetermined times or within predetermined time intervals. When multiple
processes are competing for resources and processor time, no system will be fully
deterministic. In a real-time operating system, process requests for service are dictated by
 17

external events and timings. The extent to which an operating system can
deterministically satisfy requests depends first on the speed with which it can respond to
interrupts and, second, on whether the system has sufficient capacity to handle all
requests within the required time.
One useful measure of the ability of an operating system to function
deterministically is the maximum delay from the arrival of a high-priority device interrupt
to when servicing begins.
Responsiveness is concerned with how long, after acknowledgment, it takes an
operating system to service the interrupt. Aspects of responsiveness include the
following.
1. The amount of time required to initially handle the interrupt and begin execution of the
interrupt service routine (ISR).
2. The amount of time required to perform the ISR. This generally is dependent on the
hardware platform.
3. The effect of interrupt nesting. If an ISR can be interrupted by the arrival of another
interrupt, then the service will be delayed.
User control is generally much broader in a real-time operating system than in
ordinary operating systems. In a real-time system, it is essential to allow the user fine-
grained control over task priority. The user should be able to distinguish between hard
and soft tasks and to specify relative priorities within each class. A real-time system may
also allow the user to specify such characteristics as the use of paging or process
swapping, what processes must always be resident in main memory, what disk transfer
algorithms are to be used, what rights the processes in various priority bands have, and so
on.
Reliability is typically far more important for real-time systems than non-real-time
systems. A real-time system is responding to and controlling events in real time. Loss or
degradation of performance may have catastrophic consequences, ranging from financial
loss to major equipment damage and even loss of life.
Fail-soft operation is a characteristic that refers to the ability of a system to fail in
such a way as to preserver as much capability and data as possible. A real-time system
will attempt either to correct the problem or minimize its effects while continuing to run.
Typically, the system notifies a user or user process that it should attempt corrective
action and then continues operation perhaps at a reduced level of service. In the event a
shutdown is necessary, an attempt is made to maintain file and data consistency.

18. (a) List and briefly define four techniques for thread scheduling.
(10marks)
For multiprocessor thread scheduling and processor assignment, four general
approaches stand out:
Load sharing
Gang scheduling
Dedicated processor assignment
Dynamic scheduling
1. Load sharing:
Processes are not assigned to a particular processor. A global queue of ready
threads is maintained, and each processor, when idle, selects a thread from the queue. The
term load sharing is used to distinguish this strategy from load balancing schemes in
which work is allocated on a more permanent basis.
 18

2. Gang scheduling:
A set of related threads is scheduled to run on a set of processors at the same time,
on a one-to-one basis.
3. Dedicated processor assignment:
This is the opposite of the load-sharing approach and provides implicit scheduling
defined by the assignment of threads to processors. Each program is allocated a number
of processors equal to the number of threads in the program, for the duration of the
program execution. When the program terminates, the processors return to the general
pool for possible allocation to another program.
4. Dynamic scheduling:
The number of threads in a process can be altered during the course of execution.

18. (b) Illustrate about Address Translation in a Segmentation/Paging System. (10

marks)

FIGURE 8.13 Address Translation in a Segmentation/Paging System

(page 350)
Software Engineering

IT 2015

For

Second Semester

Sample Question
1. A stack is a data storage device that are the last item stored is the first retrieved. Write
a program to test input and output of the stack. (20 marks)
2. Create string class that include a string str (an array of char) to concat of two string and
test it. (20 marks)
3. Write a function called reversit ( ) that reverses a string (an array of char). Use a for
loop that swaps a string firs and last characters, and so on. The string should be passed to
reversit ( ) as an argument. Write a program to exercise reversit ( ). The program should
get a string from the user call reversit ( ), and print out the result. Use an input method
that allows embedded blanks. (20 marks)
4. Create a class called employee that contains a name (an array of char) and employee
member (long). Include a member function called getdata( ) to get data from the user and
another function called putdata ( ) to display the data. Write a main ( ) program to
exercise this class. It should create an array of type employee and then input 100
employee. Finally it should print out the data for all the employees.
(20 marks)
5. A queue is a data storage divide like a stack. The difference is that in a stack the last
data item stored is the first one retrieved, while in a queue the First data item stored is the
first retrieved. Use two pointers, FRONT for retrieve and RARE for entry. The member
function push ( ) should include overflow checking and pop ( ) should include underflow
checking. Write a main ( ) program to implement a queue and test it.(10 marks)
6. To the Distance class, add on overloaded operator that subtracts two distance like dist
3 = dist 1 – dist 2. Assume that operator will never be used to subtract a longer number
from a smaller one. (20 marks)
7. To the Distance class, add an overloaded operator that add two distance like dist 1 +=
dist 2. (20 marks)
8. To the Distance class, add an overloaded operator that dis1 < dist2.
(20 marks)
9. Write a program the conversion of distance to meter, meter to Distance. (20 marks)
10. Create the time class with integer members (hours, minutes, seconds) and include
overloaded increment (++) and decrement (--) operators that operate in both prefix and
postfix notation and return value. Write a main program to test the above time calss.
(20 marks)
11. Create a class Int that contain an integer variable. Overload all five integer arithmetic
operators (+, -, *, /, %). So that they operate an object of type Int. If the result of any such
operation exceeds the normal range of int from -32768 to 32767, the operator prints a
warning and terminate the program. Write a program to test this class.
(20 marks)
12. Create the polar class to incorporate overloaded operators for multiplication and
division that require a constant (type double) as the second operand, not a polar. Write a
program to exercise all these operations with a variety of values.
( 20 marks)
13. Write a program to implement their hierarchy diagram. ( 20 marks)
 Class Employee
name;
number;

Class Scientist
Class manager Class laborer
title; publications
dues;

One- to – many class hierarchy

14. Write a program to implement their hierarchy diagram. (20 marks)

Class employee Class student

name (string) School (string)
number(int) degree(string)

class laborer class scientists class manager

pubs(int) title (string)
dues(double)

many – to many class hierarchy

15. Create a student class that includes the member data number (int) and marks of four
papers (ints). The member function are get-student ( ) to get student data and display ( )
to display the object details. The grade class also include the member data roll number
(int) and grade value (char) and the member function where a conversion function from
student class to grade class and a display function. The conversion condition are as
follow:
(i) Average of paper marks >= 75, grade = ‘A’
(ii) Average of paper marks < 75 and >= 65, grade ‘B’
(iii) Average of paper marks < 65 and > = 40, grade ‘C’
Write a program to create two different objects and test the conversion.

(20 marks)
16. Create the Type class which store dimension (string) grade (string) and Distance class
which store ft (int), in (float). From the type and Distance class derived class called
lumber that contain qty (int) price4 float. Implement main program and test it.
(20 marks)
17. Create a class publication that stores the title ( a string ) and price (type float). From
this class derive two classes: book which adds a page count (type int) and tape, which
adds a playing time in minutes (type float). Each of these three classes should have a
getdata ( ) function to get is data from the user and a putdata ( ) function to display its
data. Write a main ( ) program to implement this class. (20 marks)
18. A company rents both cars and trucks. A class transport stores the capacity (int), the
status (rented as available) and the cost of rental ( a float). From this class (derived car
class that include number of passengers and) three count ( an int); and truck which adds a
load limit measured in matric tones (an int). Each of these three classes should have a
getdata ( ) function to obtain data from user and a showdata ( ) function to display data on
the screen. Implement these three classes and write a main ( ) program to test a car and
truck classes. (20 marks)

19. Create a class publication that stores the title (string) and price (float) and sale class
that holds an array of three float. The book and tape that they are derived from
publication and sale. Add a disk class that like book and tape, is derived from publication.
The disk class should incorporate the same member functions as the other classes. The
data item unique to this class is the disk size: either 3-1/2 inches or 5-1/4 inches. You can
use an enum Boolean type to store this item, but the complete size should be displayed.
The user could select the appropriate size by typing 3 or 5. (20 marks)

20. Start with the publication, book and tape classes. Suppose you want to add the date of
publication for both books and tapes. From the publication class, derived a new class so
called publication 2 that includes this member data. Then change book and tape so they
are derived from publication 2 instead of publication. Make all the necessary changes in
member functions to the user can input and output data along with the other data. For the
data class, use three ints of months, day and year. The member functions are getdata ( )
and showdata ( ). (20 marks)
21.Create a linklist program using pointer. Add a destructor to the linklist program. It
should delete all the links when a linklist object is destroyed. It can to this by following
along the chain, deleting each link as it goes. You can test the destructor by having it
display a message each time it deletes a link; it should delete the same number of links
that were added to the list. (20 marks)
22. Revise the additem ( ) member functions from the linklist program so that it adds the
item at the end of the list, rather than the beginning. This will cause the first item inserted
to be the first item displayed. To add the item you will need to follow the chain of
pointers to the end of the list, then change the last link to point to the new link.
(20 marks)
23. Create an employee class that certain name, number and student class that holds
school, degree, the manager class that are derived from employee and student’s class.
That certain title (string), class (double). From the manager class derive a class called
executive. The additional data in executive class will be the size of the employee’s yearly
bonus and the number of shares of company stock held in his or her stock option plan.
Add the appropriate member functions so these data items can be input and display along
with the other manager data. (20 marks)
24. Define the following. (20 Marks)
25. Explain system design with diagram. (10 marks)
26. Explain about the following types of software process model.(10 Marks)
 Software Engineering

IT 2015

For

Second Semester

Sample Answer & Question

1. A stack is a data storage device that are the last item stored is the first retrieved. Write
a program to test input and output of the stack. (20 marks)

# include < iostream. h>

# define max 5
class stack
{ private : int st [max ];
int top ;
public : stack ( )
{ top = -1;}
void push ( int n )
{ st [ + + top ] = n; }
void pop ( )
{ cout << st [ top -- ] ; }
};
void main ( )
{ stack s ;
S. puch ( 11 );
S. puch ( 22 );
S. puch ( 33 );
S . pop ( );
S . pop ( );
S . pop ( );
}

2. Create string class that include a string str (an array of char) to concat of two string and
test it. (20 marks)
# include < iostream .h>
# include < string . h >
Class string
{
Private:
char st[50];
Public:
String(){st[0]='\0';}
String(char s[]) {strcpy(st,s);}
Void show()
{cout<<"string="<<st;}
Void concat(string s1)
{ if ((strlen(st)+strlen(s1.st))<50)
Strcat(st,s1.st);
Else
Cout<<"string is too long";
}
};
Void main()
{ string s1("Merry Christismas");
 String s2(" How are you?");
s1.concat(s2);
s1.show();
}

3. Write a function called reversit ( ) that reverses a string (an array of char). Use a for
loop that swaps a string firs and last characters, and so on. The string should be passed to
reversit ( ) as an argument. Write a program to exercise reversit ( ). The program should
get a string from the user call reversit ( ), and print out the result. Use an input method
that allows embedded blanks. (20 marks)

# include < iostream .h>

# include < string . h >
# define max ( )
void reversit ( char s [ ] );
void main ( )
{ char st [ max ];
cout << “Enter string”;
cin.getline ( st, max );
reversit ( st ) ;
cout << “After reversit” << st;
}
void reversit ( char s [ ] )
{ int p, n;
char temp;
n = strlen ( s );
for ( i =0 ; i < n/2; i+ + )
{ temp = s [ i ] ;
s [ i ] = s [ n- 1 – i ];
S [ n-1-i ] = temp;
}
}

4. Create a class called employee that contains a name (an array of char) and employee
member (long). Include a member function called getdata( ) to get data from the user and
another function called putdata ( ) to display the data. Write a main ( ) program to
exercise this class. It should create an array of type employee and then input 100
employee. Finally it should print out the data for all the employees.
(20 marks)

# include <iostream.h>
# include <conio .h>
class employee
{
 private :
char name [20];
long eno;
public:
void getdata( )
{
cout<< “ \n Enter employee name.”;
cin.getline (name ,20);
cout<< “ \n Enter employee number;”
cin>>eno;
}

void putdata( )
{
cout<< “ \n Employee name:”<<name;
cout<< “ \n Employee number;”<<eno;
}
}
void main( )
{
employee e[100];
int I;
for (i=0;i<100;i+ +)
{
cout<< “ \n Enter employee name and number”;
e[i].getdata( );
}
for(i=0;i<100;i + +);
{
cout<< “\n Employee name and number: \n”;
e[i].putdata( );
}
getch( );
}

5. A queue is a data storage divide like a stack. The difference is that in a stack the last
data item stored is the first one retrieved, while in a queue the First data item stored is the
first retrieved. Use two pointers, FRONT for retrieve and RARE for entry. The member
function push ( ) should include overflow checking and pop ( ) should include underflow
checking. Write a main ( ) program to implement a queue and test it.(10 marks)

# include<iostream.h>
# include<conio.h>
cnst int max = 20;
 class queue
{
private;
int q[max], FRON,RARE;
public;
queue( )
{ FRONT =RARE =-1;}
void push(int d)
{
if(RARE<max-1)
q[+ +RARE] =d;
else cout<< “Overflow”;
}
void pop( )
{
if(FRONT<RARE)
cout<< “\n”<<q[+ +FRONT];
else cout<< “Underflow”;
}
};

void main( )
{
queue q;
clrscr( );
q.push(11);
q.push(33);
q.pop( );
q.pop( );
q.pop( );
getch( );

6. To the Distance class, add on overloaded operator that subtracts two distance like dist
3 = dist 1 – dist 2. Assume that operator will never be used to subtract a longer number
from a smaller one. (20 marks)
# include<iostream.h>
# include<conio.h>
class Distance
{
private;
int feet;
float inches;
public:
Distance( )
{ feet =0; inches = 0.0;}
Distance(int ft ,float in)
 {feet = ft;inches = in;}
void getdist( )
{
cout<< “\nEnter feet and inches”;
cin>>feet>>inches;
}
void showdist( )
{
cout<<feet<< “\ “-”<<inches<< “\””;
}
Distance operator-(Distance d1)
{
int f = feet-d1.feet;
float I =inches-d1.inches;
if(i<0)
return Distance(f,i);
}
};
void main( )
{
Distance dist1(11,6.25);
Distance dist2.dist3;
dist2.getdist( );
dist3 =dist1 –dist2;
cout<< “\ndist1 =”;dist1.showdist( );
cout<< “\ndist2 =”;dist2.showdist( );
cout<< “\ndist3 =”;dist3.showdist( );
getch ( );
}

7. To the Distance class, add an overloaded operator that add two distance like dist 1 +=
dist 2. (20 marks)

#include<iostream.h>
#include<conio.h>
class Distance
{
private;
int feet;
float inches;
public;
Distance( )
{ feet = 0;inches = 0.0;}
Distance(int ft,float in)
{ feet = ft;inches =in;}
void getdist( )
 {
cout<< “\nEnter feet and inches”;
cin>>feet>>inches;
}
void showdist( )
{
cout<<feet<< “\ “-”<<inches<< “\””;
}
void operator += (Distance d1)
{
feet +=d1.feet;
inches += d1.inches;
if ( inches>= 12.0)
{
inches - = 12.0;
feet ++;
}
};
void main( )
{
Distance dist1( 11,6.25);
Distance dist2;
cout<< “\n dist1=”;
dist1.showdist( );
dist2.getdist( );
dist1+ = dist2;
cout <<”\n dist1=”;
dist1.showdist( );
cout <<”\n dist2=”;
dist2.showdist( );
getch( );
}

8. To the Distance class, add an overloaded operator that dis1 < dist2.
(20 marks)

#include<iostream.h>
#include<conio.h>
enum Boolean {false , true};
class Distance
{
private:
int feet;
 float inches;
public;
Distance( )
{ feet = 0;inches = 0.0;}
Distance(int ft,float in)
{ feet = ft;inches = in;}
{
cout<< “\nEnter feet and inches”;
cin>>feet>>inches;
}
void showdist( )
{
cout<<feet<< “\ “-”<<inches<< “\””;
}
Boolean operator<(Distance d1)
{
float f1 = feet + inches/12;
float 12 = d2.feet + inches/12;
return (f1<f2)? true:false;
}
};
void main( )
{
Distance dist;
dist1. getdist( )
Distance dist2(6,2.5);
cout<< “\ndist1 =”;dist1.showdist( );
cout<< “\ndist2 =”;dist2.showdist( );
if(dist1<dist2)
cout<< “Dist1 is less than Dist2”;
else cout<< “Dist2 is greater than Dist1”;
getch ( );
}

9. Write a program the conversion of distance to meter, meter to Distance.

(20 marks)

#include<iostream.h>
const float MTF = 3.280833;
class Distance
 { private : int ft;
float in;
public : Didtance ( )
{ft.in = 0;}
Distance ( int f, float i)
{ ft = f;
in = I;}
void show ( )
{ cout<<ft<< “\’”<<in<< “\” ”; }
Distance ( float m)
{ float f = m * MTF;
ft = f;
in = ( f- ft)*12; }
Operator Float ( )
{ Float f = ft + in/12;
Float m = f / MTF ;
return m;}
};
void main ( )
{ Distance d ( 5,5.5);
float m;
cout<< “ meter =”<<m;
cout<< “ Enter meter”;
cin>> m;
d = m;
d.show ( );
}

10. Create the time class with integer members (hours, minutes, seconds) and include
overloaded increment (++) and decrement (--) operators that operate in both prefix and
postfix notation and return value. Write a main program to test the above time calss.
(20 marks)

#include<iostream.h>
#include<conio.h>
class time
{
private:
int hr.min.sec;
public:
time( )
{ hr = 0;min =0;sec = 0;}
time(int h,int m, int s)
{ hr =h;min = m;sec =s;}
void gettime ( )
{
 cout<< “\nEnter hour,minute and second”;
cin>>hr>>min>>sec;
}
void puttime ( );
time operator + +( )
{
+ + sec;
return time (hr,min,sec);
}
time operator+ +( )
{
- - sec;
return time(hr,min,sec);
{
sec - -
return time(hr,min,sec);
}
};
void time::puttime ( )
{
if(see<= -1)
{sec+ = 60;
min--;
if(min< = -1) {
min+=60;
hr--;
}
}
if(sec>=60)
{sec-=60;
min+ +;
if(min>=60)
{min-=60;
hr++;}
}
void main( )
{
time t1(5,59,59);
time t2(10,10,10);
time t3,t4;
13=t1++ ;
14 = ++t1;
cout<< “time 3 =”:t3.puttime( );
cout<< “time 4 =”:t4.puttime( );
13=t1 --;
14 =--t1;
 cout<< “time 3 =”:t3.puttime( );
cout<< “time 4 =”:t4.puttime( );
getch( );
}

11. Create a class Int that contain an integer variable. Overload all five integer arithmetic
operators (+, -, *, /, %). So that they operate an object of type Int. If the result of any such
operation exceeds the normal range of int from -32768 to 32767, the operator prints a
warning and terminate the program. Write a program to test this class.
(20 marks)

# include <iostream.h>
# include <conio.h>
# include <stdio.h>
class int
{
private :
int a;
public :
int ( )
{a = 0; }
int (int x)
{ a = x; }
void getdata ( )
{ cout << “\n Enter an integer number”;
cin >> a;
}
void putdata ( )
{
cout << “The Result =” << a;
}
int check (long y)
{ if ( y >= -32768 && y < 32768 )
return 1;
else return 0;
}
int operator + (int i)
{
long y = long (a) + long (i.a);
if check(y) return int(y);
else {
cout << “Over Range”;
exit (0);
}
}
int operator – (int i)
{
long y = long (a) – long (i.a);
if check(y) return int(y);
else {
cout << “Over Range”;
exit (0);
}
}
int operator * (int i)
{
long y = long (a) *long (i.a);
if check(y) return int(y);
else {
cout << “Over Range”;
exit (0);
}
}

int operator / (int i)

{
long y = long (a) /long (i.a);
if check(y) return int(y);
else {
cout << “Over Range”;
exit (0);
}
}

int operator % (int i)

{
long y = long (a) % long (i.a);
if check(y) return int(y);
else {
cout << “Over Range”;
exit (0);
}
}
};
void main ( )
{
Int i1, i2, i3;
Int c;
i1.getdata ( );
i2. getdata ( );
cout << “Enter your choice”;
 cin >> c;
switch (c)
{
case 1: i3 = i1 + i2; break;
case 2: i3 = i1 - i2; break;
case 3: i3 = i1 * i2; break;

case 4: i3 = i1 / i2; break;

case 5: i3 = i1 % i2; break;
}
i3.putdata ( );
getch ( );
}
12. Create the polar class to incorporate overloaded operators for multiplication and
division that require a constant (type double) as the second operand, not a polar. Write a
program to exercise all these operations with a variety of values.
( 20 marks)

# include <iostream.h>
class polar
{ private : double radius, angle;
public : polar ( )
{ radius = angle = 0.0; }
Polar (double r, double a)
{ radius = r;
angle = a;
}
void get ( )
{ cout << “Enter radius & angle”;
cin >> radius >> angle;
}
void show ( )
{ cout << radius << “\t” << angle; }
Polar operator * (double x)
{ return polar (radius * x, angle); }
Polar operator / (double x)
{ return polar (radius/x, angle); }
};
void main ( )
{ Polar P;
P.get ( );
double x;
cout << “Enter Multiplication number”;
cin >> x;
P=P*x;
cout << “Multiplication =” ;
 P.show ( );
cout << “Enter division number”;
cin >> x;
P = P/x ;
cout << “Division”;
P.show ( );
}

13. Write a program to implement their hierarchy diagram. ( 20 marks)

Class Employee
name;
number;

Class Scientist
Class manager Class laborer
title; publications
dues;

One- to – many class hierarchy

# include <iostream.h>
# include <string.h>
# define max 20
class employee
{ protected : char name [max];
long num;
public : employee ( )
{ name [0] = ‘\0’;
num = 0.0;
}
employee (char s[ ], long n)
{ stcpy (name, s);
num = n;
}
void get ( )
{ cout << “enter name”;
cin.get (name, max)
cout << “Enter number”;
 cin >> num;
}
void show ( )
{ cout << “\n Name =” << name;
cout << “\n Number =” << num;
}
};

class Manager : public employee

{ private : char title [max];
double dues;
public : manager ( ) : employee ( ) { title [0] = “\0”;
dues = 0.0;
}

14. Write a program to implement their hierarchy diagram. (20 marks)

Class employee Class student

name (string) School (string)
number(int) degree(string)

class laborer class scientists class manager

pubs(int) title (string)
dues(double)

many – to many class hierarchy

# include <iostream.h>
# include <string.h>
# define max 20
class employee
{ protected : char name [max];
long num;
public : employee ( )
{ name [0] = ‘\0’;
num = 0.0;
}
employee ( char n [ ], long n )
{ strcpy (name, n);
num = n;
}
void get ( )
{ cout << “Enter name” ;
cin.get (name, max);
cout << “Enter number”;
cin >> num;
}
void show ( )
{ cout << “\n Name =” << name;
cout << “\n Number =” << num;
}
};
class student
{ protected : char sch [max];
char deg [max];
public : student ( )
{ sch [0] = ‘\0’;
deg [0] = ‘\0’;
}
student ( char s[ ], char d[ ] );
{ strcpy (sch, s);
strcpy (deg, d);
}
void get ( )
{ cout << “enter school”;
cin.get (sch, max);
cout << “Enter degree”;
cin.get (deg, max);
}
void show ( )
{ cout << “\n School =” << sch;
cout << “\n Degree =” << deg;
}
};
class laborer : public employee
{ };
class scientist : public employee, public student
{ private : int pubs;
public : scientist ( ) : employee ( ) , student ( )
 { pubs = 0; }
scientist ( char n[ ], long n, char s[ ], char d[ ],
int p ) : employee (n, n), student (s, d)
{ pubs = p; }
void get ( )
{ employee : : get ( );
student : : get ( );
cout << “Enter publications”;
cin >> pubs;
}
void show ( )
{ employee : : show ( );
student : : show ( );
cout << “Publications =” << pubs;
}
};
class managewr : public employee, public student
{ private : char tit [max];
double dues;
public : manager ( ) : employee ( ), student ( )
{ tit [0] = ‘\0’;
dues = 0.0;
}
manager ( char n[ ], long n, char s[ ], char d[ ],
char t[ ], double d): employee (n,n),
student (s, d)
{ strcpy (tit, t);
dues = d;
}
void get ( )
{ employee : : get ( );
student : : get ( );
cout << “Enter title”;
cin.get
cout << “Enter dues;
cin >> dues;
}
void show ( )
{ employee : : show ( );
student : : show ( );
cout << “\n Title =” << tit;
cout << “\n Dues =” << dues;
}
};
void main ( )
{ laborer l;
 scientist s;
manager M;
l.get ( );
l.show ( );
s.get ( );
S.show ( );
M.get ( );
M.show ( );
}

15. Create a student class that includes the member data number (int) and marks of four
papers (ints). The member function are get-student ( ) to get student data and display ( )
to display the object details. The grade class also include the member data roll number
(int) and grade value (char) and the member function where a conversion function from
student class to grade class and a display function. The conversion condition are as
follow:
(i) Average of paper marks >= 75, grade = ‘A’
(ii) Average of paper marks < 75 and >= 65, grade ‘B’
(iii) Average of paper marks < 65 and >= 40, grade ‘C’
Write a program to create two different objects and test the conversion.

(20 marks)
# include <iostream.h>
class student
{ private : int rno, m1 , m2 , m3 , m4 ;
public : void get ( )
{ cout << “Enter rno and marks”;
cin >> rno >> m1 >> m2 >> m3 >> m4 ;
}
void show ( )
{ cout << rno << “\t” << m1 << “\t” << m2 <<“\t”
<< m3 << “\t” << m4 ;
}
int getrno ( )
{ return rno; }
int get m1 ( )
{ return m1 ; }
int get m2 ( )
{ return m2 ; }
int get m3 ( )
{ return m3 ; }
int get m4 ( )
{ return m4 ; }
};
class grade
 { private : int r;
char gvalue;
public : void get ( )
{ cout << “Enter rno & gvalue”;
cin >> r >> gvalue;
}
void show ( )
{ cout << r << “\t” << gvalue; }
grade ( student st )
{ int P1 , P2 , P3 , P4 ;
r = st. getrno ( );
P1 = st.getm1 ( );
P2 = st.getm2 ( );
P3 = st.getm3 ( );
P4 = st.getm4 ( );
float avg = ( P1 + P2 + P3 + P4 ) /4 ;
if ( avg >= 75 ) gvalue = ‘A’;
else if ( avg >= 65 ) gvalue = ‘B’;
else if ( avg >= 40 ) gvalue = ‘C’;
}
};
void main ( )
{ student s;
grade g;
s.get ( );
g = s;
g.show ( );
}

16. Create the Type class which store dimension (string) grade (string) and Distance class
which store ft (int), in (float). From the type and Distance class derived class called
lumber that contain qty (int) price4 float. Implement main program and test it.
(20 marks)

# include <iostream.h>
# include < string.h>
const int max = 40;
class Type
{ private : char dimensions [max];
char grade [max];
public : Type ( )
{ strcpy ( dimensions, “N/A” );
strcpy ( grade, “N/A” );
}
 Type ( char di[ ] , char gr[ ] )
{ strcpy ( dimension, di);
strcpy (grade, gr);
}
void get type ( )
{ cout << “\n Enter dimensions (2 * 4 etc):”;
cin >> dimensions;
cout << “\n Enter grade (rough-cut, construction-
grade, surface-four-sides,)” ;
cin >> grade;
}
void show type ( )
{ cout << “\n Dimensions =” << dimensions;
cout << “\n Grade=” << grade;
}
};
class Distance
{ private : int feet;
float inches;
public : Distance ( )
{ feet = 0; inches = 0.0; }
Distance ( int ft, float in )
{ feet = ft; inches = in; }
void getdist ( )
{ cout << “\n Enter feet:”; cin >> feet;
cout << “\n Enter inches:”; cin >> inches;
}

void showdist ( )
{ cout << feet << “\’-” << inches << ‘\”’; }
};
class lumber : public Type, public Distance
{ private : int quantity;
float price;
public : lumber ( ), Type ( ), Distance ( )
{ quantity = 0; price = 0.0; }
lumber ( chart di[ ], char gr[ ], int ft, float in,
int qu, float prc);
Type (di, gr), Distance (ft, in)
{ quantity = qu ; price = prc; }
void getlumber ( )
{ Type : : gettype ( );
Distance : : getdist ( );
cout << “\n Enter quantity:”; cin >> quantity;
cout << “\n Enter price:”; cin >> price;
 }
void showlumber ( )
{ Type : : showtype ( );
Distance : : showdist ( ) ;
cout << “\n Price for:” << quantity << “is $”
<< quantity * price;
}
};
void main ( )
{ lumber siding;
cout << “\n Siding Data : \n”;
Siding.getlumber ( );
lumber studs ( “2*4”, “constru”, 8, 0.0, 200, 4.45 );
cout << “\n siding”; siding.showlumber ( );
cout << “\n studs”; studs.showlumber ( );
}

17. Create a class publication that stores the title ( a string ) and price (type float). From
this class derive two classes: book which adds a page count (type int) and tape, which
adds a playing time in minutes (type float). Each of these three classes should have a
getdata ( ) function to get is data from the user and a putdata ( ) function to display its
data. Write a main ( ) program to implement this class. (20 marks)

# include <iostream.h>
# include <string.h>
# define max 20
class publication
{ protected : char title [max];
float pri;
public : void get ( )
{ cout << “Enter title”;
cin.get (title, max );
cout << “Enter price”;
cin >> pri;
}
void show ( )
{ cout << “\n Title =” << title;
cout <, “\n Price =” << pri;
}
};
class book : public publication
{ private : int pcount;
public : void get ( );
 { publication : : get ( );
cout << “Enter page count”;
cin >> pcount;
}
void show ( )
{ publication : : show ( );
cout << “\n Page Count =” << pcount;
}
};
class type : public publication
{ private : float min;
public : void get ( )
{ publication : : get ( )
cout << “Enter minute” ;
cin >> min;
}
void show ( )
{ publication : : show ( );
cout << “\n Minute =” << min;
}
};
void main ( )
{ book b;
tape t;
b.get ( );
b.show ( );
t.get ( );
t.show ( );
}

18. A company rents both cars and trucks. A class transport stores the capacity (int), the
status (rented as available) and the cost of rental ( a float). From this class (derived car
class that include number of passengers and) three count ( an int); and truck which adds a
load limit measured in matric tones (an int). Each of these three classes should have a
getdata ( ) function to obtain data from user and a showdata ( ) function to display data on
the screen. Implement these three classes and write a main ( ) program to test a car and
truck classes. (20 marks)

# include <iostream.h>
# define max 5
class transport
{ protected : int cop;
char status [max];
float cost;
public : void get ( )
{ cout << “Enter capacity”;
 cin >> cap;
cout << “Enter status”;
cin.get (status, max);
cout << “Enter cost”;
cin >> cost;
}
void show ( )
{ cout << “\n Capacity =” << cap;
cout << “\n Status =” << status;
cout << “\n Cost =” << cost;
}
};
class car : public transport
{ private : int no: per; int count;
public : void get ( )
{ transport : : get ( )
cout << “Enter no: of person”;
cin >> no: per;
cout << “Enter count”;
cin >> count;
}
void show ( )
{ transport : : show ( );
cout << “\n No: of person =” << no: per;
cout << “\n count =” << count;
}
};
class truck : public transport
{ private : int ton;
public : void get ( )
{ transport : : get ( );
cout << “Enter ton”;
cin >> ton;
}
void show ( )
{ transport : : show ( );
cout << “Enter ton”
cin >> ton;
}
void show ( )
{ transport : : show ( );
cout << “\n Ton =” << ton;
}
};
void main ( )
{ car c;
 truck t;
c.get ( );
c.show ( );
t.get ( );
t.show ( );
}

19. Create a class publication that stores the title (string) and price (float) and sale class
that holds an array of three float. The book and tape that they are derived from
publication and sale. Add a disk class that like book and tape, is derived from publication.
The disk class should incorporate the same member functions as the other classes. The
data item unique to this class is the disk size: either 3-1/2 inches or 5-1/4 inches. You can
use an enum Boolean type to store this item, but the complete size should be displayed.
The user could select the appropriate size by typing 3 or 5. (20 marks)

# include <iostream.h>
# define max 20
class publication
{ protected : char title [max];
float pri;
public : void get ( )
{ cout << “Enter title”;
cin.get (title, max);
cout << “enter price”;
cin >> pri;
}
void show ( )
{ cout << “\n Title =” << title;
cout << “\nPrice =” << pri;
}
};
class sale
{ protected : float m[3];
public : void get ( );
void show ( );
};
void sale : : get ( )
{ for (int i = 0; i < 3; i++ )
{ cout << “Enter sale amount for one month”;
cin >> m[i];
}
}
void sale : : show ( )
{ for (int i = 0; i < 3; i++ )
{ cout << m[i]; }
}
class book : public publication, public sale
{ private : int pcount;
public : void get ( )
{ publication : : get ( );
sale : : get ( );
cout << “Enter page count”;
cin >> pcount;
}
void show ( )
{ publication : : show ( );
sale : : show ( );
cout << “\n Page count =” << pcount;
}
};
class tape : public publication, public sale
{ private : int min;
public : void get ( )
{ publication : : get ( );
sale : : get ( );
cout << “Enter Minute”;
cin >> min;
}
void show ( )
{ publication : : show ( );
sale : : show ( );
cout << “\n Minute =” << min;
}
};
enom size { three, five };
class disk : public publication
{ private : size s;
public : void get ( )
{ int n;
cout << “Enter 3 or 5”;
cin >> n;
s = ( n = = 3 ) ? three : five;
publication : : get ( );
}
void show ( )
{ cout << ( s = = three ) ? “disk size = 3 ½”;
“disk size = 5 ¼”;
publication : : show ( );
}
};
void main ( )
{ book b;
 tape t;
disk d;
b.get ( ); b.show ( );
t.get ( ); t.show ( );
d.get ( ); d.show ( );
}

20. Start with the publication, book and tape classes. Suppose you want to add the date of
publication for both books and tapes. From the publication class, derived a new class so
called publication 2 that includes this member data. Then change book and tape so they
are derived from publication 2 instead of publication. Make all the necessary changes in
member functions to the user can input and output data along with the other data. For the
data class, use three ints of months, day and year. The member functions are getdata ( )
and showdata ( ). (20 marks)

# include <iostream.h>
# define max 20
class publication
{ protected : char title [max];
float pri;
public : void get ( )
{ cout << “enter title”;
cin.get (title, max);
cout << “Enter price”;
cin >> pri;
}
void show ( )
{ cout << “\n Title =” << title;
cout << “\n Price +” << pri;
}
};
class publication 2 : public publication
{ protected : int mon, day, year;
public : void get ( )
{ publication : : get ( );
cout << “Enter month, day and year”;
cin >> mon >> day >> year;
}
void show ( )
{ employee : : show ( );
student : : show ( );
cout << “\n Title =” << tit << “\t” << “Dues =”
<< dues;
}
};
class book : public publication2
 { private : int pcount;
public : void get ( )
{ publication 2: : get ( );
cout << “Enter page count”;
cin >> pcount;
}
void show ( )
{ publication 2: : show ( );
cout << “\n Page count =” << pcount;
}
};
class tape : public publication2
{ private : int min;
public : void get ( )
{ publication 2: : get ( );

cout << “Enter Minute”;

cin >> min;
}
void show ( )
{ publication2 : : show ( );
cout << “\n Minute =” << min;
}
};
Void main()
{ book B;tape T;
B.get();
T.get();
B.show ( );
T.show ( );

21.Create a linklist program using pointer. Add a destructor to the linklist program. It
should delete all the links when a linklist object is destroyed. It can to this by following
along the chain, deleting each link as it goes. You can test the destructor by having it
display a message each time it deletes a link; it should delete the same number of links
that were added to the list. (20 marks)
# include <iostream.h>
struct link
{ int data;
link * next;
};
 class linklist
{ private : link * F;
public : linklist ( )
{ F = NULL; }
void add ( int d );
void display ( );
~ linklist ( );
};
void linklist : : add ( int d )
{ link * L;
L = new link;
L → data = d ;
L → next = F;
F = L;
}
void linklist : : display ( )
{ link * c;
c = F;
while ( c! = NULL )
{ cout << c → data;
c = c → next;
}
}
linklist : : ~ linklist ( )
{ link * d ;
d = F;
while ( d ! = NULL )
{ F = d → next;
delete d;
d = F;
}
}
void main ( )
{ linklist li;
Li.add (5);
Li.add (6);
Li.display ( );
}

22. Revise the additem ( ) member functions from the linklist program so that it adds the
item at the end of the list, rather than the beginning. This will cause the first item inserted
to be the first item displayed. To add the item you will need to follow the chain of
pointers to the end of the list, then change the last link to point to the new link.
(20 marks)

# include <iostream.h>
 struct link
{ int data;
link * next;
};
class linklist
{ private : link * F
public : linklist ( )
{ F = NULL; }
void add ( int d );
void display ( );
void operator = (linklist L1 );
~ linklist ( );
};
void linklist : : add ( int d )
{ link * L;
L = new list;
L → data = d;
L → next = NULL;
if ( F == NULL )
{ F = L; }
else { link * P ;
P = F;
while ( P → next != NULL )
{ P = P → next; }
P → next = L;
}
void linklist : : display ( )
{ link * c ;
c = F;
while ( c != NUL )
{ cout << c → data;
c = c → next;
}
}
void linklist : : operator = ( linklist L1 )
{ link * t, * temp, * P;
L = F;
while ( t != NULL )
{ temp = new link;
temp → data = t data;
temp → next = NULL;
if ( F = = NULL )
{ F = temp;
P = temp;
t = t → next;
}
 else { P → next = temp;
P = temp;
t = t → next;
}
}
}
linklist : : ~ linklist ( )
{ link * d ;
D = F;
while ( d ! = NULL )
{ F = d → next;
delete d ;
d = F;
}
}
void main ( )
{ linklist L1 , L2 ;
L 1.add (5);
L1 .add (6);
L 1. add (7);
L 1.display ( );
L 2 = L2 ;
L 2. display ( );
}

23. Create an employee class that certain name, number and student class that holds
school, degree, the manager class that are derived from employee and student’s class.
That certain title (string), class (double). From the manager class derive a class called
executive. The additional data in executive class will be the size of the employee’s yearly
bonus and the number of shares of company stock held in his or her stock option plan.
Add the appropriate member functions so these data items can be input and display along
with the other manager data. (20 marks)

# define max 20
# include <iostream.h>
# include <string.h>
class employee
{ protected : char name [max];
long num;
public : employee ( ) { }
employee (char n[ ], long n)
{ strcpy ( name , n )
num = n;
}
void get ( )
 { cout << “Enter name”;
cin.get ( name, max );
cout << “Enter number”;
cin >> num;
}
void show ( )
{ cout << “\n Name =” << name;
cout << “\n Number =” << num;
}
};
class student
{ protected : char sch [max];
char deg [max];
public : void get ( )
{ cout << “Enter school”;
cin.get ( sch, max);
cout << “Enter degree”;
cin.get (deg, max);
}
void show ( )
{ cout << “\n school =” << sch;
cout << “\n degree =”;
}
};
class manager : public employee, public student
{ protected : chartit [max];
double dues;
public : void get ( )
{ employee : : get ( );
student : : get ( );
cout << “Enter title”;
cin.get (tit, max);
cout << “Enter dues”;
cin >> dues;
}
void show ( )
{ employee : : show ( );
student : : show ( );
cout << “\n Title =” << tit << “\t” << “Dues =”
<< dues;
}
};
class executive : public manager
{ private : int bonus, shares;
public : void get ( )
{ manager : : get ( );
 cout << “Enter bonus and shares”;
cin >> bonus >> shares;
void show ( )
{ manager : : show ( );
cout << “\n Bonus =” << bonus << “\t” <<
“ shares =” << shares;
}
};
void main ( )
{ executive e;
e.get ( ); e.show ( );
}

Software Engineering

24.Define the following. (20 Marks)

i. Software and Software Engineering
ii. Difference between software engineering and computer scinence and
difference between software engineering and system engineering
iii. Software process and software process model
iv. Software engineering methods and CASE

Solution
i. Software – computer programs and associated documentation. Software product
may be developed for a particular customer or may be developed for a general
market.
Software Engineering – software engineering is an engineering discipline which is
concerned with all aspects of software production.

ii. Difference between software engineering and computer scinence- Computer

scince I concernd with theory and fundamental; software engineering is concernd
with thee practicalities of developing and delivering useful software.
Difference between software engineering and system engineering-System
engineering is concerned with all aspects of computer-ad system development,
including hardware, software and process engineering. Software engineering is
part of this process.

iii. Software process- a set of activities whose goal is the development or evolution of
software.
software process model- a simplified representation of a software process,
presented from a specific perspective.
 iv. Software engineering methods-structured approaches to software development
which include system models, notation, rules, design advice and process guidance
CASE-computer aided software engineering.software systems which are intended
to provide automated support for software process activities. CASE systems are
often used for method support.

25. Explain system design with diagram. (10 marks)

Sol
i. Parition requirements The requirements and organize them into related groups are
analysed. There are usually several possible portioning options, and a number of
alternatives at this stage of the process.
ii. Identify sub-systems That are identified sub-system that can individually or
collectively meet the requirements. Groups of requirements are usually related to
sub-systems , so this activity and requirements portioning may be amalgamated.
However, sub-system identification may also be influenced by other
organizational or environmental factors
iii. Assign requirements to sub-system,
That are the requirements to sub-systems. This should be straight-forward if
the requirements partitioning is used to drive the sub-system identification .There
is never a clean match between tequirements partitions and identified sub-
systems.
iv. Specify sub-system functionality
That specifies the specific functions provided by each sub-system.This
may be seen as part of the system design phase or if the sub-system , pat of the
requirements specification activity for that system.
v. Define sub-system interfaces
That defines the interfaces that are provided and required by each sub-
system .Once these interfaces have been agreed upon, it becomes possible to
develop these sub-system in parallel.

Partition
Define sub-system
requirement
interfaces
s

Identify Specify sub-system

Sub-systems functionality

Assign requirements
To sub-system

Figure 2.4 The system design process

26.Explain about the following types of software process model.(10 Marks)
• Workflow model
• Dataflow or activity model
• Role/action model
• Waterfall approach
• Component-based software engineering

Sol
Workflow model
This shows the sequence of activities in the process along with their inputs,
outputs and dependencies. This represent human actions.

Dataflow model
This represents the process as a set of activites, each of which carries out some
data transformation. It shows how the input to the process, such as a specification, is
transformed to an output, such as a design.

Role/action model
This represents the roles of the people involved in the software process and the
activities for which they are responsible.

Waterfall approach
This takes the above activities and represents them as separate process phases
such as requirements specification, software design, implementation, testing and so
on.

Component-based software engineering

This technique assumes that parts of the system already exist. The system
development process focuses on integrating these parts rather than developing them
from scratch.
Digital Electronics

IT 2023

for

Second Semester
s

Sample Question
1. Show the state of the 5-bit register in figure, for the specified data input and clock
waveforms. Assume that the register is initially cleared (all 0s). (15 Marks)

FF0 FF1 FF2 FF3 FF4

Q0 Q1 Q2 Q3 Q4
Data
input D D D D D Data
Output

C C C C C

CLK

CLK

Data
input
R 0 1 0

2. Determine the state of the bi-directional shift register after each clock pulse for the
given RIGHT/ LEFT control input waveform in figure . Assume that Q0 =1, Q1 =1,
Q2 =0 and Q3 =1 and that the serial data input line is LOW. (20 Marks)

RIGHT /
(right) (left) (right) (left)
LEFT

CLK

3. Determine the amount of time delay between the serial input and each output in
figure. Show a timing diagram to illustrate. (10 Marks)

A
Data in SRG 8*
B
CLR
o
CLK
500KHz

Q0Q1Q2Q3Q4Q5Q6Q7

CLK
4. What is register and draw basic data movements of shift register. (20 Marks)
5. Draw the storing process of 4-bit register step-by-step with input of 1010. (20 Marks)
6. Show the state of the 4-bit registers (SRG-4) for the data input and clock waveform in
figure. The register initially contains all 1s. (10 Marks)

SRG-4
D

Q0 Q1 Q2 Q3

0 1 1 0
Data in

CLK

7. Explain basic memory operation with figures. (10 Marks)

8. Explain the memory write operation with appropriate figure. (10 Marks)
9. Explain the memory read operation with appropriate figure. (10 Marks)
10. Briefly discuss about RAMs. (10 Marks)
11. Explain RAM family and draw the block diagram of RAM family. (10 Marks)
12. Use 1M x 8 SRAM to create a 1Mx16 SRAM. (10 Marks)
13. Draw basic organization of an asynchronous 32k x 8 SRAM. (20 Marks)
14. Briefly discuss the following storages. (10 Marks)
(a) CD-ROM
(b) CD-R
(c) CR-RW
15. Explain about the following storages. (10 Marks)
(a) WROM
(b) DVD-ROM
16. Show a basic ROM that programmed for a 4-bit binary to Gray conversion with
required truth table. (20 Marks)
17. Use 512k x 4 RAM to implement a 1M x 4 memory. (10 Marks)
18. Use 65,536 x 4 ROM to form a 64k x 16 ROM. (10 Marks)
19. Explain about the steps in placing a valid address on the 8288 bus controller.
(20 Marks)
20. Explain the example of an 8088 memory- read operation. (20 Marks)
21. Explain the example of an 8088 memory - write operation. (20 Marks)
22. (a) Define the term DMA. (5 Marks)
(b) Compare a memory I/O data transfer handled by the CPU to a DMA transfer.
(15 Marks)
23. Describe the internal buses system in a typical system in a typical personal computer.
(10 Marks)
24. Describe the RS-232 C bus (25 pins). (10 Marks)
Digital Circuit and System

IT (2023)

For

Second Semester

Sample Answer & Question

1
1. Show the state of the 5-bit register in figure, for the specified data input and clock
waveforms. Assume that the register is initially cleared (all 0s). (10 Marks)

FF0 FF1 FF2 FF3 FF4

Q0 Q1 Q2 Q3 Q4
Data
input D D D D D Data
Output

C C C C C

CLK

CLK

Data
input
R 0 1 0

Solution

CLK
Data
Input 0
1 1 0

Q0 0
Data
1 bits
Q1 stored
after
Q2 0 five
1
Q3
1
Q4

2. Determine the state of the bi-directional shift register after each clock pulse for the given
RIGHT/ LEFT control input waveform in figure (b). Assume that Q0 =1, Q1 =1, Q2 =0
and Q3 =1 and that the serial data input line is LOW. (20 Marks)

2
 RIGHT /
(right) (left) (right) (left)
LEFT

CLK

Solution
Data In ‘0’
RIGHT/

( right ) ( left )
( right ) ( left )

CLK

Q0
1

Q1
1

Q2 0

Q3
1

3. Determine the amount of time delay between the serial input and each output in figure.
Show a timing diagram to illustrate. (10 Marks)

3
 A
Data in SRG 8*
B
CLR
o
CLK
500KHz

Q0Q1Q2Q3Q4Q5Q6Q7

CLK

Solution

f =500kHz

f =1/t

t =1/f
=1/500 103
= 1/5 105
=0.2 10-5
t =2 10-6s
t =2µs

For SRG 8*, the time delay can be increased or decreased in 2µs increments from a
minimum of 2µs to a maximum of 16µs. This is shown in the following figure.

CLK

Data in

Q0

Q1

Q2

Data
out Q3

Q4

Q5

Q6

Q7
2µs
4µs
6µs
8µs 10µs
4 12µs
14µs
16µs
4. What is registered and draw basic data movements of shift register. (20 Marks)

Register
A register is a digitae circuit with two basic functions: data storage and data
movement. The storage capability of a register makes it an important type of memory
device. A register, unlike a counter, has no specified sequence of states.
The basic data movements of shift register are shown in the following.

5
 Data Data
Data in Data out out in
(a) Serial in/ shift right/serial (b) Serial in/ shift left/serial out

Data in

Data in
Data
out
(c) Parallel in /serial out Data out
(d) Serial in /parallel out

Data in

Data
out

Data out
(e) Parallel in/Parallel put (f) Rotate right

(g) Rotate left

6
5. Draw the storing process of 4-bit register step-by-step with input of 1010. (20 Marks)

FF0 FF1 FF2 FF3 0

Data 1 0 1 Q3
D D D D
Input

C C C C Register
initially
clear
C

1 0 1 0
1st data Q3
bit=0 D D D D
After
C C C C CLK1

CLK 1

0 0
2nd data 0 0 Q3
bit=1 D D D D

C C C After
C CLK2

CLK2

1 0 0 Q3
3rd data 0
D D D D
bit=1
C C C C After
CLK3

CLK3
1 1 0
4th data 0 Q3
D D D D
bit=1
C C C C After
CLK4

CLK 4

The 4-bit number is completely stored in register after four clock pulse.

7
6. Show the state of the 4-bit registers (SRG-4) for the data input and clock waveform in
figure. The register initially contains all 1s. (10 Marks)

SRG-4
D

Q0 Q1 Q2 Q3

0 1 1 0
Data in

CLK

Solution
Data 0
in 1 0
1

CLK

Q0

Q1

Q2

Q3

The register contains 0110 after four clock pulses.

8
 Chapter (12)

7. Explain basic memory operation with figures. (10 Marks)

Basic memory operation

Since a memory stores binary data, data must be put into the memory and copied
from the memory when needed. The write operation puts data into a specified address in
the memory, and the re ad operation takes data out of a specified address in the memory.
The addressing operation selects s the specified memory address.
In figure, the data bus is bi-directional, which means that data can go in either direction
(into the memory or out of the memory). In this case of a byte organized memory, the
data bus has a least eight lines so that all eight bits in a selected address are transferred in
parallel. For a write or a read operation, an address is selected by placing a binary code
representing the desired address on a set of lines called the address bus. The address code
is decoded internally in the appropriate address is selected. The number of lines in the
address bus depends on the capacity of the memory.

Address Bus
Address
Data bus
decoder Memory array

Read Write
Fig: Block diagram of a memory

8. Explain the memory write operation with appropriate figure. (10 Marks)

The write operation: To store a byte of data in the memory, a code held in the address
register is placed on the address bus. Once the address code is on the bus, the address
decoder decodes the address and selects the specified location in the memory. The
memory then gets a write command and the data byte held in the data register is placed on
the data bus and stored in the selected memory address. When a new data byte is written
into a memory address, the current data byte stored at that address is overwritten and
destroyed.

9
 Address Register
Data register
Byte organized memory array
101 10001101
0
1
Address 2
decoder 3
1 4 2
5 10 0 0 1 1 01
Address Bus 6 Data Bus
7

3 Write
Fig: Illustration of the write operation

9. Explain the memory read operation with appropriate figure. (10 Marks)

The read operation: In figure: a code held in the address register is placed on the address
bus. Once the address code is on the bus, the address decoder decodes the address and
selects the specified location in the memory. The memory then gets a read command, and
a “copy” of the data bytes that is stored in the selected memory address is placed on the
data bus and loaded into the data register. When a data byte is read from a memory
address, it also remains stored at that address and is not destroyed. This is called
nondestructive read.

Address Register
Data register
Byte organized memory array
011 11000001
0
1
Address 2
decoder 3 11 0 0 0 0 01
1 4 3
5
Address Bus 6 Data Bus
7

2 Read
Fig: Illustration of the Read operation

10. Briefly discuss about RAMs. (10 Marks)

RAMs are read/write memories in which data can be written into or read from any
selected address in any sequence. When a data unit is written into a given address in the
RAM, the data unit previously stored at that address is replaced by the new data unit.
When a data unit is read from a given address in the RAM, the data unit remains stored
and is not destroyed by the read operation. This nondestructive read operation can be
viewed as copying the content of an address while leaving the content intact. A RAM is
typically used for short-term data storage because it cannot retain stored data when power
is turned off.

10
11. Explain RAM family and draw the block diagram of RAM family. (10 Marks)

The RAM Family

The two categories of RAM are the static RAM (SRAM) and dynamic RAM
(DRAM). Static RAM use flip-flops as storage elements and can therefore store data
indefinitely as long as dc power is applied. Dynamic RAM use capacitors as storage
elements and cannot retain data very lone without the capacitors being recharged by a
process called refreshing. Both SRAMs and DRAMs will lose data when dc power is
removed and, therefore, are classified as volatile memories.

Random Access
Memory(RAM)

Static RAM Dynamic RAM

(SRAM) (DRAM)

Asynchronous Synchronous Fast page Extended Burst Synchron

SRAM Burst SRAM mode Data out EDO ous
(ASRAM) (SB SRAM) DRAM DRAM DRAM DRAM
(FPM (EDO (BEDO (SDRA
DRAM) DRAM) DRAM ) M)

Fig: The RAM Family

11
12. Use 1M x 8 SRAM to create a 1Mx16 SRAM. (10 Marks)

Address A0
bus
A1

I/O8
0 SRAM 2
0 SRAM 1 A 0
A 0 I/O0 19 1048 575
19
1048 575
I/O15
E0
E1
Data I/O
G Data I/O I/O7
R/W

7
Data
8
out

15

Fig: 1m×16 SRAM by using 1m×8 SRAM

13. Draw basic organization of an asynchronous 32k x 8 SRAM. (20 Marks)

Basic organization of an asynchronous 32k ×8 SRAM

Memory Array
256 rows 256 rows ×128
columns
×8 bits
8
bits

128 columns

Fig(a) Memory Array Configuration

12
 o
Address
o
lines
o Row Memory Array
o decoder 256 rows ×128 columns
o
×8 bits
o
o
Eight
input o
Output
buffers
I/O1 data
Input Column I/O
data
control Column decoder
I/O8
o o o o o o o
Address lines
CS o
o
WE o
OE o Eight
output
buffers

(b)Memory block diagram

*Basic organization of an asynchronous 32k ×8 SRAM.

14. Briefly discuss the following storages. (10 Marks)

(a) CD-ROM
(b) CD-R
(c) CR-RW

(a) CD ROM: The basic compact Disk Read Only Memory is a 120 mm diameter disk
with a sandwich of three coating. The CD-ROM disk is formatted in a single spiral track
with sequential 2 k byte sector and has a capacity of 680 m bytes. Data is pre recorded at
the factory area surrounding the pits called lands. The pits are stamped into the plastic
layer and cannot be erased.

(b) CD-R: The CD-Recordable allows multiple write sessions to different areas of the
disk. The CD-R disk has a spiral track like the CD-ROM, but instead of mechanically
pressing indentations on the disk to represent data, the CD-R uses a laser to burn
microscopic spots into an organic dye surface. When heated beyond a critical temperature
with a laser during read, the burned spots change color and reflected less light than the
non-burned areas. Therefore, 1s and 0s are represented on a CD-R by burned and non-
burned areas. The data cannot be erased once it is written.

13
 (c) CD-RW: The CD-Rewritable disk can be used to read and write data. When it is
heated to a certain temperature, it becomes crystalline when it cools, but if it is heated to a
certain higher temperature, it melts and becomes amorphous when it cools. To write data,
the focused laser beam heats the material to the melting temperature resulting in an
amorphous state. The data can be erased or overwritten by heating the amorphous areas to
a temperature above the crystallization temperature.

15. Explain about the following storages. (10 Marks)

(a) WROM
(b) DVD-ROM

(a) WORM: Write Once/Read Many (WORM) is a type of optical storage that can be
written onto one time after which the data cannot be erased but can be read many times.
1s and 0s are represented by the burned and non-burned areas.

(b) DVD-ROM : DVD was an abbreviation for Digital Video Disk but eventually came
to represent Digital Versatile Disk. DVD-ROM data are pre-stored on the disk. However,
the pit size is smaller than for the CD-ROM, allowing more data to be store on a track.
The major difference between CD-ROM and DVD-ROM is that the CD is single sided,
while the DVD has data on both sides. Also, in addition to double sided DVD disks, there
are also multiple layer disks that use semi transparent data layer placed over the main data
layers.

16. Show a basic ROM that programmed for a 4-bit binary to Gray conversion with required
truth table. (20 Marks)

Solution

Binary to Gray code conversion Truth Table

BINARY GRAY
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

14
 1 0
Address
decoder
0

5
Binary B0
6
code
applied B1
to 7
address
B2
input 8
lines
B3
9

10

11

12

13

14

15

G3 G2 G1 G0

Gray code output

15
17. Use 512k x 4 RAM to implement a 1M x 4 memory. (10 Marks)

A0
RAM 1

20-bit A
address 0
bus 524, 287
A18
A19 E0
& EN
E1
DI/O0 4-bit
DI/O1 data
DI/O2
DI/O3 bus
RAM 2

A
524, 287
1, 048,575

E0
& EN
Control E1
bus

18. Use 65,536 x 4 ROM to form a 64k x 16 ROM. (10 Marks)

A0 Address bus
16 bits
A15

16 bits ROM 1 16 bits ROM 2 16 bits ROM 3 16 bits ROM 4

64k x 4 64k x 4 64k x 4 64k x 4

4 bits 4 bits 4 bits 4 bits

& EN & EN & EN & EN

Control
bus
16
(enable) bits

Data
bus

16
 Chapter (13)

19. Explain about the steps in placing a valid address on the 8288 bus controller. (20 Marks)

The 8288 bus controller is used to relieve the 8088 microprocessor of most bus control
functions in order to increase the processing efficiency. One function of the bus controller
in the CPU is to provide the signals to multiplex the AD0-AD7 bus lines coming from the
microprocessor. The bus controller generates these control signals based on the codes on
the status lines ( s0 , s1 , s2 ) from the microprocessor.
When the microprocessor needs to communicate with memory or I/O, it sends a code
on the status lines to the bus controller. The bus controller then generates an ALE signal,
which latches the address placed on AD0-AD7 and AD8-AD19 by the microprocessor into
system address lathes. There are twenty latches (AD0-AD19), whose tristate outputs form
the system address bus. The steps in this operation are shown in figure. During a memory
read/write cycle, a valid address is available on the address bus; therefore, the lower eight
bits (AD0-AD7) of the microprocessor’s combined bus are freed up to send or receive data.

Bus controller ALE 3 Bus controller issues

(8288) ALE pulse to enable
latches

2 The 8088 signals bus

controller to latch 4 20 bit address is stored
address code in the latches
S2 S1 S0 EN
A19
A18
A17 A19
. . .
. . Address .
. . 5 20 bit address
. . latches is held on the
A8 . address bus
AD7 A0
. .
. .
. .
.
AD0

Microprocessor 1 20 bit address code is

placed on the address
(8088) lines

Figure- Steps in placing a valid address on the bus

Table- The 8088 read/write status codes

STATUS CODE ACTIVE BUS CONTROLLER

OPERATION
S2 S1 S0 OUTPUT COMMAND
0 0 1 Read I/O port IORC
0 1 0 Write I/O port IOWC
1 0 1 Read Memory MRDC
1 1 0 Write Memory MWTC

17
20. Explain the example of an 8088 memory- read operation. (20 Marks)

When the bus controller receives the status code of read operation, it sends a read
command ( IORC or MRDC ) to the appropriate device, and it also sends two signals to
the tristate data bus transceiver (XCVR). These two signals are DT/ R (data
transmit/ receive ) and DEN (data enable). The DEN signal enables the data bus
transceiver, and the DT/ R signal selects the direction of data on the data bus (D0-D7).

MRDC
4 Bus controller issues
MWTC memory- read
IORC
command ( MRDC )
IOWC
DT/ R
DEN
ALE

Bus controller
1 (8288) 2 Bus controller issues
8088 sends DT/ R and DEN
status code signals to data bus
to bus 1 0 1 XCVR
controller
for memory EN
S2 S1 S0
read.
.
. Address
. Address is held on
20 bit
latches bus
AD7 .
.. .
. .
AD0

.
. Data bus
. XCVR
. 8 bit Data Bus

Microprocessor 5 Data byte is 3 Data bus XCVR is enabled and

transferred to placed in the receive mode so
(8088) microprocessor from data can be transferred to the
data bus microprocessor from the memory
location selected by the address
code

Figure- Example of an 8088 memory- read operation

18
21. Explain the example of an 8088 memory - write operation. (20 Marks)

When the bus controller receives the status code of write operation, it sends a write
command ( IOWC or MWTC ) to the appropriate device, and it also sends two signals to
the tristate data bus transceiver (XCVR). These two signals are DT/ R (data
transmit/ receive ) and DEN (data enable). The DEN signal enables the data bus
transceiver, and the DT/ R signal selects the direction of data on the data bus (D0-D7).

MRDC
4 Bus controller issues
MWTC memory- write
IORC
command ( MWTC )
IOWC
DT/ R
DEN
ALE

Bus controller
1 (8288) 2 Bus controller issues
8088 sends DT/ R and DEN
status code signals to data bus
to bus 1 1 1 XCVR
controller
for memory EN
S2 S1 S0
write.
.
. Address
. Address is held on
20 bit
latches bus
AD7 .
.. .
. .
AD0

.
. Data bus
. XCVR
. 8 bit Data Bus

Microprocessor 5 Data byte is 3 Data bus XCVR is enabled and

transferred from placed in the transmit mode so
(8088) microprocessor to data data can be transferred from the
bus microprocessor to the memory
location selected by the address
code

Figure- Example of an 8088 memory- write operation

19
22. (a) Define the term DMA. (5 Marks)
(b) Compare a memory I/O data transfer handled by the CPU to a DMA transfer.
(15 Marks)

(a) The technique of data transfer called direct memory access (DMA). DMA bypass the
CPU for certain types of data transfers, thus eliminating the time consumed by the normal
fetch and execute cycles required for each read or write operation.

(b)

CPU

Data
Bus

IOWC
MRDC

Figure-(a) A memory I/O transfer handled by CPU

CPU

Data
Bus

MEMR IOW
RAM DMA I/O port
controller

Figure-(b) A DMA transfer

20
23. Describe the internal buses system in a typical system in a typical personal computer.
(10 Marks)

Main
Coprocessor Microprocessor
Memory

Cache

Local bus

PCI bus
controller

PCI devices
PCI bus
(card slots)

ISA bus
controller

ISA devices
ISA bus
(card slots)

Figure (a) - Simplified illusion of the basic bus system in a typical personal computer

21
24. Describe the RS-232 C bus (25 pins). (10 Marks)

PIN
Protective ground
1
Transmitted data (TD)
*2
Received data (RD)
*3
Request to send (RTS)
4
Clear to send (CTS)
5
Data set ready (DSR)
6
Signal ground
*7
Data carrier detect (DCD)
8
9 Test Pin
10 Test Pin
11 Unassigned
Secondary RCVD line signal detect
12
DTE Secondary CTS (SCTS) DCE
13
Secondary TD (STD)
14
Transmission timing
15
Secondary RD (SRD)
16
Receiver timing
17
Local loopback (LL)
18
Secondary RTS (SRTS)
19
Data terminal ready (DTR)
20
Remote loopback (RL)
21
Ring indicator
22
Data rate select
23
Transmit signal timing
24
Test Mode (TM)
25

Figure (b) – Full RS-232C 25- pin interface with typical personal configuration indicated
by blue and three signals marked by an asterisk (pins 2,3,7)

22
Instrumentation and Data Acquisition

IT (2033)

for

Second Semester

Sample Question
Q1. Describe the features of 8259APIC. (5 marks)
Q2. Explain I/O devices requesting interrupt service. (10 marks)
Q3. Explain interrupt service routines. (10 marks)
Q4. Explain DMA controllers. (5 marks)
Q5. Explain initialization required for DMA control. (10 marks)
Q6. Explain DMA modes. (10 marks)
Q7. Explain Repeat String Instruction. (10marks)
Q8. Draw the timing chart of 8-bit memory access. (20marks)
Q9. Draw the timing chart of 16-bit memory access. (20 marks)
Q10. Draw the timing chart of 8-bit I/O access. (20 marks)
Q11. Draw the timing chart of 16-bit I/O access. (20 marks)
Q12. Explain Expanded memory system. (10 marks)
Q13. Explain ISA bus. (10 marks)
Q14. Explain the PCI ,COMPACT PCI and PXI bus. (10marks)
Q-15. Explain A/D boards (10-Marks)
Q-16.What is successive approximation A/D converter? (10-Marks)
Q-17. What is Flash A/D converter? (10-Marks)
Q-18.What is integrating A/D converter? (10-Marks)
Q-19 Explain D/A boards. (10-Marks)
Q-20 Explain digital to analog converters. (10-Marks)
Q-21. Explain digital I/O boards. (10-Marks)
Q-22. What is (EIA) RS-232 interface standard? (5-Marks)
Q-23. What is the functional circuit of EIA-232? (10-Marks)
Q-24 What is RS-485 interface standard? (5-Marks)
Q-25. What is comparison of the RS-232 and RS-485 interface standard? (5-Marks)
Instrumentation and Data Acquisition

IT (2033)

for

Second Semester

Sample Answer & Question

Q1. Describe the features of 8259APIC. (5 marks)
The 8259A PIC has the following features:
• IRQ inputs are prioritized with the lower numbered inputs having the
higher priority. When the slave PIC is cascaded into IRQ2 of the master
PIC on the PC/AT type systems, IRQ0 and IRQ1 have a higher priority
than the slave PIC IRQs (IRQS–IRQ15). However IRQ3–IRQ7 have a
lower priority than the slave PICs IRQ8–IRQ15
• Since IRQ2 is not available for expansion boards, any interrupt requests on
IRQ2 (from expansion boards originally designed for use in XT type boards)
are transparently routed to IRQ9 by the system board
• IRQs can be ndividually masked (enabled or disabled). This is performed by
writing to the PIC’s operation command register (OCWl) – a single byte
describing the interrupt status for the eight IRQ inputs
• It automatically issues the interrupt type bytes to the CPU during the INTA
cycles (see I/O devices requesting interrupt service p. 74). The master PIC can
generate interrupt types 08h to 00h, whilst the slave PIC (when available) is
programmed to generate interrupt types 70h to 77h, see Table 4.1 It
automatically tracks which interrupts are being serviced by the CPU, to
prevent multiple occurrences of the same interrupt
• IRQ inputs can be configured as edge-sensitive (normal) or level-sensitive via
the initialization command word (ICW) register

******************************

Q2. Explain I/O devices requesting interrupt service. (10 marks)

When an I/O device asserts an interrupt request, an ordered sequence of events

occurs, to direct the CPU to the interrupt service routine (ISR) that will service the
specific request.
The sequence of events is as follows:
• The I/O device hardware activates an interrupt request by asserting its IRQx
line from ‘low’ to ‘high’. This signal is usually ‘latched’ high by an interrupt
request latch on the I/O device and remains high until the latch is reset and the
interrupt is acknowledged (thus allowing further interrupts). These last tasks
are performed by the ISR (see Interrupt service routines, p. 75).
 • The interrupt controller receives this IRQx interrupt request and prioritizes it
with other requests that may be coming in or pending. The interrupt controller
will then send an interrupt request to the CPU on the INTR signal line under
the following conditions:
-This is the only interrupt request.
-A lower priority interrupt is in progress.
-Several interrupts are pending but this interrupt has the highest priority.
• If the CPU has interrupts enabled, it acknowledges the interrupt request by
sending two INTA pulses to the interrupt controller. The first freezes the
priority levels in the interrupt controller, while the second requests an 8-bit
pointer value, called the ‘interrupt type’.
• The interrupt controller places the 8-bit interrupt type onto the CPU data bus.
This ‘interrupt type’ byte is the means by which the CPU knows where to
look for the address of the interrupt service routine that will service the I/O
device.
• The CPU saves the information necessary to allow the program currently
being executed to resume execution at its next instruction upon completion of
the ISR.It does this by saving the current code segment instruction pointer
(CS:IP) and system FLAGS registers onto the stack.
The CPU finally fetches the instruction pointer (IP) and code segment (CS) value
from the interrupt vector table at the correct location for the interrupt being serviced,
and branches to this address.
******************************

Q3. Explain interrupt service routines. (10 marks)

These are listed below:

• Any CPU registers that might be used by the ISR, (registers that the
interrupted program could have been using), should be saved by pushing their
current values onto the stack. Only those registers whose values will be
altered need be saved, although it is safe programming practice to save all
registers (remember that the CS, IP and FLAGS registers are automatically
saved by the CPU).
 • Since the interrupt enable flag bit IF in the FLAGS register has been cleared
and interrupts to the CPU are disabled, a decision must be made whether to set
this flag bit and re-enable INTR interrupts to the CPU
• An EOI command must be sent to the master PIC to re-enable interrupts on the
same IRQ line. Where an interrupt occurred on one of the interrupt lines
IRQ8–IRQ15 via the slave PIC an EOI command must be sent to this PIC as
well.
• Upon completion of the ISR all registers saved onto the stack at the start of the
ISR are retrieved and restored to their original values.
• The very last instruction executed within the ISR is the IRET (return from
interrupt) instruction. This signals the CPU that the ISR is complete. Upon
exe-cuting this command the CPU retrieves the original CS, IP and FLAGS
register values from the stack and begins executing the interrupted program at
the segmented memory location CS:IP.
******************************

Q4. Explain DMA controllers. (5 marks)

The 8237-5 DMA controller contains:

• A two-byte address register containing the starting memory address from
which data must be read.
• A two-byte address register containing the current address to which data must
be written.
• A two-byte count register, which holds the number of bytes/words to be
written in total.
• A two-byte count register containing the current bytes/word count of each
channel.
• Control lines that allow the reading/writing of data from/to memory.
As each device only supports 16-bit addresses (limiting access to 64 kB of
memory), each DMA channel has an associated ‘page register’ in system I/O memory
to provide the added upper 4 address lines required to address the complete 20-bit (1
MB) system base address space.

Q5. Explain initialization required for DMA control. (10 marks)

Before any DMA operation can occur, the DMA controller must be initialized.
 Items requiring initialization are as follows:
• Select whether the DMA controller will read or write to memory.
• Configure the type of DMA data transfer. Four modes of DMA data transfer
are available:
- Single transfer mode
The DRQx signal must be asserted for every byte/word transferred.
- Block transfer mode
A single DRQx signal DMA request initiates the transfer of an entire
block of data.
- Demand transfer mode
Data is transferred as long as the DRQx signal DMA request is
asserted and the terminal count has not been reached.
- Cascade mode
All DMA channels are programmed for single transfer mode.
• The total number of bytes to be transferred is loaded into the appropriate total
byte/word count register. The current byte/word count register is then
automatically initialized.
• The memory address to which the first data byte will be read/written is loaded
into the start memory address register. The current memory address register is
automatically initialized.
• The 4-bit page register corresponding to the upper four bits of the 20-bit
address is written using the I/O port addresses of the PC.
• The DMA channel priorities should be set. When the PC is booted up, the
ROM BIOS sets the priorities so that the lowest numbered channel has the
highest priority.
• The DMA controller(s) channels that are to be used should be enabled.
Channels to be enabled have the channel mask register bits cleared.

******************************

Q6. Explain DMA modes. (10 marks)

The DMA system is based on two 8237-type DMA controllers. Controller 2 provides
DMA channels 5, 6 and 7 as well as the cascade input for controller 1
To overcome this limitation, the following techniques may be used:
Dual channel gap-free DMA
At the end of the first 64 kB block of data, the board immediately switches to
a second DMA channel and begins transferring the second block of data on it. The
host software reprograms the first DMA channel to point the following (third) 64 kB
block. When the second block is complete, the board immediately reverts back to the
first DMA channel and continues the transfer, which allows the software to reprogram
the second DMA channel. This ping-pong approach continues, filling up memory,
until all the data has been transferred. This method is called dual channel gap-free
DMA. Its advantages are that it can access virtually all memory up to 16 MB. It can
operate without program intervention if the DMA device provides an interrupt-on-
terminal count signal, but it uses up two of the six available DMA channels.
Circular buffer DMA
A buffer (up to 64 kB) may be set up in memory, and the DMA controller
programmed to transfer data into the buffer. The controller is programmed for auto-
initialize so that when it reaches the end of the buffer, it immediately continues
transfer to the beginning of the buffer. The host computer software must process or
transfer the data out of the buffer before the next cycle overwrites the previous cycle's
data. This is called circular buffer DMA. The ad-vantages are that it is simpler to
implement, uses less memory, and allows processing while transferring the data.
However, it generally requires much program intervention.

Normal DMA using on-board FIFO

The DMA device uses a single DMA channel but it has an on-board cache
large enough to store buffer data while the DMA controller is reprogrammed to point
to the starting address of the next 64 kB memory block. This is normal DMA as far as
the host PC is concerned. It allows gap-free DMA using one channel, with the
additional hardware on the expansion board. The host DMA system must operate fast
enough to be able to transfer not only the data that has built up in the cache while the
DMA channel was being reprogrammed, but also subsequent data arriving at the
cache. The process may also operate completely in the background if the board has
an interrupt-on-terminal count signal.
 ******************************
Q7. Explain Repeat String Instruction. (10marks)

To obtain a series of data samples from a board, the program initializes a

counter register, sets up a destination memory address register and executes the repeat
input string word instruction (REP INSW), giving the I/O address of the board’s data
register. The instruction automatically reads a sample value, stores it at the memory
address pointed to by the desti-nation address register, increments this register,
decrements the counter and continues trans-ferring samples until the counter reaches
zero. This method has distinct advantages, but the data acquisition board must meet
certain requirements.
The advantages are:
• Very high speed (slightly higher than DMA because there is no
overhead associated with the single-sample nature of PC type DMA)
• Very simple to program
• Does not need to use hardware methods at all
The requirements are:
• Since the PC just reads a block of converted samples, the board must have an
on-board or external pacer clock, convert all the readings without program
inter-vention, as well as have a fair-sized sample buffer to pre-store the
samples in readiness for the REP INSW instruction.
• The board must have a status flag to indicate the ‘buffer half full’ or ‘nearly
full’ condition, so that the program can execute the REP INSW loop. If this
flag is cap-able of causing an interrupt request, collection may be done in the
background, otherwise the program must poll the status flag at regular
intervals to check if the data is ready for transfer.
• As high-level language compilers do not support these instructions, the code
must be written in assembly language.

******************************

Q8. Draw the timing chart of 8-bit memory access. (20marks)

The three timing charts of 8-bit memory access:
• A standard 6-BCLK cycle
• A circle which the expansion board extends( to seven BCLK) with
CHRDY
• A circle shortened by the expansion board to three BCLKs with the
/NOWS signal
******************************
Q9. Draw the timing chart of 16-bit memory access. (20 marks)
The three timing chart of 16-bit memory access:
• A standard 3-BCLK circle
• A circle which the expansion board extended (to six BCLKs) with
CHRDY
• A circle shortended by the expansion board to 2 BCLKs with the
/NOWS signal
******************************
Q10. Draw the timing chart of 8-bit I/O access. (20 marks)

The three tining chart of 8-bit I/O access:

• A standard 6 BCLK circle
• A circle which the expansion board extends (to seven BCLK) with
CHRDY
• A circle shortended bny the expansion board to 3 BCLKs with the
/NOWS signal
******************************
Q11. Draw the timing chart of 16-bit I/O access. (20 marks)
The timing chart of 16-bit I/O access:
• A standard 3 BCLK circle
• A circle that the expansion board extends (to 6 BCLK)with CHRDY
 ******************************

Q12. Explain Expanded memory system. (10 marks)

All PC processors running in real mode are limited to a memory space of 1

MB because only the first 20 address lines are available. (The same holds for DOS,
being a 16-bit operating system.) To make more memory available for applications, a
scheme was developed by Lotus, Intel, and Microsoft called expanded memory (LIM
EMS 4.0 is a common version). In ardware, a second linear array of memory, called
the logical expanded memory is designed into a system. This may be up to 32 MB in
size. A block of memory space is then set aside in the high memory area (normally 64
kB) and divided into four separate pages of 16 kB each. This acts as a window into
the expanded memory. Thus, four pages of the actual expanded memory are ccessible
at any one time through the window in high memory. These windows are called page
frames. The required portion of expanded memory is mapped into the page frame
through registers in the computer’s I/O space.
 The management of the memory is handled by an operating system extension
called the expanded memory manager (EMM).
The EMM has two main sections:
• The driver, which has some of the characteristics of a real device
driver, and includes initialization and output status functions.
• The manager, which acts as an interface between application software
and the expanded memory hardware.
The EMM provides the following services:
• Hardware and software module status
• Allocation and de-allocation of EMS pages
• Mapping of logical pages into the physical frame
• Support for multitasking operating systems
• Diagnostic routines
******************************
Q13. Explain ISA bus. (10 marks)

The ISA signal are divided into 4 groups according to their function:
• Address and data bus signal group
• Data transfer control signal group
• Bus arbitration signal group
• Utility signal group

Address and data bus signal group

These group contain the signal lines that are used to address memor and I/O
devices and the signal lines used to transfer the actual data.
D[7—0], D[15—8], LA[23—17], SA[19—0], /SBHE, AEN.
Data transfer control signal group
This group contains signals that are used to control data transfer cycles on the
bus.
BCLK, BALE, /MRDC, /SMRDC, /MWTC, /SMWTC, /IORC, /IOWC, CHRDY,
/NOWS, /M16, /IO16.
Bus arbitration signal group
These signals are used to arbitrate between devices anad the system board for
control of the bus.
DRQ[7--5] and DRQ[3--0] ,/DAK[7--5] and /DAK[3--0], T-C, /MASTER16,
/REFRESH B19.
Utility signal group
OSC, RESDRV, IRQ[15—14], IRQ[12—9], IRQ[7—3], /IOCHK.
******************************

Q14. Explain the PCI ,COMPACT PCI and PXI bus. (10marks)

The PCI or (Personal Computer Interface bus) is a relatively new addition to

the PC motherboard. Legacy bus systems such as the ISA and EISA were good in the
ays when only one application was running at a time. Now that the PC can run more
thanone application at a time, it is necessary to have a multi-card bus system. The PCI
bus does this by running at faster clock rates then the legacy buses and by temporarily
releasing the bus, therefore allowing other cards to have a chance to transmit or
receive data from the CPU. Card size is also a big advantage of the PCI bus. The
fingers on the PCI bus are smaller and more numerous. This makes the average PCI
card the same size as a legacy ISA card.
Smaller PCI cards can have more functions than huge EISA cards. This will be
a benefit for the manufacture (reduction in cost) and for the consumer (more functions
for the same or smaller price). Another spin off of the PCI bus is better plug and play.
The PCI local bus is a high-performance bus that provides a processor-
independent data path between the CPU and high-speed peripherals. PCI is a robust
interconnect mechanism designed specifically to accommodate multiple high
performance peripherals for graphics, full motion video, SCSI, LAN, etc.
The PCI bus is not a local bus but an intermediate bus. This allows the CPU
to talk to host memory, or the cache, over a very fast and short local bus, while the
PCI bus connected devices (and even ISA bus devices) do their own thing. A bridge is
used as a buffer / transmitter / receiver between the CPU bus (local bus) and the PCI
bus.
The legacy bus is allocated resources by IRQ and DMA control chips in
conjunction with the PCI bus system. The PCI devices still can use IRQs and DMA
but in a different way than legacy devices. The PCI bus has its own internal interrupts
called INT#…
In 1998, the compactPCI and PXI bus were developed to combine the
attributes of the PC’s CI bus with the industrial card connection system of the VME.
The VME bus had been used various forms for many years as an industrial bus rack
for mounting electronic PCBs. The CI bus is a very fast and easy way of connecting
the computer to the outside world. By mbining the PCI with the VME the best of both
worlds was accomplished. Instead of aving to open the PC and insert a PCI card, the
user can just slide the card into the front of e chassis. It uses a 5-row 2 mm-pitch
connector with impedance-matched pins and sockets. he integrated shielding system
doubles the bus card’s capacity from four to eight. The PXI ersion of the compactPCI
has extra features that the basic compactPCI does not. These clude timing and
triggering functions so multiple boards can perform synchronous data quisition, and
the ability of one card to trigger another without the intervention of the stem.

******************************
Q-15. Explain A/D boards (10-Marks)
Analog input (A/D) boards convert analog voltages from external signal
sources into a digital format, which can be interpreted by the host computer. The
functional diagram of a typical A/D board is shown in Figure and comprises the
following main components:
Input channel sample and hold circuits (for simultaneous sampling)
• Input multiplexer
• Input signal amplifier
• Sample and hold circuit
• A/D converter (ADC)
• FIFO buffer
• Timing system
• Expansion bus interface
Each of these components plays an important role in determining how fast and
how accurately the A/D board can acquire data.

Functional diagram of a typical A/D board

****************************************
Q-16.What is successive approximation A/D converter? (10-Marks)
A successive approximation A/D conversion is the most common and popular
direct A/D conversion method used in data acquisition systems because it allows high
sampling rates and high resolution, while still being reasonable in terms of cost. One
clear advantage of this device is that it has a fixed conversion time proportional to the
number of bits, n, in the digital output. Each successive bit, which doubles the ADCs
accuracy, increases the conversion time by the period T only. The functional diagram
of an n-bit successive approximation A/D converter is shown in Figure

Functional diagram of an n-bit successive approximation A/D converter

The successive approximation technique generates each bit of the output code
sequentially, starting with the most significant bit (MSB).
If the analog input signal is greater, the most significant bit (MSB) of the D/A
converter input is set to logic 1 and the next most significant bit of the D/A converter
input is set to logic 1. If the analog input signal was less, the MSB of the D/A input is
cleared to logic 0 and the next most significant bit of the D/A input is set to logic 1.
***********************
Q-17. What is Flash A/D converter? (10-Marks)
Simultaneously compares the input signal voltage to a reference voltage
determined by its position in the resistor series, and corresponding to the output code
of the device. Flash A/D conversion is quicker than other methods of A/D conversion
because each bit of the output code is found simultaneously, irrespective of the
number of bits-resolution. However, the greater the resolution of the device, the
greater the number of comparators required to perform the conversion. In fact, each
additional bit doubles the number of comparators, and therefore increases the size and
cost of the chip.

Functional diagram of an n-bit flash A/D converter

Flash A/D converters tend to be found in specialist boards, such as digital
oscilloscopes, real-time digital signal processing applications and general high-
frequency applications.
**************************************
Q-18.What is integrating A/D converter? (10-Marks)
Integrating A/D converters use an indirect method of A/D conversion,
whereby the analog input voltage is converted to a time period that is measured by a
counter. The functional diagram of a dual-slope integrating A/D converter is shown in
Figure

Functional diagram of an n-bit dual slope integrating A/D converter

Voltage appearing at V0
 At the start of the A/D conversion, a fixed counter is cleared to zero and the
unknown analog input voltage is applied to the input of the integrating amplifier. As
soon as the output of the integrating amplifier reaches zero, a fixed interval count
begins. After a predetermined count period, T, the count is stopped.
These devices are low speed. They are capable of high accuracy and resolution
at low cost. They are principally used in low frequency applications, such as
temperature measurement, in digital multimeters and instrumentation.

*********************************

Q-19 Explain D/A boards. (10-Marks)

D/A boards convert digital signals from a host computer into an analog format
for use by external devices such as actuators in controlling or stimulating a system or
process.
D/A boards fall into two main categories:
• Waveform generation boards
• Analog output boards
Waveform generation D/A boards
Waveform generation D/A boards are used in the high speed generation of
analog waveforms.
The functional diagram of a waveform generation D/A board is shown in
Figure and comprises the following main components:
• D/A converter (DAC)
• Output amplifier/buffer
• FIFO buffer
• Timing system
• Expansion bus interface
Each of these components plays an important role in determining the speed,
accuracy, and flexibility with which the D/A board can generate analog waveforms.

Analog output D/A boards

Unlike high speed, high resolution, waveform generation boards, more typical
analog output D/A boards, as shown in Figure and used in industrial control, multi-
function data acquisition boards often include two or more analog output channels,
applications which require many dedicated analog outputs are most efficiently
provided.
The D/A conversion sub-system is straightforward in design and can be
divided into two main functional components:
• D/A converter
• Output amplifier and buffer

Functional diagram of an analog output D/A board

Analog output D/A boards typically have between two and sixteen dedicated
output channels, each with its own D/A converter and where required output
buffer/amplifier.

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Q-20 Explain digital to analog converters. (10-Marks)
Digital to analog converters (D/A converters or DACs) accept an n-bit parallel
digital code as input and provide an analog current or voltage as output using an
operational amplifier. A D/A converter consists principally of a network of analog
switches, controlled by the input code, and a network of precision weighted resistors.
The switches control currents or voltages derived from a precise reference voltage and
provide an analog output current or voltage. The output current/voltage represents the
ratio of the input code to the full-scale voltage of the reference source. The main types
of current output DACs and their specific important parameters are discussed in the
following sections.

Weighted-current source D/A converters

N-bit weighted-current source D/A converter

This method creates an output current, IT, which is the summation of the
weighted currents: the current contributed by each transistor set by the resistances R,
2R, 4R, 8R, etc. The selection of the currents to be summed is determined by the
digital code appearing at the input.
R-2R ladder D/A converters

N-bit R-2R ladder D/A converter

The principle of operation of the ladder network relies on the binary divisions
of the current as it flows through the ladder resistance network.
The main advantages, which make this type of DAC popular, are the easy
matching of resistances (R or 2R), the constant input resistance for the output
amplifier, and the fact that low resistor values can be used, thus ensuring high-speed
operations.

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Q-21. Explain digital I/O boards. (10-Marks)
Digital I/O interfaces are commonly used in a PC based DAQ systems to
provide monitoring and control for industrial processes, generate patterns for testing
in the laboratory and communicate with peripheral equipment such as data loggers
and printers which have parallel digital I/O capabilities.
Non-latched digital I/O
Non-latched digital I/O is the mode of operation in which the state of a digital
output line is updated immediately a digital value is written to the digital I/O port.
Non-latched digital I/O is the most common and simplest implementation used in
digital I/O interfaces and is supported by all boards with digital I/O lines. The
direction of the digital lines of a digital I/O port is conveniently set by software and
can be changed as many times as required.

Latched digital I/O

For applications that require handshaking of digital data, latched digital I/O is
used. In this mode of operation, an external signal determines when the data is either
input to or output from the digital I/O port. The signals that are used to control the
transfer of data are sometimes known as handshake lines.
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Q-22. What is (EIA) RS-232 interface standard? (5-Marks)
The EIA-232 standard consists of three major components, which define:
• Electrical signal characteristics
Electrical signals such as the voltage levels and grounding characteristics of
the interchange signals and associated circuitry.
• Interface mechanical characteristics
The mechanical characteristics of the interface between the DTE and DCE.
This section dictates that the interface must consist of a plug and socket, and
that the socket will normally be on the DCE.
• Functional description of the interchange circuits
This section defines the function of the data, timing and control signals used at
the interface between DTE and DCE.

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Q-23. What is the functional circuit of EIA-232? (10-Marks)

The EIA circuit functions are defined, with reference to the DTE, as follows:
• Pin 1: Protective ground (shield)
A connection is seldom made between the protective ground pins at each end.
Their purpose is to prevent hazardous voltages, by ensuring that the DTE and
DCE chassis are at the same potential at both ends. However, there is a danger
that a path could be established for circulating earth currents, so, usually the
cable shield is connected at one end only.
• Pin 2: Transmitted data (TXD)
This line carries serial data from pin 2 on the DTE to pin 2 on the DCE. The
line is held at MARK (or a negative voltage) during periods of line idle
• Pin 3: Received data (RXD)
This line carries serial data from pin 3 on the DCE to pin 3 on the DTE.
• Pin 4: Request to send (RTS)
The RTS line is a request to send from the DTE to the DCE. This line is used
in conjunction with the CTS line to do hardware control. The DCE will not
enable the CTS line until the DTE enables its RTS line.
• Pin 5: Clear to send (CTS)
 When a half-duplex modem is receiving, the DTE keeps RTS inhibited. When
it becomes the DTE’s turn to transmit, it advises the modem by asserting the
RTS pin. When the modem asserts the CTS, it informs the DTE that it is now
safe to send data.
• Pin 6: Data set ready (DSR)
This is also called DCE ready. In the answer mode, the answer tone and the
data set ready are asserted two seconds after the telephone goes off hook.
• Pin 7: Signal ground (common)
This is the common return line for the data transmit and receive signals. The
connection, pin 7 to pin 7 between the two ends, is always made.
• Pin 8: Data carrier detect (DCD)
This is also called the received line signal detector. Pin 8 is asserted by the
modem when it receives a remote carrier and remains asserted for the duration
of the link.
• Pin 20: DTE ready (or data terminal ready)
DTE Ready enables, but does not cause, the modem to switch onto the line. In
originate mode, DTE Ready must be asserted in order to auto dial. In answer
mode, DTE Ready must be asserted to auto answer.
• Pin 22: Ring indicator
This pin is asserted during a ring on the line.
• Pin 23: Data signal rate selector (DSRS)
When two data rates are possible, the higher is selected by asserting pin 23.

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24 What is RS-485 interface standard? (5-Marks)

The EIA RS-485 is the most versatile of the EIA standards, and is an
expansion of the RS- 422 standard. The RS-485 standard was designed for two-wire,
half duplex, balanced multidrop communications, and allows up to 32 line drivers and
32 line receivers on the same line.
RS-485 provides reliable serial communications for:
• Distances of up to 1200 m
• Data rates of up to 10 Mbps
• Up to 32 line drivers permitted on the same line
• Up to 32 line receivers permitted on the same line

RS-485 multidrop networks

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Q-25. What is comparison of the RS-232 and RS-485 interface standard? (5-
Marks)

Comparisons of main features of EIA-232 and EIA-485

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