MIELOAP03

Implementación de sistemas digitales VHDL

TAREA 7_ Muestra de diferentes números en cada digito de 7 segmentos provenientes de un contador

__Sanchez _1937480

Nombre completo del alumno: Raúl Sanchez Hernandez

Número de matrícula del alumno: 1937480

Fecha: 19 febrero 2019

Anexos a esta tarea: resumen

Nombre del archivo (con extensión) Descripción

Ejemplo7.mp4 Video

Practica 7- Instrucción
• Muestra de diferentes números en cada digito de 7 segmentos provenientes de un contador
cada uno. Con los PB btnL, btnU, btnC, btnD, se incrementa la cuenta manual cada vez que le
oprime manualmente dichos botones . Y Se muestran una cuenta hexadecimal (del 0 al F)

3
E3
8
ARCHIVO VHDL
A
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17.02.2019 16:36:17
-- Design Name:
-- Module Name: ejemplo7 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
 MIELOAP03

Implementación de sistemas digitales VHDL

--
----------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Descomente la siguiente declaración de la biblioteca si usa

-- Funciones aritméticas con valores firmados o no firmados.
--use IEEE.NUMERIC_STD.ALL;

-- Descomente la siguiente declaración de la biblioteca si crea una instancia

-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ejemplo7 is
Port ( clk : in STD_LOGIC;
btnL : in STD_LOGIC;
btnU : in STD_LOGIC;
btnC : in STD_LOGIC;
btnD : in STD_LOGIC;
an : inout STD_LOGIC_VECTOR (3 downto 0);
seg : out STD_LOGIC_VECTOR (6 downto 0));
end ejemplo7;

architecture Behavioral of ejemplo7 is

signal count_int0:std_logic_vector (3 downto 0):= "0000";

SIGNAL flipflops0 : STD_LOGIC_VECTOR(1 DOWNTO 0); --input flip flops
SIGNAL counter_set0 : STD_LOGIC; --sync reset to zero
SIGNAL counter_out0 : STD_LOGIC_VECTOR(19 DOWNTO 0) := (OTHERS => '0');
--counter output
SIGNAL result0 : STD_LOGIC;
signal count_int1:std_logic_vector (3 downto 0):= "0000";
SIGNAL flipflops1 : STD_LOGIC_VECTOR(1 DOWNTO 0); --input flip flops
SIGNAL counter_set1 : STD_LOGIC; --sync reset to zero
SIGNAL counter_out1 : STD_LOGIC_VECTOR(19 DOWNTO 0) := (OTHERS => '0');
--counter output
SIGNAL result1 : STD_LOGIC;
signal count_int2:std_logic_vector (3 downto 0):= "0000";
SIGNAL flipflops2 : STD_LOGIC_VECTOR(1 DOWNTO 0); --input flip flops
SIGNAL counter_set2 : STD_LOGIC; --sync reset to zero
SIGNAL counter_out2 : STD_LOGIC_VECTOR(19 DOWNTO 0) := (OTHERS => '0');
--counter output
SIGNAL result2 : STD_LOGIC;
signal count_int3:std_logic_vector (3 downto 0):= "0000";
SIGNAL flipflops3 : STD_LOGIC_VECTOR(1 DOWNTO 0); --input flip flops
SIGNAL counter_set3 : STD_LOGIC; --sync reset to zero
 MIELOAP03

Implementación de sistemas digitales VHDL

SIGNAL counter_out3 : STD_LOGIC_VECTOR(19 DOWNTO 0) := (OTHERS => '0');

--counter output
SIGNAL result3 : STD_LOGIC;
signal divisor:std_logic_vector(25 downto 0);
signal one:std_logic;
signal a:std_logic_vector (3 downto 0):="0111";
signal b:std_logic_vector (3 downto 0):="0111";
signal numero:std_logic_vector (3 downto 0);

begin

counter_set0 <= flipflops0(0) xor flipflops0(1); --Determine cuándo iniciar / reiniciar el

contador
counter_set1 <= flipflops1(0) xor flipflops1(1); --Determine cuándo iniciar / reiniciar el
contador
counter_set2 <= flipflops2(0) xor flipflops2(1); --Determine cuándo iniciar / reiniciar el
contador
counter_set3 <= flipflops3(0) xor flipflops3(1); --Determine cuándo iniciar / reiniciar el
contador

PROCESS(clk)
BEGIN
IF(clk'EVENT and clk = '1') THEN
flipflops0(0) <= btnL;
flipflops0(1) <= flipflops0(0);
If(counter_set0 = '1') THEN --Reinicie el contador porque la entrada está
cambiando
counter_out0 <= (OTHERS => '0');
ELSIF(counter_out0(19) = '0') THEN --El tiempo de entrada de la tabla aún no se ha
cumplido.
counter_out0 <= counter_out0 + 1;
ELSE --tiempo de entrada estable se cumple
result0 <= flipflops0(1);
END IF;
END IF;
END PROCESS;

process(result0)
begin
if result0='1' and result0'event then

count_int0<= count_int0 + 1;

end if;
end process;

with numero SELect

seg<= "1111001" when "0001", --1
"0100100" when "0010", --2
"0110000" when "0011", --3
"0011001" when "0100", --4
 MIELOAP03

Implementación de sistemas digitales VHDL

"0010010" when "0101", --5

"0000010" when "0110", --6
"1111000" when "0111", --7
"0000000" when "1000", --8
"0010000" when "1001", --9
"0001000" when "1010", --A
"0000011" when "1011", --b
"1000110" when "1100", --C
"0100001" when "1101", --d
"0000110" when "1110", --E
"0001110" when "1111", --F
"1000000" when others; --0

PROCESS(clk)
BEGIN
IF(clk'EVENT and clk = '1') THEN
flipflops1(0) <= btnU;
flipflops1(1) <= flipflops1(0);
If(counter_set1 = '1') THEN --Reiniciar el contador porque la entrada está
cambiando
counter_out1 <= (OTHERS => '0');
ELSIF(counter_out1(19) = '0') THEN --tiempo de entrada estable aún no se cumple
counter_out1 <= counter_out1 + 1;
ELSE --tiempo de entrada estable se cumple
result1 <= flipflops1(1);
END IF;
END IF;
END PROCESS;

process(result1)
begin
if result1='1' and result1'event then

count_int1<= count_int1 + 1;

end if;
end process;

PROCESS(clk)
BEGIN
IF(clk'EVENT and clk = '1') THEN
flipflops2(0) <= btnC;
flipflops2(1) <= flipflops2(0);
If(counter_set2 = '1') THEN --Reiniciar el contador porque la entrada está
cambiando
counter_out2 <= (OTHERS => '0');
ELSIF(counter_out2(19) = '0') THEN --tiempo de entrada estable aún no se cumple
counter_out2 <= counter_out2 + 1;
ELSE --tiempo de entrada estable se cumple
result2 <= flipflops2(1);
END IF;
 MIELOAP03

Implementación de sistemas digitales VHDL

END IF;
END PROCESS;

process(result2)
begin
if result2='1' and result2'event then

count_int2<= count_int2 + 1;

end if;
end process;

PROCESS(clk)
BEGIN
IF(clk'EVENT and clk = '1') THEN
flipflops3(0) <= btnD;
flipflops3(1) <= flipflops3(0);
If(counter_set3 = '1') THEN --Reiniciar el contador porque la entrada está
cambiando
counter_out3 <= (OTHERS => '0');
ELSIF(counter_out3(19) = '0') THEN --tiempo de entrada estable aún no se cumple
counter_out3 <= counter_out3 + 1;
ELSE --tiempo de entrada estable se cumple
result3 <= flipflops3(1);
END IF;
END IF;
END PROCESS;

process(result3)
begin
if result3='1' and result3'event then

count_int3<= count_int3 + 1;

end if;
end process;

process (clk)
begin
if clk='1' and clk'event then
divisor <= divisor + 1;
if divisor>= "10111110101111000010000000" then
divisor<="00000000000000000000000000";
one<= not one;
end if;
end if;
end process;

process (divisor(10))
 MIELOAP03

Implementación de sistemas digitales VHDL

begin
if divisor(10)='1' and divisor(10)'event then
case a is
when "0111" => b <= "1011";
when "1011" => b <= "1101";
when "1101" => b <= "1110";
when "1110" => b <= "0111";
when others => b <= "0111";
end case;
an<=b;
a<=b;
end if;

end process;

numero <= count_int0 when an="0111" else

count_int1 when an="1011" else
count_int2 when an="1101" else
count_int3 when an="1110";

end Behavioral;

ARCHIVO CONSTRS

# Clock signal
set_property PACKAGE_PIN W5 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports
clk]

#7 segment display
set_property PACKAGE_PIN W7 [get_ports {seg[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
set_property PACKAGE_PIN W6 [get_ports {seg[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
set_property PACKAGE_PIN U8 [get_ports {seg[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
set_property PACKAGE_PIN V8 [get_ports {seg[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
set_property PACKAGE_PIN U5 [get_ports {seg[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
set_property PACKAGE_PIN V5 [get_ports {seg[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
set_property PACKAGE_PIN U7 [get_ports {seg[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]

set_property PACKAGE_PIN U2 [get_ports {an[0]}]

set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
set_property PACKAGE_PIN U4 [get_ports {an[1]}]
 MIELOAP03

Implementación de sistemas digitales VHDL

set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]

set_property PACKAGE_PIN V4 [get_ports {an[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
set_property PACKAGE_PIN W4 [get_ports {an[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]

#Buttons
set_property PACKAGE_PIN U18 [get_ports btnC]
set_property IOSTANDARD LVCMOS33 [get_ports btnC]
set_property PACKAGE_PIN T18 [get_ports btnU]
set_property IOSTANDARD LVCMOS33 [get_ports btnU]
set_property PACKAGE_PIN W19 [get_ports btnL]
set_property IOSTANDARD LVCMOS33 [get_ports btnL]

set_property PACKAGE_PIN U17 [get_ports btnD]

set_property IOSTANDARD LVCMOS33 [get_ports btnD]

OBSERVACIONES:

Cada vez que se oprime el botón btnL aumenta un digito de displey de 7 segmentos
0 1 23 4 5 6 7 8 9 A B C D E F; así respectivamente. btnU, btnC, btnD.

EVIDECIA: algunas muestras con 7 segmentos de salida.

89bE

538b
 MIELOAP03

Implementación de sistemas digitales VHDL

538C