NAME: E.

AJAY DATE:
ROLL NO: 18H65A0413 PAGE NO:
EXPERIMENT NO: 11

DESIGN OF 10 BIT SHIFT REGISTER

AIM: To design the 10 bit shift register using Xilinx ISE 9.2i with verilog HDL programming
language.

APPARATUS:
1. PERSONAL COMPUTER

2. XILINX ISE 9.2 SOFTWARE

THEORY:
A Universal shift register is a register which has both the right shift and left shift with
parallel load capabilities. Universal shift registers are used as memory elements in
computers. A Unidirectional shift register is capable of shifting in only one direction. A
bidirectional shift register is capable of shifting in both the directions. The Universal shift
register is a combination design of bidirectional shift register and a unidirectional shift
register with parallel load provision.
A n-bit universal shift register consists of n flip-flops and n 4×1 multiplexers. All the n
multiplexers share the same select lines(S1 and S0)to select the mode in which the shift
register operates. The select inputs select the suitable input for the flip-flops.

TEST BENCH:

module regg6_v;

// Inputs

reg sir;

reg si1;

reg c;

reg rst;

reg [9:0] pi;

reg [1:0] s;

// Outputs

wire so1;

ANURAG GROUP OF INSTITUTIONS ECE Department Basic circuits simulation lab

NAME: E.AJAY DATE:
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wire sor;

wire [9:0] q;

// Instantiate the Unit Under Test (UUT)

shift uut (

.so1(so1),

.sor(sor),

.q(q),

.sir(sir),

.si1(si1),

.c(c),

.rst(rst),

.pi(pi),

.s(s)

);

initial begin

// Initialize Inputs

rst=1;c=1;s=1;sir=1;si1=1;pi=10'b1101100010;#10;

rst=0;s=3;sir=0;si1=0;pi=10'b1101100010;#10;

repeat (10)

begin

rst=0;s=1;sir=0;si1=0;pi=10'b1101100010;#10;

end

rst=1;s=1;sir=1;si1=1;pi=10'b1101100010;#10;

rst=0;s=3;sir=0;si1=0;pi=10'b1101100010;#10;

repeat (10)

ANURAG GROUP OF INSTITUTIONS ECE Department Basic circuits simulation lab

NAME: E.AJAY DATE:
ROLL NO:18H65A0413 PAGE NO:

begin

rst=0;s=2;sir=0;si1=0;pi=10'b1101100010;#10;

end

rst=1;s=1;sir=1;si1=0;pi=10'b0000000000;#10;

rst=0;s=1;sir=0;si1=0;pi=10'b1101100010;#10;

rst=0;s=1;sir=1;si1=0;pi=10'b1101100010;#10;

rst=0;s=1;sir=0;si1=0;pi=10'b1101100010;#10;

rst=0;s=1;sir=0;si1=0;pi=10'b1101100010;#10;

rst=0;s=1;sir=0;si1=0;pi=10'b1101100010;#10;

rst=0;s=1;sir=0;si1=0;pi=10'b1101100010;#10;

rst=0;s=1;sir=0;si1=0;pi=10'b1101100010;#10;

rst=0;s=1;sir=0;si1=0;pi=10'b1101100010;#10;

rst=0;s=1;sir=1;si1=0;pi=10'b1101100010;#10;

rst=0;s=1;sir=0;si1=0;pi=10'b1101100010;#10;

//leftshift

rst=1;s=2;sir=1;si1=1;pi=10'b1101100010;#10;

rst=0;s=2;sir=1;si1=0;pi=10'b1101100010;#10;

rst=0;s=2;sir=1;si1=1;pi=10'b1101100010;#10;

rst=0;s=2;sir=1;si1=0;pi=10'b1101100010;#10;

rst=0;s=2;sir=1;si1=0;pi=10'b1101100010;#10;

rst=0;s=2;sir=1;si1=0;pi=10'b1101100010;#10;

rst=0;s=2;sir=1;si1=1;pi=10'b1101100010;#10;

rst=0;s=2;sir=1;si1=1;pi=10'b1101100010;#10;

rst=0;s=2;sir=1;si1=0;pi=10'b1101100010;#10;

rst=0;s=2;sir=1;si1=1;pi=10'b1101100010;#10;

ANURAG GROUP OF INSTITUTIONS ECE Department Basic circuits simulation lab

NAME: E.AJAY DATE:
ROLL NO:18H65A0413 PAGE NO:

rst=0;s=2;sir=1;si1=1;pi=10'b1101100010;#10;

//stable state

rst=0;s=3;sir=1;si1=1;pi=10'b1101100010;#10;

end

always #5 c=~c;

endmodule

SOURCE CODE:
module shift(so1,sor,q, sir,si1,c,rst,pi,s);

output reg so1,sor;output reg [9:0]q;

input sir,si1,c,rst;input [9:0]pi;input [1:0]s;

always@(posedge c)

begin

if(rst==1)

q<=10'b0000000000;

else

case(s)

2'b00:q<=q;

2'b01:q<={sir,q[9:1]};

2'b10:q<={q[8:0],si1};

2'b11:q<=pi;

endcase

end

always@(q)

begin

so1=q[9];

ANURAG GROUP OF INSTITUTIONS ECE Department Basic circuits simulation lab

NAME: E.AJAY DATE:
ROLL NO:18H65A0413 PAGE NO:

sor=q[0];

end

endmodule

RTL BLOCK DIAGRAM:

RTL SCHEMATIC DIAGRAM:

ANURAG GROUP OF INSTITUTIONS ECE Department Basic circuits simulation lab

NAME: E.AJAY DATE:
ROLL NO:18H65A0413 PAGE NO:

APPLICATIONS:.
Registers are used in digital electronic devices like computers as

Temporary data storage

Data transfer

Data manipulation

As counters.

Many of the digital system operations like division, multiplication are performed by using
registers.

Counters are used as Digital clocks, Frequency counters, Binary counters etc.

SIMULATION WAVEFORM:

PERCAUTIONS:
Make sure that there is no syntax error and verify the functionality of the program.

ANURAG GROUP OF INSTITUTIONS ECE Department Basic circuits simulation lab

NAME: E.AJAY DATE:
ROLL NO:18H65A0413 PAGE NO:

SYNTHESIS REPORT:
=========================================================================

* Final Report *

=========================================================================

Final Results

RTL Top Level Output File Name : tff.ngr

Top Level Output File Name : tff

Output Format : NGC

Optimization Goal : Speed

Keep Hierarchy : YES

Target Technology : Automotive 9500XL

Macro Preserve : YES

XOR Preserve : YES

Clock Enable : YES

wysiwyg : NO

Design Statistics

# IOs :4

Cell Usage :

# BELS :3

# GND :1

# INV :2

# FlipFlops/Latches :2

# FDCE :2

# IO Buffers :4

# IBUF :2

ANURAG GROUP OF INSTITUTIONS ECE Department Basic circuits simulation lab

NAME: E.AJAY DATE:
ROLL NO:18H65A0413 PAGE NO:

# OBUF :2

=========================================================================

CPU : 1.82 / 1.91 s | Elapsed : 2.00 / 2.00 s

Total memory usage is 150508 kilobytes

Number of errors : 0 ( 0 filtered)

Number of warnings : 0 ( 0 filtered)

Number of infos : 0 ( 0 filtered)

RESULT:

Verilog code in behaviourial modeling is implemented for designing 10 bit shift register using
Xilinx ISE 9.2ISE. Synthesis report is obtained and simulation is done by using ISE simulator
for 10 bit shift register using different input combinations. The simulation result is verified with
the truth table.

ANURAG GROUP OF INSTITUTIONS ECE Department Basic circuits simulation lab