Sequential Circuit

The sequential circuit receives binary information from external input that, together with the
present state of the storage elements, determine the binary value of outputs. The outputs in a
sequential circuit are a function not only of the inputs, but also of the present state of the storage
elements. To realize sequential circuit in addition to AND, OR and NOT gates, flip-flop are also
required. Example of sequential circuit are: registers, shift-registers, counters etc.

Latch
Latches means to hold or lock something until we does not change information. Latches are the
basic building blocks using which flip flop are constructed. Latches have capacity to store one bit
until necessary. To implement the concept of latches we can use NAND or NOR gate but its
operation can be illustrate simply using NOT gate. To know whether the latches are working
correctly or not two output must be complemented each other otherwise its operation is wrong. It
does not mean that latches store two bit information it just a complement of each other.

Here input and output are found in Q i.e. when we put Qn=0 initially then Output is obtained in
Qn+1

Flip flop
Flip flop is a bistable device. It has two stable states: its output remains either high or low. the high stable
state, i.e. 1 is called SET . The other stable state low i.e. 0 is called RESET. Its property is to remain in
one state indefinitely until it is changed by an input signal to switch over to the other state. So, it can store
binary bit either 1 or 0 either 1 or 0. Thus it has storing capability, i.e. memory. It is a basic memory
element or storage cell. A storage element in a clock sequential circuit are called flip flop.

SR Flip flop
The SR flip flop is a circuit with two cross coupled NOR (or NAND) gate and two inputs labeled
S for Set and R for Reset. Here, output of one gate feeds back to the input of another and vice
versa. The output of one gate is complement to that of another gate. To meet the functionality, if
we use NOR gates in SR flip flop, the input of first gate is labeled as R and second gate is
labeled as S but with SR flip flop with NAND gate the first gate is labeled as S and second gate
is labeled as R. It is a sequential circuit to get the output, the present input and present state (i.e.
output is important). Here the main things is to get the next state of output. If the present state
and next sate is same then we called of latch or memory state.
SR Flip Flop using NOR gate

For the observation of truth table of SR Flip flop using NOR gate first construct the truth table of
NOR gate
INPUT OUTPUT
A B C
0 0 1
0 1 0
1 0 0
1 1 0

To analysis the S-R Flip flop we consider the three different cases
Case-I : Let S=0 and R=1
According to the property of NOR gate if any one input is 0 among two input then output also 0 so
Q = 0 and Q' = 1. To verify this output value, when R=1 then it does not important whether the next
input is 0 or 1 because in both case i.e. in 0 or 1 the output of NOR gate which include R is 0 i.e. Q = 0 .
The output value of Q is input to the next NOR gate which consist the S=0 . I n this gate S=0 and next
input is 0 come from previous NOR gate then output of this gate Q' = 1 since in NOR gate when both
input are 0 then its output is 1.
Here, we want to store the data and after storing, we remove this input values then S= 0 and R= 0 but the
output does not change, then verify the above case with putting Q = 0 and Q' = 1 and we have clear that
by removing input value the output does not change , which is same as the first case.
Then the condition S= 0 and R= 0 , Q = 0 and Q' = 1 is called memory
Case –II : Let S =1 and R = 0
According to the truth table of NOR gate if any one or all input is 1 then output is 0. So, Q' = 0. This
output Q' is connected with R in next NOR gate where the value of R=0 .Then output of NOR gate when
both input is 0 is 1 i.e. Q = 1. So, when S= 1 and R= 0 then output Q = 1 and Q' = 0
Again remove input then S= 0 and R= 0 in the above case, here input is reset but output is saved i.e. Q = 1
and Q' = 0 verifying this using above logic circuit. So, S= 0 , R= 0 ,Q = 1 and Q' = 0 is memory.
Case-III: S = 1 and R= 1
By using the truth table of NOR gate, when both input is 1 then its output is 0. Suppose in the case of
gate which include R =1 its output is 0 i.e. Q = 0 (it is not concern the next input state of this gate ).And
this output is input to the next NOR gate which include S=1 again the output of this gate also 0 i.e. Q' =
0 . Which is invalid case because value of Q never equal to the value of Q'. There is something wrong in
configuration .
But this is not only problem if we make S=0 and R=0 then using the output Q= 0 and Q' = 0 new value of
Q, Q' become Q = 0 and Q' = 1. So output value of this case is not saved in memory. This case is neither
valid nor used (NVNU).

In summary it is written as
S R Q Q'
0 0 MEMORY

0 1 0 1

1 0 1 0
1 1 NOT USED

Clocked S-R Flip Flop

A clock signal is added to the flip-flop (latch) to control the instant at which the flip flop changes the state
of its output. Here two additional AND gate with clock is used [when we design flip flop with NOR gate].
When clock is low the outputs of AND gates will be forced to be low and hence the state of the flip flop is
not changed. It remains the previous state. The changes in R and S has no effect on the flip flop output Q.
Thus the flip flop disable when clock is low.
When clock is high the outputs of AND gates will respond to the changes in inputs R and S. The flip flop
will now change its output according to the set or reset input. Thus the flip flop is enabled when clock is
high.
Step:1 When value of clock is low then the value of S and R is not importance, that is, the value of Q and
Q' is remain in previous state
step :2 When the clock is high
check the state of flip flop as previous S-R Latch in different values of S and R which
satisfy the following truth table(Previous truth table).

S R Q Q' Remarks
1 0 1 0 Set
0 0 1 0 No change

0 1 0 1 Reset

0 0 0 1 No change

1 1 - - Forbidden

J-K Flip Flop

One of the most useful and versatile flip flop is the JK flip flop the unique features of JK flip flop
are:

1. If the J and K input are both at 1 and the clock pulse is applied, then the output will
change state(toggle)
2. If both J and K inputs are at 0 and the clock is applied there will be no change in the state
(i.e. in memory state)
 logic symbol
Truth table
J K Qn Q(n+1)
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

Function table
J K Qn+1
0 0 Memory state
0 1 Reset
1 0 Set
1 1 Toggle

When J=0 and K=0

These J and K inputs disable the both NOR gates, therefore clock pulse have no effect on the flip
flop. In other words, Qn+1 remain in On state.

When J=0 and K=1

The lower NOR gate is disable and the upper NOR gate is enabled. The flip flop will be reset
(When Qn=0 or 1)

When J=1 and K=0

The upper NOR gate is disable and the lower NOR gate is enabled. The flip flop will be in set
state(When Qn=0 or 1)

When J=1 and K=1

If Qn=0 the upper NOR gate is disabled and the upper NOR gate is enabld. This will set the flip
flop and hence Qn+1 will be 1. on the other hand, if Qn=1, the upper NOR gate is enabled and
flip flop will be reset and hence Qn+1will be 0. In other words, when J and K are both high, the
clock pulses cause the JK flip flop to toggle

T Flip Flop
This is a simpler version of the J-K flip flop. Both the J and K inputs are connected together and
thus are also called a single input J-K flip flop. T flip flop act as a toggle switch. Toggle means
to switch over to the opposite state

Logic symbol
Truth Table

T Qn Qn+1
0 0 0

0 1 1
1 0 1
1 1 0

Function Table
T Qn+1

0 Qn

1 Qn’
D Flip Flop
D flip-flops are used to eliminate the indeterminate state that occurs in RS Flip-flop. D flip-flop
ensures that R and S are never equal to one at the same time. D and CP are the two inputs of the .

Clock D Qn Qn+1
0 x No Change
1 0 0 0

1 1 1 1