U.S.N.

BMS College of Engineering, Bangalore-560019

(Autonomous Institute, Affiliated to VTU, Belgaum)
December 2015 Semester End Main Examinations
Course: DIGITAL ELECTRONICS Duration: 3 Hours
Course Code: 15ES3GCDEC Max Marks: 100
Date: 15.12.2015

Instruction: Answer any five full questions choosing one from each unit.

UNIT-I
1. a) Simplify the following Boolean function using Quine McCluskey method 10
F(w,x,y,z) = ∑ ( ) ( )
b) Design a system to accept a 4 bit input and generate an output whenever the input 10
code is divisible by either 3 or 5 and represent the output using 4x1 multiplexer
OR
2. a) Design a combinational logic circuit to output the 2’s complement of a 4 bit 10
binary number. Construct the truth table. Simplify each output function using K-
maps and write the reduced equations. Draw the result in logic diagram
b) using the smallest size PROM PLD implement the decimal arithmetic equation 10
f(a) == 2a+3 for 0<= a<= 7 where f(a) and ‘a’ are in binary
UNIT-II
3. a) Explain the application of SR latch as a switch de-bouncer. Also draw the timing 06
diagrams associated with it.
b) Obtain the characteristic equations for the following. Also write the excitation 04
table. i) SR Flip-flop ii) JK Flip-flop
c) Explain 0’s and 1’s catching with reference to Master-Slave flip-flops. How this 10
problem of catching can be avoided? Also draw relevant timing diagrams
UNIT-III
4. a) Design a synchronous counter using T flip flops for the sequence 0, 1, 2, 4, 5, 6, 08
0, 1, 2, …….Is the counter self-starting? Draw the state diagram Indicating the
valid states and the unused states
b) Design a Mod-6 Asynchronous down counter using –ve edge triggered JK flip 06
flops . Draw the timing waveforms
c) Explain the four modes of working of 3-bit shift register using D-flip-flops 06
 UNIT-IV
5. a) For the clocked synchronous sequential network shown in the figure construct the 10
excitation table, transition table, state table and state diagram.

b) Design a serial adder with necessary state graph and timing diagram. 10
OR
6. a) For the state table as given in Table 6(b) obtain 10
(i) the reduced state table
(ii) design the sequential circuit for the state table obtained from step
Table 6(b)
Next State Output
Present State x=0 x=1 x=0 x=1
a f b 0 0

b d c 0 0

c f e 0 0

d g a 1 0

e d c 0 0

f f b 1 1

g g h 0 1

h g a 1 0
 b) Realize the system represented by the following state diagram using T flip-flops 10
assuming the state assignments: a = 00, b = 01, c = 10, d = 11

UNIT-V
7. a) Explain the following characteristics of digital ICs (i) Fan out (ii) Propagation 06
delay (iii) Noise Margin
b) With neat circuit diagram explain the working of three input TTL NAND gate 10
c) Give the performance comparison of TTL versus CMOS gates 04
*******