Digital Design

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 Field-Programmable Gate Array (FPGA)
. The FPGA configuration is generally specified using a hardware
description language(HDL).

. FPGAs have large resources of logic gates and RAM blocks to

implement complex digital computations.

. FPGAs contain programmable logic components called "logic

blocks", and a hierarchy of reconfigurable interconnects that
allow the blocks to be "wired together"

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FPGA Architecture

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 FPGA Applications
. Communications
. Radio , Digital Signal Processing (DSP)
. Image Processing
. Network Processing
. Motor Control

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 VHDL

VHDL is a hardware description language used in electronic

design automation to describe digital and mixed systems such
as FPGA and integrated circuit.

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 Advantages of VHDL
. It allows the behavior of the required system to be described
(modeled) and verified (simulated) before synthesis tools
translate the design into real hardware (gates and wires).

. It allows the description of a concurrent system.

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 File in VHDL
Any VHDL file needs to:
. Description of inputs and outputs.
. Relation between inputs and outputs.
. Architecture to define the function.

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 Types of direction and data
Types of direction:
1) In Input
It is available for reading only.
e.g. K<=A and B; True
A<=B; False

2) Out Output
It is available for writing only
e.g. Sum<= A xor B; True
K<= Sum; False

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 Continue
Data Types:
1) Bit : Value set is ('0', '1')
2) Bit_vector : Value set is array of bits.
e.g. A: bit_vector (3 downto 0); A(3) is MSB and A(0) is LSB
A: bit_vector (0 to 3); A(0) is MSB and A(3) is LSB

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 Continue
3) Std_logic: Value set is ('U','X','0','1','Z','W','L','H','-')
'U‘ -- Uninitialized
'X‘ -- Forcing unknown
'0‘ -- Forcing 0
'1‘ -- Forcing 1
'Z‘ -- High impedance
'W‘ -- Weak unknown
'L‘ -- Weak 0
'H‘ -- Weak 1
'-‘ -- Don't care

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4) Std_logic_vector : Value set is array std_logic
5) Other types as : integer , real, string, character and so on.

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 Examples
Combinational Circuit (Half Adder)
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
A S
use IEEE.std_logic_unsigned.all;
ENTITY half_adder IS --- Half Adder
PORT(a,b: IN std_logic; B Half adder C
s,c : OUT std_logic);
END half_adder;
ARCHITECTURE half_adder_beh OF half_adder IS
BEGIN
s <= a XOR b; -- Implements Sum for Half Adder
c <= a AND b; -- Implements Carry for Half Adder
END half_adder_beh;

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 Sequential Circuit (D Flip Flop)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; D Q
entity DFF1 is
Port ( D : in std_logic;
CLK : in std_logic; D FF
Q : out std_logic;
CLK QN
QN : out std_logic);
end DFF1;
architecture Behavioral of DFF1 is
begin
process (CLK) --- sensitivity list
begin
if (CLK’event and CLK = ‘1’ )then
Q <= D;
QN <= NOT D;
end if;
end process;
end Behavioral; 13