Viewing internal Signals using Chipscope:

Please go through the current FPGA set up for the SD Host Controller database for
easy understanding of this process.
• The two IP cores need to be generated to view internal RTL signals through
Chipscope. They are Integrated Controller Core (ICON) and Integrated Logic
Analyzer (ILA). Current, FPGA set up for SD Host Controller database has both
of them instantiated already.
• The ILA core is a customizable logic analyzer core that can be used to monitor
any internal signal of the RTL.
• The ICON core provides communication path between JTAG boundary Scan Port
of the target FPGA and the ILA core.
• Firstly, we need to choose the signals that we wish to debug and probe on
Chipscope from any internal module. We can then concatenate such signals into a
single debug port and declare it as output of that particular module. We can take
any number debug ports from a module and each debug port has a size of 32-bits.
We can use some or all of those 32-bits. There is a limit of 16 debug ports per
ILA Core.
• Such output debug ports should be connected through wires to the ILA Core in
the main module. They will be connected to Trigger ports of ILA Core (TRIG0,
TRIG1, TRIG2….etc) The triggering clock frequency of ILA Core clock ‘CLK’
should be high enough to sample the transitions of the signals.
• After dumping the bit/mcs file into FPGA, the debug signals can be probed
through Chipscope. The Data Port signals should be named appropriately in order
of the signal connection in the ILA CORE, with TRIG0 being least significant
word.
• Open Chipscope Analyzer and click the Open Cable/Search JTAG chain (tiny
image below File option) to detect the JTAG chain.
• The Data lines here used for Triggering. We can set the appropriate signal to 0 or
1 that we wish to trigger at using “Trigger Setup”. We can put the signal at X, for
a don’t care condition. We can have 4096 samples per trigger. We can set Trigger
 position to 2050, if we want the same amount of data before and after trigger
point. If we want to have more data before triggering point we can set trigger
position closer to 4096. If we want to have more data after triggering point we can
set trigger position closer to 0.
• We can have a combination of triggers. For example if we want to trigger a
condition where a signal goes to 0 in one module and another signal goes to 1 in
other module, we can set it through ‘and’ combination of triggers in trigger setup.
After setting up the combination of triggers, we can push the run button and wait
for the trigger. Once the trigger has been encountered, sampled signals will be
displayed in the waveform according to the triggered position.
• We can save the waveform in .vcd format by choosing File  Export….