CHAPTER-1

MULTILEVEL INVERTER

The multilevel inverter uses a series of power semiconductor switches with several lower
voltage dc sources to perform the power conversion by synthesizing a staircase voltage
waveform. Capacitors, batteries, and renewable energy voltage sources can be used as the
multiple dc voltage sources. Multilevel inverters generate the output voltages with very
low distortion, produce smaller common mode voltage, draw input current with low
distortion and can operate at both fundamental switching frequency and high switching
frequency PWM. Despite these advantages, the major disadvantage is that a multilevel
inverter uses more number of semiconductor switches. Lower voltage rated switches can
be utilized but each switch requires an appropriate gate drive circuit. This may cause the
overall system to be more expensive and complex.
The types of multilevel inverter is
 Diode Clamped multilevel inverter
 Flying Capacitor multilevel inverter
 Cascaded multilevel inverter
The flying capacitor inverter is difficult to realize because each capacitor must be
charged with different voltages as the voltage level increases. The diode clamped inverter
is difficult to expand to multilevel because of the natural problem of the DC link voltage
unbalancing. Though the cascaded multilevel inverter requires separate dc sources, it can
be expanded to multilevel easily and the problem of the dc link voltage unbalancing does
not occur.
Due to these advantages, the cascaded inverter has been widely applied to such
applications as HVDC, SVC, stabilizer, high power motor drive and so on. This topology
of inverter is suitable for high voltage and high power inversion because of its ability to
synthesize waveforms with better harmonic spectrum.
1.1 DIODE CLAMPED MULTILEVEL INVERTER
This converter is based on a modification of the classic two level converter
topology adding new power semiconductors per phase. The simplest NPC converter is
shown in Fig. 1.1(a), implementing three leg voltage levels by doubling the number
ofswitches and adding the same number of diodes to each additional switch. An additional

1
level is clamped through the diodes (clamping diodes) connected to so-called neutral point
of the source, as denoted in Fig. 1.1(a). Using this new topology, each power device has to
stand, at the most, half voltage compared with the two-level case with the same dc-link
voltage. Therefore, having the same power semiconductors ratings as the two-level case,
the output voltage can be doubled.
Note that for number of leg voltage levels nhigher than three there is no single
clamped point, (for even number of levels there is no neutral point at all). Based on the
parity of the n converters are divided in neutral point clamped (NPC) for an odd number,
and multi-point clamped, when n is even.
The principle of the switching is quite simple: for n-level inverter highest (n-1) adjacent
switches need to be turned on together to achieve maximum leg voltage, next (n-1)
switches to be turned on for (n-2)-th output level etc, up to the last (n-1) switches, which
turned on together give zero leg voltage. There are also limitations: turning on nadjacent
switches would lead to shoot-through. This can be illustrated on a three-level and four-
level examples (Fig. 1.1), which are also of the highest practical interest, with the
switching combinations given in Tab. 1.1. There are only three useful combinations for
three-level case, whereas the other lead to undefined states. Therefore, this multilevel
inverter has no redundant states (i.e. different switching combinations leading to the same
output voltage). Similar conclusion can be made from four level inverter switching states
(Tab. 1.1).

2
 (a)Three Level

(b)Four Level
Fig. 1.1 Diode clamped multilevel inverter
State of switches 3-level
Ta1 Ta2 Ta3 Ta4 Leg Voltage
1 1 0 0 Vdc
Value
0 1 1 0 0
0 0 1 1 -Vdc

State of switches 4-level

Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Leg Voltage
1 1 1 0 0 0 1.5Vdc
0 1 1 1 0 0 0.5Vdc
Value 0 0 1 1 1 0 -0.5Vdc
0 0 0 1 1 1 -1.5Vdc

Tab.1.1 Switching states and leg output voltages for three-level and four-level diode-
clamped inverters

However, four-level inverter has a serious drawback compared to three-level one:

additional diodes do not have equal reverse voltage. Indeed, when Ta5 and Ta6 are on,
diode Da2 has to withstand reverse voltage equal to 2Vdc, which is double of the
transistors rated voltage. Furthermore, for inverters with higher number of levels this

3
voltage further increases. In addition, switches are not directly clamped to the dc link
capacitors by the opposite freewheeling diodes, except for the outmost two, in contrast to
two-level inverter. In this way static or stray inductance overvoltage can appear across the
switches. These two are the biggest drawbacks of NPC inverters with higher number of
levels, because it practically turns back the problem to the initial series connection of
switches.
For these reasons, three-level inverter is the most popular within its class. In order
to solve these problems for higher number of levels a different diode-clamped topology has
been proposed. The structure provides a more direct clamping both diodes and switches to
the dc capacitors.
The main features of diode clamped inverter are:
 High voltage rating for blocking diodes
 Unequal switching device rating
 Capacitor voltage unbalance
The major advantages are:
 When the number of levels is high enough, the harmonic content is
low enough to avoid the need for filters
 Inverter efficiency is high because all devices are switched at the
fundamental frequency
 The control method is simple
The major disadvantages are:
 Excessive clamping diodes are required when the number of levels is
high
 It is difficult to control the real power flow of the individual converter in
multi converter systems
1.2 FLYING CAPACITOR MULTILEVEL INVERTER
The flying capacitor (FC) topology is in some way derived from it diode clamped
predecessor by the simplification – elimination of the clamping diodes. FC inverter uses
additional capacitors oppositely charged to be included in series with dc supply, since after
the elimination of the diodes it is not possible to connect leg output directly to the desired
dc voltage. These capacitors have the same function of the clamping diodes in diode-
clamped converter: they keep constant the voltage drop between the busses to which they
are connected. For this reason, they are called clamping capacitors, giving the name to the
converter. Another name that can be found in the literature is the nest cell converter. The
principle of the switching is similar to the DCI, and will be explained for three-level and

4
four-level examples shown in Fig. 1.2. However, there is adifference in the principle:
clamping capacitors need to be connected in series, and must not be short-circuited by
turning on switches connected in parallel.
The switching table is given in Tab. 1.2, showing redundancy for leg output voltage
equal to zero which is another difference with respect to DCI. These voltage-level
redundancies can be used as extra degrees of freedom for control or optimization purposes.
However, the main and most important difference with the NPC topology is that the FChas
a modular structure that can be more easily extended to achieve more voltage levels, for
this reason sometimes called multicell inverter.

(a)Three Level

5
 (b)Four Level
Fig. 1.2Flying capacitor inverter
The main drawback of the FCI is complex control algorithm and many voltage
sensors forhigh number of capacitor voltages to be controlled. Another problem is
capacitors flyingconnection that requires both initialization and control, which requires the
use of the redundant states. The hardware disadvantage is requirement for significant
number of capacitors.
Since the applications are at lower carrier frequencies the high values of capacitors
is the major disadvantage of the FCI. In addition, capacitors are unequally rated, as can be
noted in Fig. 1.2(b), where the outer capacitors need to withstand almost full dc voltage,
compared to DCI where all capacitors were equal and relatively small. In addition, the
drawback of unequal switch currents common with DCI remained. To conclude, the
youngest among the common multilevel configurations (proposed less than twenty years
ago), this converter remained in the shadow of the other two competitors.
The main features of flying capacitor inverter are:
 Large number of capacitors
 Balancing capacitor voltages

The major advantages are:

6
  Large amounts of storage capacitors can provide capabilities during
power outages
 These inverters provide switch combination redundancy for
balancing different voltage levels
 Like the diode clamped inverter with more levels, the harmonic
content is low enough to avoid the need for filters
 Both real and reactive power flow can be controlled
The major disadvantages are:
 An excessive number of storage capacitors is required when the
number of levels is high
 High level inverters are more difficult to package with the bulky
power capacitors and are more expensive too
 The inverter control can be very complicated, and the switching
frequency and the switching losses are high for real power
transmission

State of switches 3-level

Ta1 Ta2 Ta3 Ta4 Leg Voltage
1 1 0 0 Vdc
1 0 1 0 0
Value 0 1 0 1 0
0 0 1 1 -Vdc
0 1 1 0 Short-Circuit

Tab. 1.2 Switching states and leg output voltages for three-level flying capacitor inverter

1.3 CASCADED MULTILEVEL INVERTER

Figure.1.3 shows 3-level and 5-level cascaded H-bridge legs. As usual, the 3-level
converter analysis is the simplest and lets understand the operating principle of the
modules composing the leg of a generic n-level converter; these modules are often called
cells. It is well known that H-bridge converters can be modulated with 2-level or 3-level
output. In this kind of multilevel converter, all the possible cell output levels are exploited.
Some switches configurations are harmful for the converter and they must be avoided; for
instance, the switches T1 and T1′are not allowed to be turned on at the same time because
this situation causes a shortcut of the source.Table.3 shows the relationship between the
allowed switches configurations and theoutput of a 3-level cascaded inverter.
Switches State Output Voltage

7
 T1 T2 T1′ T2′ VAO

1 0 0 1 E

1 1 0 0 0

0 0 1 1 0

0 1 1 0 -E

Table.1.3Switching states and leg output voltages for three-level cascaded H-Bridge
inverter
It can be seen that even cascaded converter presents an intra-phase redundancy
because there are two different ways to obtain the level 0. Moreover, considering the same
DC source voltage, the output level amplitude and the switches reverse voltage drop are
greater here than in the diode-clamped or flying-capacitor.

(a)Three Level

8
 (b)Five Level
Figure.1.3cascaded H-bridge
In order to increase the number of levels more cells have to be cascaded. High and
low couple of switches can be defined in the respect of voltage output direction.
Considering the couple of switches composed by T1 and T1′is the high one, whereas T2 and
T2′constitute the low couple. The high output of one cell is shortcut to the low output of
another one to realize a cascade connection between two cells.

Switches State Output

Voltage
T11 T12 T21 T22 T11′ T12′ T21′ T22′ VAO
1 0 1 0 0 1 0 1 2E
1 1 1 0 0 0 0 1 E
1 0 0 0 0 1 1 1 E
1 0 1 1 0 1 0 0 E
0 0 1 0 1 1 0 1 E
1 1 1 1 0 0 0 0 0
1 1 0 0 0 0 1 1 0
1 0 0 1 0 1 1 0 0
0 1 1 0 1 0 0 1 0
0 0 1 1 1 1 0 0 0
0 0 0 0 1 1 1 1 0
0 1 1 1 1 0 0 0 -E
0 0 0 1 1 1 1 0 -E
0 1 0 0 1 0 1 1 -E
1 1 0 1 0 0 1 0 -E
0 1 0 1 1 0 1 0 -2E

9
Table.1.4Switching states and leg output voltages for five-level cascaded H-Bridge inverter
The cascade H-bridge was the founder of cascade converter family and the simplest
one. Each type of single-phase multilevel converter can be cascaded to obtain a leg. In this
way, the level each cell adds increase and is a good compromise between the required
insulated sources and the number of output levels.
The main features of cascaded inverter are:
 For real power conversions from ac to dc and then dc to ac, the
cascaded inverters need separate dc sources.
 The structure of separate dc sources is well suited for various
renewable energy sources such as fuel cell, photovoltaic, and
biomass
 Connecting dc sources between two converters in a back to back
fashion is not possible because a short circuit can be introduced
when two back to back converters are not switching synchronously
The major advantages are:
 Compared with the diode clamped and flying capacitors inverters,
it requires the least number of components to achieve the same
number of voltage levels
 Optimized circuit layout and packaging are possible because each
level has the same structure and there are no extra clamping
diodes or voltage balancing capacitors
 Soft switching techniques can be used to reduce switching losses
and device stresses
Inverter Diode-Clamp Flying-Capacitors Cascaded Inverters
Configuration Inverter Inverter
Main Switching 2(m-1) 2(m-1) 2(m-1)
Devices
Main 2(m-1) 2(m-1) 2(m-1)
Diodes
Clamping (m-1)(m-2) 0 0
Diodes
DC Bus (m-1) (m-1) (m-1)/2
Capacitors
Balancing 0 (m-1)(m-2)/2 0
Capacitors

10
 Table.1.5 Comparison of power component requirements per phase leg among three
multilevel Inverter

CHAPTER-2
LITERATURE SURVEY

G. Pandian and S. Rama Reddy “Implementation of Multilevel Inverter-Fed

Induction Motor Drive” Journal of Industrial Technology, Volume 24, Number 2 ,
June 2008.

This paper introduces a symmetrical multilevel inverter fed induction motor. This
method highly reduces harmonics present in the circuit and also produce a high torque

Karalapati Preethi, G.Anil, E.Vani, ”Speed Control of Induction Motor Using Eleven
Levels Multilevel Inverter”, International Journal of Science and Modern Engineering
(IJISME) , Volume-1, Issue-5, April 2013

In this paper diode clamped MLI are used to control the speed of Induction Motor.
Stator control method are used to control the speed. By this method harmonics was highly
reduced and motor torque was increased.

Johannes Kolb, Felix Kammerer, Mario Gommeringer, and Michael Braun,

“Cascaded Control System of the Modular Multilevel Converter for Feeding
Variable-Speed Drives”, IEEE Transactions On Power Electronics, VOL. 30, NO. 1,pp
349-357, JANUARY 2015

11
 The modular multilevel converter (MMC) is an up- coming topology for high-
power drive applications especially in the medium voltage range. This paper presents the
design process of a holistic control system for a MMC to feed variable-speed drives. By
this method minimize current stress and additional voltage pulsations.

Yuhei Okazaki, Makoto Hagiwara, and Hirofumi Akagi,” A Speed-Sensorless Start-

Up Method of an Induction Motor Driven by a Modular Multilevel Cascade Inverter”
(MMCI-DSCC) IEEE Transactions On Industry Applications, VOL. 50, NO. 4, pp
2671-2680, JULY/AUGUST 2014.

This paper presents theoretical and experimental discussions on a practical speed-

sensorless start-up method for an induction motor driven by a modular multilevel cascade
inverter based on double-star chopper cells (MMCI-DSCC) from stand- still to middle
speed. It reduces voltage fluctuation.

Obrad Dordevic, Martin Jones, and Emil Levi,A ,”Comparison of Carrier-Based and
Space Vector PWMTechniquesforThree-LevelFive-PhaseVoltage Source Inverters”,
IEEE Transactions On Industrial Informatics, VOL. 9, NO. 2,pp 609-618, MAY 2013.

This paper deals with a three-level neutral point clamped (NPC) inverter supplied
five-phase induction motor drive and analyses five PWM strate- gies: three are carrier-
based (CBPWM) and two are space vector based (SVPWM).The aim is to provide a
detailed comparison and thus conclude on pros and cons of each solution, providing a
guide- line for the selection of the most appropriate PWM technique

Ashwini N.Kadam,” Simulation And Implementation Of Multilevel Inverter Based

Induction Motor Drive Based On PWM Techniques”, International Journal of
Industrial Electronics and Electrical Engineering, ISSN: 2347-6982 Volume- 2, Issue-
1, Jan.-2014.

The main objective of this paper is to control the speed of an induction motor by
using three level diode clamped multilevel inverter. To obtain high quality sinusoidal
output voltage with reduced harmonics, multicarrier PWM control scheme is proposed for
diode clamped multilevel inverter

Ebrahim Babaei, Somayeh Alilu, Sara Laali ,“A New General Topology for Cascaded
Multilevel Inverters With Reduced Number of Components Based on Developed H-
12
Bridge”, IEEE Transactions On Industrial Electronics, VOL. 61, NO. 8, pp 3932-3939,
AUGUST 2014.

In this paper, a new general cascaded multilevel inverter using developed H-bridges
is proposed. The proposed topology requires a lesser number of dc voltage sources and
power switches and consists of lower blocking voltage on switches, which results in
decreased complexity and total cost of the inverter

Sumit K. Chattopadhyay, and Chandan Chakraborty,” A New Multilevel Inverter

Topology With Self-Balancing Level Doubling Network”, IEEE Transactions On
Industrial Electronics, VOL. 61, NO. 9, Pp 4622-4631, SEPTEMBER 2014

A new multilevel inverter (MLI) topology is proposed using a level doubling

network (LDN). The LDN takes the form of a half-bridge inverter to almost double the
number of output volt- age levels. The concept (of the proposed LDN) has the capability of
self-balancing during positive and negative cycles without any closed-loop
control/algorithm, and it does not consume or supply any power. It significantly improves
the power quality, reduces the switching frequency, and reduces the cost and size of the
power filter

Bahr Eldin S. Mohammed and K.S.RamaRao, “A New Multicarrier Based PWM For
Multilevel Converter”, IEEE applied power electronics colloquium (IAPEC)., 2011.
This paper introduced a multicarrier based pwm for modulation for multilevel
converter, which is used to reduce the total harmonic distortion and improve the power
quality. A various modulation techniques are used in this method.

Fang ZhengPeng, “A Generalized Multilevel Inverter Topology with Self Voltage

Balancing,”IEEE Trans.Ind.Appl.,Vol.37,no.2,March/April 2001.
This paper presents reduced number of switches for asymmetrical multilevel
inverter. The disadvantage is that the small voltage steps are typically produced by isolated
voltage source.

13
S.Mekhilaf and A.M.Omar, “Modeling of Three Phase Uniform Symmetrical
Sampling Digital PWM for Power Converter,”IEEETrans.Ind.Electron, Vol.54, no.1,
PP.427-432, Feb 2007.
This paper introduced a multilevel converter, which has reduced the number
of switches, harmonics and cost and improves the power quality and efficiency.

Mariusz Malinowski, K.GopaKumar, Jose Rodriguez and Marcelo A.Perez, “A

Survey on Cascaded Multilevel Inverters”,IEEE Trans. On Ind.Electrons, Vol.57,
no. 7, July 2010.
This paper developed a multicarrier pulse width modulation based cascaded
inverter, which works in minimum voltage to improve the harmonic performance of the
output voltage and efficiency.

S.Malathy, U.Shajith Ali, “Performance Analysis of Multi-Carriers PWM based

Cascaded Multilevel Inverter”, Vol.22, pp.32-40, 2012.
This paper developed introduced a cascaded multilevel inverter to achieve a high
quality output voltage. Here the numbers of voltage levels are increased and the power
electronic components are reduced. From this the lower harmonics are obtained.

Nho-Van, Nguyen, Bac-Xuan Nguyen and Hong-Hee Lee, “An Optimized

Discontinuous PWM Method to Minimize Switching Loss For Multilevel
Inverters”,copyright (c). IEEE 2009.
This paper proposed a discontinuous pulse width modulation method for multilevel
inverter to reduce the switching losses, harmonics and improves the efficiency.

J.Rodriguez, J.Lai and F.Peng, “Multilevel Inverter: A Survey of topologies, controls

and applications,”IEEETrans.onInd.Electronics, Vol.49, no.4, PP.724-738, 2002.
They introduced various topologies which controls of multilevel inverter.
The main advantages are lower harmonic components, lower switching losses and
improves power quality.

14
J.Rodriguez, S.Kouro, J.Rebolledo and J.Pontt, “A Reduced Switching Frequency
Modulation Algorithm for High Power Multilevel Inverter,”IEEETrans.Ind.Electron,
2005.
This paper developed an algorithm for high power multilevel inverter used in
frequency modulation. For high power application, there are many problems occur in
asymmetrical multilevel inverter. But it can produce lower harmonics for high switching
frequencies.

Rajesh Gupta, ArindamGhosh and Avinash Joshi, “Switching Characterization of

Cascaded Multilevel Inverter Controlled Systems,”IEEETrans.Ind.Electron, Vol.55,
no.3, March 2008.
This paper proposed the characteristics of controlled systems, which
results in the reduction of number of switches, harmonics, losses, installation area and
converter cost.

K.Surya Suresh and M.Vishnu Prasad, “Analysis and Simulation of New Seven Level
Inverter Topology”, Inter. Jou. Of Scientific and research publications, (ISSN 2250-
3153), Vol.2, Issue.4, April 2012.
This paper introduced a new topology for conventional H-bridge multilevel
inverter. It can generate a number of levels with less number of bidirectional switches.
Here they are proposed a seven level inverter which reduces the switching losses and cost.

15
 CHAPTER-3
PROPOSED TOPOLOGY

3.1 PROPOSED SOLUTION

 Newer Topology of MULTILEVEL inverter
 We have to reduce the total harmonic distortion as much as possible.
 By this we can :
 Increase the performance of drive.
 Increase the efficiency

Cascaded Hybrid New Hybrid

No of level 2S+1 2s+1-1 3s

S=No of Stages 7 level 15 level 27 level
S=3
Input DC Vdc 2s-1Vdc 3s-1Vdc
voltage 1Vdc 4Vdc 9Vdc

Tab.3.1 Comparison between Hybrid and New Hybrid Inverter

3.2 NEW HYBRID MULTILEVEL INVERTER

The proposed asymmetric multilevel inverter can be shown in the fig.3.3. Each phase
consists of three conversion cells and H-bridge. Each cell consists of V1, V2, and V3

16
voltages connected in cascaded form. This inverter consists of seven switches. Depending
upon the switching condition the positive and negative polarity output will be produced by
the H-bridge.
Expected output voltage level,
Vn=3s
Where,
s=number of stages

Figure.3.1 New Hybrid Multilevel Inverter

17
 Fig 3.2 Block diagram of Induction motor control

3.3 OPERATION
The new hybrid multilevel inverter consists of full bridge modules which have the
relationship of 1v, 3v, 9v…..3s-1v for dc link Voltage .The output waveform has 27 levels,
+ 13, + 12, + 11, + 10, + 9, + 8, + 7, + 6, + 5, + 4, + 3, + 2, + 1,0.
The inverter generates 3s different voltage levels (e.g. an inverter with s=3 cells can
generate 33=27 different voltage level).The basic hybrid multilevel inverter structure for
one phase is illustrated in Fig 3.2.This multilevel inverter is made up of a set of series
connected cells. Each cell consists of a 4-switch H-bridge voltage source inverter. The
output inverter voltage is obtained by summing the cell contributions. In conventional
method, low level inverter is used. Better sinusoidal output was not obtained which is the
drawback of the conventional system and the harmonics was high. So increase the levels of
the inverter to get high resolution, hence the output wave form is mostly sinusoidal wave
form. The cascaded multilevel inverter is prepared by series connection of single phase
full bridge inverter. The common function of multilevel inverter is to synthesize a desired
voltage from several separate DC sources. Each source is connected to a single phase full

18
bridge inverter. Each inverter is capable of generating three different output voltages,
+Vdc, 0 and - Vdc.

CHAPTER-4
MOULATION TECHNIQUES

4.1 ADVANCED PULSE WIDTH MODULATION TECHNIQUE

This scheme consist of following unipolar PWM techniques
Trapezoidal modulation Technique
Triangular Modulation Technique
Stepped Modulation Technique

4.2 PWM CONTROL STRATEGIES:

This scheme consists of three unipolar PWM strategies. The multicarrier is
positioned above zero level and the carriers are depending upon the output voltage levels.
For m level inverter, (m-1)/2 carriers are used.
The three unipolar PWM strategies are
 PD(Phase Disposition)

19
  APOD(Alternative Phase Opposition Disposition)
 CO(Carrier Overlapping)
 VF (Variable Frequency)
 VA( Variable Amplitude)
The advantages of this scheme is
 Reduces the harmonics
 Efficiency is high
 Increase the drive performance

4.3 SINUSOIDAL MODULATION TECHNIQUE:

4.3.1 UNIPOLAR PHASE DISPOSITION PWM STRATEGY:
This strategy uses (m-1)/2 triangular carriers with the same frequency fc and same peak-
to-peak amplitude Ac which are disposed so that the bands they occupy are contiguous. The
carrier set is placed above the zero reference. Two modulation waveforms having
amplitude Am and frequency fm. and it is centred about the zero level and are used to
sample the triangular carriers to generate the gating pulses. The carrier arrangement for
fifteen level inverter using UPDPWM is shown in Fig.4.1

Amplitude of modulation index can be given by

ma=Am/Ac

Frequency ratio is

mf=fc/fm

Where,
fc= frequency of carrier signal
fm=frequency of reference signal
Am=amplitude of reference signal
Ac=amplitude of carrier signal

20
 Figure.4.1 Carrier arrangement for UPDPWM strategy(ma=1 and mf=50)

4.3.2 UNIPOLAR ALTERNATIVE PHASE OPPOSITION DISPOSITION PWM

STRATEGY:
For m-level inverter, the carriers are arranged in 180 degree out of phase. The carrier
arrangement for fifteen level inverter using UAPODPWM is shown in Fig.4.2
Amplitude of modulation index can be given by
ma=Am/Ac

Frequency ratio is
mf=fc/fm
Where,
fc= frequency of carrier signal
fm=frequency of reference signal
Am=amplitude of reference signal
Ac=amplitude of carrier signal

21
 Figure.4.2 Carrier arrangement for UAPODPWM strategy(ma=1 and mf=50)

4.3.3 UNIPOLAR CARRIER OVERLAPPING PWM STRATEGY:

The UCOPWM uses thirteen carrier signals of peak-to-peak amplitude A c and they
overlap with each other. The gate signals for this strategy are derived by comparing the two
overlapping carriers with seven references. Fig.4.3 shows the carrier arrangement for the
chosen MLI with UCOPWM strategy.
Amplitude of modulation index can be given by

ma=Am/4Ac

Frequency ratio is

mf=fc/fm

Where,
fc= frequency of carrier signal
fm=frequency of reference signal
Am=amplitude of reference signal
Ac=amplitude of carrier signal

Figure.4.3 Carrier arrangement for UCOPWM strategy(ma=1 and mf=50)

4.3.4 UNIPOLAR VARIABLE FREQUENCY PWM STRATGY:

Figure 4.4 shows the carrier arrangement of UVFPWM stratgy. In Variable
Frequency method adjucent carrier having different frequency and same amplitude.

22
 Figure 4.4 Carrier arrangement of UVFPWM stratgy(m a=1 and mf=50)

4.3.5 UNIPOLAR VARIABLE AMPLITUDE PWM STRATGY:

Figure 4.5 shows the carrier arrangement of UVAPWM technique. In variable
amplitude method adjusent carrier having different amplitude and same frequency.

Figure 4.5 Carrier arrangement of UVAPWM stratgy(m a=1 and mf=50)

4.4 TRIANGULAR MODULATION TECHNIQUE

In this modulation techinque both reference and carrier having same triangular
signal. Various carrier arrangement of this technique was shown below.

4.4.1 UNIPOLAR PHASE DISPOSITION PWM STRATEGY

23
 In this techinque all carrier was arranged in phase with another carrier and having
same frequency.

Figure.4.6 Carrier arrangement for UPDPWM strategy(ma=1 and mf=50)

4.4.2 UNIPOLAR ALTERNATIVE PHASE OPPOSITION DISPOSITION PWM

STRATEGY
In this techinque all carrier was arranged in180 degree out of phase with another
carrier and having same frequency.

Figure.4.7 Carrier arrangement for UAPODPWM strategy(ma=1 and mf=50)

4.3.3 UNIPOLAR CARRIER OVERLAPPING PWM STRATGY

In this technique all carrier was over lapped with another carrier and having same
frequency.

24
 Figure.4.8 Carrier arrangement for UCOPWM strategy(ma=1 and mf=50)

4.4.4 UNIPOLAR VARIABLE FREQUENCY PWM STRATGY

Figure 4.9 shows the carrier arrangement of UVFPWM stratgy. In Variable
Frequency method adjucent carrier having different frequency and same amplitude.

Figure 4.9 Carrier arrangement of UVFPWM stratgy(m a=1 and mf=50)

4.3.5 UNIPOLAR VARIABLE AMPLITUDE PWM STRATGY

Figure 4.10 shows the carrier arrangement of UVAPWM technique. In variable
amplitude method adjusent carrier having different amplitude and same frequency.

25
 Figure 4.10 Carrier arrangement of UVAPWM stratgy(m a=1 and mf=50)

4.5 STEPPED MODULATION TECHNIQUE

In this modulation techinque stepped sine is used as reference signal and triangular
wavw is used as carrier signal. Various carrier arrangement of this technique was shown
below.

4.5.1 UNIPOLAR PHASE DISPOSITION PWM STRATEGY:

In this techinque all carrier was arranged in phase with another carrier and having
same frequency.

Figure.4.11 Carrier arrangement for UPDPWM strategy(ma=1 and mf=50)

26
4.5.2 UNIPOLAR ALTERNATIVE PHASE OPPOSITION DISPOSITION PWM
STRATEGY
In this techinque all carrier was arranged in180 degree out of phase with another
carrier and having same frequency.

Figure.4.12 Carrier arrangement for UAPODPWM strategy(ma=1 and mf=50)

4.5.3 UNIPOLAR CARRIER OVERLAPPING PWM STRATGY:

In this technique all carrier was over lapped with another carrier and having same
frequency.

Figure.4.13 Carrier arrangement for UCOPWM strategy(ma=1 and mf=50)

4.5.4 UNIPOLAR VARIABLE FREQUENCY PWM STRATGY:

Figure 4.14 shows the carrier arrangement of UVFPWM stratgy. In Variable
Frequency method adjucent carrier having different frequency and same amplitude.

27
 Figure 4.14 Carrier arrangement of UVFPWM stratgy(m a=1 and mf=50)

4.5.5 UNIPOLAR VARIABLE AMPLITUDE PWM STRATGY

Figure 4.15 shows the carrier arrangement of UVAPWM technique. In variable
amplitude method adjusent carrier having different amplitude and same frequency.

Figure 4.15 Carrier arrangement of UVAPWM stratgy(m a=1 and mf=50)

28
 CHAPTER-5
SIMULATION RESULTS
5.1 SIMULATION CIRCUIT

29
 Continuous

powergui [s3] -T-

[s1] [s13] -T-

C
[s25]

C
E
g
C

E
g

g
C

C
E

E
[s1] [s13]
-T-
[s2] [s4] [s2] [s14] [s16] [s14]
-T- [s26]
[s28]
g

g
C

g
C

C
Bridge 1 -T-
E

-T-
E

g
C

C
Bridge 1
Bridge 1 -T-

E
[s4] -T-
Bridge 2 -T- Vabc
[s5] A
-T- [s7] Bridge 2 [s17]
[s17] -T- Bridge 2
g

-T- [s29]
g

-T- -T-
g

Iabc
C

[s18]
E

C
Bridge 3
E

-T-
E

-T-
g
C

Bridge 3 [s19]
E
E

Bridge 3 -T-
g

Ba
C

MC PWM
E

[s8] -T-
MC PWM1
[s8] [s18] MC PWM2 -T-
[s6] [s20]
-T- b
-T- [s32]
-T-
-T-
g

C
g

C
C

C
E

c
E

-T-
g

-T-
g

C
E

-T-
Three-Phase
[s11] [s23] V-I Measurement
[s35]
-T- [s9] [s11]
-T- [s21] [s23]
g

C
g

-T- [s33] [s35]

g

g
C

C
E

g
C

C
E

E
E

E
E

[s10]
[s12] [s24]
g
C

[s36]
g

-T-
g

g
C
E

C
E

-T-
E

g
C

E
E

Fig.5.1 Simulink model of proposed multilevel inverter

5.2 SIMULATION OUTPUT FOR TRAPEZOIDAL MODULATION:

30
 Figure.5.2 Output voltage generated by USPDPWM strategy

Figure.5.3 FFT- harmonic spectrum of output of UPDPWM strategy

Figure.5.4 Output voltage generated by UAPODPWM strategy

31
Figure.5.5 FFT- harmonic spectrum of output of UAPODPWM strategy

Figure.5.6 Output voltage generated by UCOPWM strategy

Figure.5.7 FFT- harmonic spectrum of output of UCOPWM strategy

32
Figure 5.8 Output voltage generated by UVFPWM strategy

Figure.5.9 FFT- harmonic spectrum of output of UVFPWM strategy

Figure 5.10 Output voltage generated by UVFPWM strategy

33
Figure.5.11 FFT- harmonic spectrum of output of UVAPWM strategy

Figure 5.12 Motor Speed in RPM

34
 Figure 5.13 Motor Torque

ma Pd APOD CO VA VF
1 6.03 6.00 7.96 6.53 6.02
0.95 6.96 6.90 8.59 7.78 6.91

Table 5.1 %THD for different modulation indices

ma PD APOD CO VA VF
1 310.7 319.7 312.5 309 310.6
0.95 295.4 295.3 301.3 291.9 295.3

Table 5.2 Vrms(fundamental) for different modulation indices

ma PD APOD CO VA VF
1 3767.887 3016.504 3856.596 3285.137 3639.132
0.95 3525.059 3033.696 4281.654 3766.937 2833.973

Table 5.3 Form Factor for different modulation indices

35
 ma PD APOD CO VA VF
1 1.41422 1.4139 1.41423 1.41436 1.41436
0.95 1.41401 1.41415 1.41452 1.41449 1.41449

Table 5.4 Crest Factor for different modulation indices

5.3 SIMULATION OUTPUT FOR TRIANGULAR MODULATION:

Figure.5.14 Output voltage generated by UPDPWM strategy

36
Figure.5.15 FFT- harmonic spectrum of output of UPDPWM strategy

Figure.5.16 Output voltage generated by UAPODPWM strategy

Figure.5.17 FFT- harmonic spectrum of output of UAPODPWM strategy

37
 Figure.5.18 Output voltage generated by UCOPWM strategy

Figure.5.19 FFT- harmonic spectrum of output of UCOPWM strategy

Figure 5.20 Output voltage generated by UVFPWM strategy

38
Figure.5.21 FFT- harmonic spectrum of output of UVFPWM strategy

Figure 5.22 Output voltage generated by UVFPWM strategy

Figure.5.23 FFT- harmonic spectrum of output of UVAPWM strategy

39
 Figure 5.24 Motor Speed in RPM

Figure 5.25 Motor Torque

ma PD APOD CO VA VF

1 15.34 14.42 17.17 15.38 14.36

0.95 14.39 14.20 17.51 15.10 14.08

Table 5.5 %THD for different modulation indices

ma PD APOD CO VA VF

1 232.9 236.1 239.4 232.6 236.2

0.95 223.1 225.8 232.3 222 225.6

40
 Table 5.6 Vrms(fundamental) for different modulation indices

ma PD APOD CO VA VF

1 43.69 94.74 95.15 96.31 95.62

0.95 45.11 93.77 85.90 91.62 92.26

Table 5.7 Form Factor for different modulation indices

ma PD APOD CO VA VF

1 1.4139 1.4123 1.4139 1.4144 1.4140

0.95 1.4142 1.4141 1.4145 1.4144 1.4130

Table 5.8 Crest Factor for different modulation indices

5.4 SIMULATION OUTPUT FOR STEPPED MODULATION:

Figure.5.26 Output voltage generated by UPDPWM strategy

41
 Figure.5.27 FFT- harmonic spectrum of output of UPDPWM strategy

Figure.5.28 Output voltage generated by UAPODPWM strategy

Figure.5.29 FFT- harmonic spectrum of output of USAPODPWM strategy

42
 Figure.5.30 Output voltage generated by UCOPWM strategy

Figure.5.31 FFT- harmonic spectrum of output of UCOPWM strategy

Figure 5.32 Output voltage generated by UVFPWM strategy

43
Figure.5.33 FFT- harmonic spectrum of output of UVFPWM strategy

Figure 5.34 Output voltage generated by UVFPWM strategy

Figure.5.35 FFT- harmonic spectrum of output of UVAPWM strategy

44
 Figure 5.36 Motor Speed in RPM

Figure 5.37 Motor Torque

ma PD APOD CO VA VF

1 4.73 4.79 6.78 5.42 4.95

0.95 4.39 4.20 7.51 5.10 5.08

Table 5.9 %THD for different modulation indices

ma PD APOD CO VA VF

1 232.9 236.1 239.4 232.6 236.2

0.95 223.1 225.8 232.3 222 225.6

45
 Table 5.10 Vrms(fundamental) for different modulation indices

ma PD APOD CO VA VF

1 43.69 94.74 95.15 96.31 95.62

0.95 45.11 93.77 85.90 91.62 92.26

Table 5.1 Form Factor for different modulation indices

ma PD APOD CO VA VF

1 1.4139 1.4123 1.4139 1.4144 1.4140

0.95 1.4142 1.4141 1.4145 1.4144 1.4130

Table 5.12 Crest Factor for different modulation indices

The Three phase Twenty seven level inverter is modelled in SIMULINK using power
system block set. Switching signals for three phase multilevel inverter using Advanced
PWM techniques are simulated. Simulations are performed for different values of ma
ranging from 0.95 to 1 and the corresponding %THD are measured using the FFT block
and their values are shown in Table. Figure5.2 to5.11 show the simulated output voltage
of three phase MLI and their corresponding FFT plot for trapezoidal modulation technique.
Figure5.14 to5.25 show the simulated output voltage of Three phase MLI and their
corresponding FFT plot for triangular modulation technique.. Figure5.28 to5.35 show the
simulated output voltage of three phase MLI and their corresponding FFT plot for stepped
modulation technique.

46
 CHAPTER 6
CONCLUSION
In this project, a New Hybrid multilevel inverter have been developed using
MATLAB/SIMULINK. A proposed asymmetric multilevel inverter gives higher output
voltage level. The Performance parameters like %THD, V rms, CF and FF have been
analysed and presented. From that the UPD technique provides lower %THD and V rms is
higher in UCO. From a high voltage level with low distortion performance of induction
motor was increased.

47
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