Sei sulla pagina 1di 45

HT46R46/HT46C46/HT46R47/HT46C47

Cost-Effective A/D Type 8-Bit MCU

Technical Document
· Tools Information
· FAQs
· Application Note
- HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM
- HA0049E Read and Write Control of the HT1380
- HA0051E Li Battery Charger Demo Board - Using the HT46R47
- HA0052E Microcontroller Application - Battery Charger
- HA0083E Li Battery Charger Demo Board - Using the HT46R46

Features
· Operating voltage: · Up to 0.5ms instruction cycle with 8MHz system clock
fSYS=4MHz: 2.2V~5.5V at VDD=5V
fSYS=8MHz: 3.3V~5.5V · 4-level subroutine nesting for HT46R46/HT46C46
· 13 bidirectional I/O lines (max.) · 6-level subroutine nesting for HT46R47/HT46C47
· 1 interrupt input shared with an I/O line · 4 channels 8-bit resolution A/D converter
· 8-bit programmable timer/event counter with overflow for HT46R46/HT46C46
interrupt and 7-stage prescaler · 4 channels 9-bit resolution A/D converter
· On-chip crystal and RC oscillator for HT46R47/HT46C47
· Watchdog Timer · 1 channel 8-bit PWM output shared with an I/O line
· 1024´14 program memory for HT46R46/HT46C46 · Bit manipulation instruction
· 2048´14 program memory for HT46R47/HT46C47 · 14-bit table read instruction
· 64´8 data memory RAM · 63 powerful instructions
· Supports PFD for sound generation · All instructions in one or two machine cycles
· HALT function and wake-up feature reduce power · Low voltage reset function
consumption · 18-pin DIP/SOP, 20-pin SSOP packages

General Description
The HT46R46/HT46C46 and HT46R47/HT46C47 are The advantages of low power consumption, I/O flexibil-
8 -b it , h i gh p e r f or m a n c e, R I S C a r c h i t e ct u r e ity, programmable frequency divider, timer functions,
microcontroller devices specifically designed for A/D oscillator options, multi-channel A/D Converter, Pulse
applications that interface directly to analog signals, Width Modulation function, HALT and wake-up func-
such as those from sensors. The mask version tions, enhance the versatility of these devices to suit a
HT46C46, HT46C47 are fully pin and functionally com- wide range of A/D application possibilities such as sen-
patible with the OTP version HT46R46, HT46R47 de- sor signal processing, motor driving, industrial control,
vice. consumer products, subsystem controllers, etc.

Rev. 1.30 1 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

Block Diagram
P A 5 /IN T

In te rru p t
C ir c u it
M P r e s c a le r fS Y S
S T A C K T M R C
U
P ro g ra m P ro g ra m IN T C X P A 4 /T M R
T M R
R O M C o u n te r

P A 3 /P F D P A 4

M fS Y S /4
In s tr u c tio n W D T U
R e g is te r M P M D A T A W D T O S C
X
U M e m o ry
X
P W M

P D C P o rt D
P D 0 /P W M
P D
In s tr u c tio n M U X
D e c o d e r 4 -C h a n n e l
A /D C o n v e rte r
A L U S T A T U S
P B C P o rt B
P B 0 /A N 0 ~ P B 3 /A N 3
T im in g S h ifte r
P B
G e n e ra to r
P A 3 , P A 5
P A 0 ~ P A 2
P A C P o rt A P A 3 /P F D
P A 4 /T M R
O S C 2 O S C 1 A C C L V R P A P A 5 /IN T
R E S P A 6 ~ P A 7
V D D
V S S

Rev. 1.30 2 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

Pin Assignment

P A 3 /P F D 1 2 0 P A 4 /T M R
P A 3 /P F D 1 1 8 P A 4 /T M R P A 2 2 1 9 P A 5 /IN T
P A 2 2 1 7 P A 5 /IN T P A 1 3 1 8 P A 6
P A 1 3 1 6 P A 6 P A 0 4 1 7 P A 7
P A 0 4 1 5 P A 7 P B 3 /A N 3 5 1 6 O S C 2
P B 3 /A N 3 5 1 4 O S C 2 N C 6 1 5 O S C 1
P B 2 /A N 2 6 1 3 O S C 1 P B 2 /A N 2 7 1 4 V D D
P B 1 /A N 1 7 1 2 V D D P B 1 /A N 1 8 1 3 R E S
P B 0 /A N 0 8 1 1 R E S P B 0 /A N 0 9 1 2 P D 0 /P W M
V S S 9 1 0 P D 0 /P W M V S S 1 0 1 1 N C

H T 4 6 R 4 6 /H T 4 6 C 4 6 H T 4 6 R 4 6 /H T 4 6 C 4 6
H T 4 6 R 4 7 /H T 4 6 C 4 7 H T 4 6 R 4 7 /H T 4 6 C 4 7
1 8 D IP -A /S O P -A 2 0 S S O P -A

Pin Description
Pin Name I/O Options Description
PA0~PA2 Bidirectional 8-bit input/output port. Each bit can be configured as wake-up
PA3/PFD Pull-high input by options. Software instructions determine the CMOS output or Schmitt
PA4/TMR I/O Wake-up trigger input with or without pull-high resistor (determined by pull-high options: bit
PA5/INT PA3 or PFD option). The PFD, TMR and INT are pin-shared with PA3, PA4 and PA5, re-
PA6, PA7 spectively.
Bidirectional 4-bit input/output port. Software instructions determine the
PB0/AN0
CMOS output, Schmitt trigger input with or without pull-high resistor (deter-
PB1/AN1
I/O Pull-high mined by pull-high options: bit option) or A/D input.
PB2/AN2
Once a PB line is selected as an A/D input (by using software control), the I/O
PB3/AN3
function and pull-high resistor are disabled automatically.
Bidirectional I/O line. Software instructions determine the CMOS output,
Pull-high Schmitt trigger input with or without a pull-high resistor (determined by
PD0/PWM I/O
PD0 or PWM pull-high options: bit option). The PWM output function is pin-shared with
PD0 (dependent on PWM options).
RES I ¾ Schmitt trigger reset input. Active low.

VDD ¾ ¾ Positive power supply

VSS ¾ ¾ Negative power supply, ground.


OSC1, OSC2 are connected to an RC network or a Crystal (determined by
OSC1 I Crystal
options) for the internal system clock. In the case of RC operation, OSC2 is
OSC2 O or RC
the output terminal for 1/4 system clock.

Absolute Maximum Ratings


Supply Voltage ...........................VSS-0.3V to VSS+6.0V Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V Operating Temperature...........................-40°C to 85°C

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.

Rev. 1.30 3 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

D.C. Characteristics Ta=25°C

Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions

¾ fSYS=4MHz 2.2 ¾ 5.5 V


VDD Operating Voltage
¾ fSYS=8MHz 3.3 ¾ 5.5 V

Operating Current 3V No load, fSYS=4MHz ¾ 0.6 1.5 mA


IDD1
(Crystal OSC) 5V ADC disable ¾ 2 4 mA

Operating Current 3V No load, fSYS=4MHz ¾ 0.8 1.5 mA


IDD2
(RC OSC) 5V ADC disable ¾ 2.5 4 mA
Operating Current No load, fSYS=8MHz
IDD3 5V ¾ 4 8 mA
(Crystal OSC, RC OSC) ADC disable

Standby Current 3V No load, ¾ ¾ 5 mA


ISTB1
(WDT Enabled) 5V system HALT ¾ ¾ 10 mA

Standby Current 3V No load, ¾ ¾ 1 mA


ISTB2
(WDT Disabled) 5V system HALT ¾ ¾ 2 mA
Input Low Voltage for I/O Ports,
VIL1 ¾ ¾ 0 ¾ 0.3VDD V
TMR and INT
Input High Voltage for I/O Ports,
VIH1 ¾ ¾ 0.7VDD ¾ VDD V
TMR and INT
VIL2 Input Low Voltage (RES) ¾ ¾ 0 ¾ 0.4VDD V
VIH2 Input High Voltage (RES) ¾ ¾ 0.9VDD ¾ VDD V
VLVR Low Voltage Reset ¾ ¾ 2.7 3 3.3 V

3V VOL=0.1VDD 4 8 ¾ mA
IOL I/O Port Sink Current
5V VOL=0.1VDD 10 20 ¾ mA

3V VOH=0.9VDD -2 -4 ¾ mA
IOH I/O Port Source Current
5V VOH=0.9VDD -5 -10 ¾ mA

3V ¾ 20 60 100 kW
RPH Pull-high Resistance
5V ¾ 10 30 50 kW
VAD A/D Input Voltage ¾ ¾ 0 ¾ VDD V
EAD A/D Conversion Error ¾ ¾ ¾ ±0.5 ±1 LSB

Additional Power Consumption 3V ¾ 0.5 1 mA


IADC ¾
if A/D Converter is Used 5V ¾ 1.5 3 mA

Rev. 1.30 4 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

A.C. Characteristics Ta=25°C

Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions

¾ 2.2V~5.5V 400 ¾ 4000 kHz


fSYS System Clock
¾ 3.3V~5.5V 400 ¾ 8000 kHz

Timer I/P Frequency ¾ 2.2V~5.5V 0 ¾ 4000 kHz


fTIMER
(TMR) ¾ 3.3V~5.5V 0 ¾ 8000 kHz

3V ¾ 45 90 180 ms
tWDTOSC Watchdog Oscillator Period
5V ¾ 32 65 130 ms
Watchdog Time-out Period
tWDT1 ¾ ¾ 215 ¾ 216 tWDTOSC
(RC)
Watchdog Time-out Period
tWDT2 ¾ ¾ 217 ¾ 218 tSYS
(System Clock)
tRES External Reset Low Pulse Width ¾ ¾ 1 ¾ ¾ ms
tSST System Start-up Timer Period ¾ Wake-up from HALT ¾ 1024 ¾ *tSYS

tINT Interrupt Pulse Width ¾ ¾ 1 ¾ ¾ ms


A/D Clock Period
tAD1 ¾ ¾ 0.5 ¾ ¾ ms
for HT46R46/HT46C46
A/D Clock Period
tAD2 ¾ ¾ 1 ¾ ¾ ms
for HT46R47/HT46C47
A/D Conversion Time
tADC1 ¾ ¾ ¾ 64 ¾ tAD1
for HT46R46/HT46C46
A/D Conversion Time
tADC2 ¾ ¾ ¾ 76 ¾ tAD2
for HT46R47/HT46C47
A/D Sampling Time
tADCS1 ¾ ¾ ¾ 32 ¾ tAD1
for HT46R46/HT46C46
A/D Sampling Time
tADCS2 ¾ ¾ ¾ 32 ¾ tAD2
for HT46R47/HT46C47

Note: *tSYS=1/fSYS

Rev. 1.30 5 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

Functional Description
Execution Flow incremented by one. The program counter then points to
the memory word containing the next instruction code.
The system clock for the microcontroller is derived from
either a crystal or an RC oscillator. The system clock is When executing a jump instruction, conditional skip ex-
internally divided into four non-overlapping clocks. One ecution, loading PCL register, subroutine call, initial re-
instruction cycle consists of four system clock cycles. set, internal interrupt, external interrupt or return from
subroutine, the PC manipulates the program transfer by
Instruction fetching and execution are pipelined in such
loading the address corresponding to each instruction.
a way that a fetch takes an instruction cycle while de-
coding and execution takes the next instruction cycle. The conditional skip is activated by instructions. Once
However, the pipelining scheme causes each instruc- the condition is met, the next instruction, fetched during
tion to effectively execute in a cycle. If an instruction the current instruction execution, is discarded and a
changes the program counter, two cycles are required to dummy cycle replaces it to get the proper instruction.
complete the instruction. Otherwise proceed with the next instruction.
The lower byte of the program counter (PCL) is a read-
Program Counter - PC
able and writeable register (06H). Moving data into the
The program counter (PC) controls the sequence in PCL performs a short jump. The destination will be
which the instructions stored in program ROM are exe- within 256 locations.
cuted and its contents specify full range of program
When a control transfer takes place, an additional
memory.
dummy cycle is required.
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are

T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4
S y s te m C lo c k

O S C 2 (R C o n ly )

P C P C P C + 1 P C + 2

F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 ) F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C ) F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )

Execution Flow

Program Counter
Mode
*10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0
Initial Reset 0 0 0 0 0 0 0 0 0 0 0
External Interrupt 0 0 0 0 0 0 0 0 1 0 0
Timer/Event Counter Overflow 0 0 0 0 0 0 0 1 0 0 0
A/D Converter Interrupt 0 0 0 0 0 0 0 1 1 0 0
Skip Program Counter+2
Loading PCL *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0
Jump, Call Branch #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0
Return from Subroutine S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

Program Counter

Note: *10~*0: Program counter bits S10~S0: Stack register bits


#10~#0: Instruction code bits @7~@0: PCL bits
For the HT46R47/HT46C47, the Program Counter is 11 bits wide, i.e. from *10~*0.
For the HT46R46/HT46C46, the Program Counter is 10 bits wide, the *10 the column in the table is not
applicable.

Rev. 1.30 6 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

Program Memory - ROM TBLP. The TBLH is read only and cannot be restored.
If the main routine and the ISR (Interrupt Service Rou-
The program memory is used to store the program in-
tine) both employ the table read instruction, the con-
structions which are to be executed. It also contains tents of the TBLH in the main routine are likely to be
data, table, and interrupt entries, and is organized into
1K´14 bits for the HT46R46/HT46C46 or 2K´14 bits for 0 0 0 H
D e v ic e In itia liz a tio n P r o g r a m
the HT46R47/HT46C47, addressed by the program
counter and table pointer. 0 0 4 H
E x te r n a l In te r r u p t S u b r o u tin e
Certain locations in the program memory are reserved 0 0 8 H
for special usage: T im e r /E v e n t C o u n te r In te r r u p t S u b r o u tin e

· Location 000H 0 0 C H
A /D C o n v e r te r In te r r u p t S u b r o u tin e
This area is reserved for program initialization. After
P ro g ra m
chip reset, the program always begins execution at lo- M e m o ry
cation 000H.
n 0 0 H
· Location 004H L o o k - u p T a b le ( 2 5 6 w o r d s )
n F F H
This area is reserved for the external interrupt service
program. If the INT input pin is activated, the interrupt
is enabled and the stack is not full, the program begins
execution at location 004H.
3 0 0 H
L o o k - u p T a b le ( 2 5 6 w o r d s )
· Location 008H 3 F F H
This area is reserved for the timer/event counter inter- 1 4 b its
rupt service program. If a timer interrupt results from a N o te : n ra n g e s fro m 0 to 3
timer/event counter overflow, and if the interrupt is en-
abled and the stack is not full, the program begins exe- Program Memory for the HT46R46/HT46C46
cution at location 008H.
· Location 00CH 0 0 0 H
D e v ic e In itia liz a tio n P r o g r a m
This area is reserved for the A/D converter interrupt
service program. If an A/D converter interrupt results 0 0 4 H
E x te r n a l In te r r u p t S u b r o u tin e
from an end of A/D conversion, and if the interrupt is
enabled and the stack is not full, the program begins 0 0 8 H
execution at location 00CH. T im e r /E v e n t C o u n te r In te r r u p t S u b r o u tin e
0 0 C H
· Table location A /D C o n v e r te r In te r r u p t S u b r o u tin e
Any location in the ROM space can be used as P ro g ra m
look-up tables. The instructions ²TABRDC [m]² (the M e m o ry
current page, 1 page=256 words) and ²TABRDL [m]² n 0 0 H
(the last page) transfer the contents of the lower-order L o o k - u p T a b le ( 2 5 6 w o r d s )
byte to the specified data memory, and the n F F H
higher-order byte to TBLH (08H). Only the destination
of the lower-order byte in the table is well-defined, the
other bits of the table word are transferred to the lower
7 0 0 H
portion of TBLH, and the remaining 2 bits are read as L o o k - u p T a b le ( 2 5 6 w o r d s )
7 F F H
²0². The Table Higher-order byte register (TBLH) is
1 4 b its
read only. The table pointer (TBLP) is a read/write reg-
N o te : n ra n g e s fro m 0 to 7
ister (07H), which indicates the table location. Before
accessing the table, the location must be placed in Program Memory for the HT46R47/HT46C47

Table Location
Instruction
*10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0
TABRDC [m] P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0
TABRDL [m] 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0

Table Location

Note: *10~*0: Table location bits P10~P8: Current program counter bits
@7~@0: Table pointer bits
For the HT46R47/HT46C47, the Table address location is 11 bits, i.e. from *10~*0.
For the HT46R46/HT46C46, the Table address location is 10 bits, i.e. from *9~*0.

Rev. 1.30 7 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

changed by the table read instruction used in the ISR. 0 0 H In d ir e c t A d d r e s s in g R e g is te r


Errors can occur. In other words, using the table read 0 1 H M P
instruction in the main routine and the ISR simulta- 0 2 H
neously should be avoided. However, if the table read 0 3 H
instruction has to be applied in both the main routine 0 4 H
and the ISR, the interrupt is supposed to be disabled 0 5 H A C C
prior to the table read instruction. It will not be enabled 0 6 H P C L

until the TBLH has been backed up. All table related 0 7 H T B L P
0 8 H T B L H
instructions require two cycles to complete the opera-
tion. These areas may function as normal program 0 9 H
0 A H S T A T U S
memory depending upon the requirements.
0 B H IN T C
0 C H
Stack Register - STACK
0 D H T M R
This is a special part of the memory which is used to 0 E H T M R C
save the contents of the program counter only. The 0 F H
1 0 H
stack is organized into 4 levels for the HT46R46/
1 1 H
HT46C46 or 6 levels for the HT46R47/HT46C47 and
1 2 H P A
are neither part of the data nor part of the program S p e c ia l P u r p o s e
1 3 H P A C
D A T A M E M O R Y
space, and is neither readable nor writeable. The acti- 1 4 H P B
vated level is indexed by the stack pointer (SP) and is 1 5 H P B C
neither readable nor writeable. At a subroutine call or in- 1 6 H
terrupt acknowledgment, the contents of the program 1 7 H
1 8 H P D
counter are pushed onto the stack. At the end of a sub-
1 9 H P D C
routine or an interrupt routine, signaled by a return in-
1 A H P W M
struction (RET or RETI), the program counter is restored 1 B H
to its previous value from the stack. After a chip reset, 1 C H
the SP will point to the top of the stack. 1 D H
1 E H
If the stack is full and a non-masked interrupt takes
1 F H
place, the interrupt request flag will be recorded but the 2 0 H
acknowledgment will be inhibited. When the stack 2 1 H A D R
pointer is decremented (by RET or RETI), the interrupt 2 2 H A D C R
will be serviced. This feature prevents stack overflow al- 2 3 H A C S R
2 4 H
lowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a ²CALL² is sub- 3 F H
4 0 H
sequently executed, stack overflow occurs and the first G e n e ra l P u rp o s e
e n t ry w i l l b e l o s t ( onl y t h e m os t r e ce n t 4 D A T A M E M O R Y : U n u s e d
(HT46R47/HT46C46) or 6 (HT46R47/HT46C47) return (6 4 B y te s )
R e a d a s "0 0 "
7 F H
addresses are stored).
RAM Mapping for the HT46R46/HT46C46
Data Memory - RAM
The data memory is designed with 84´8 bits HT46R47/HT46C47, the A/D result higher-order byte
(HT46R46/HT46C46) or 85´8 bits (HT46R47/HT46C47). register (ADRH;21H) for the HT46R47/HT46C47, the
The data memory is divided into two functional groups: A/D control register (ADCR;22H), the A/D clock setting
special function registers and general purpose data register (ACSR;23H), I/O registers (PA;12H, PB;14H,
memory (64´8). Most are read/write, but some are PD;18H) and I/O control registers (PAC;13H,
read only. PBC;15H, PDC;19H). The remaining space before the
40H is reserved for future expanded usage and reading
The special function registers include the indirect ad-
dressing register (00H), timer/event counter these locations will get ²00H². The general purpose
(TMR;0DH), timer/event counter control register data memory, addressed from 40H to 7FH, is used for
(TMRC;0EH), program counter lower-order byte regis- data and control information under instruction com-
ter (PCL;06H), memory pointer register (MP;01H), ac- mands.
cumulator (ACC;05H), table pointer (TBLP;07H), table All of the data memory areas can handle arithmetic,
higher-order byte register (TBLH;08H), status register logic, increment, decrement and rotate operations di-
(STATUS;0AH), interrupt control register (INTC;0BH), rectly. Except for some dedicated bits, each bit in the
PWM data register (PWM;1AH), the A/D result register data memory can be set and reset by ²SET [m].i² and
(ADR;21H) for the HT46R46/HT46C46, the A/D result ²CLR [m].i². They are also indirectly accessible through
lower-order byte register (ADRL;20H) for the memory pointer register (MP;01H).

Rev. 1.30 8 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

0 0 H In d ir e c t A d d r e s s in g R e g is te r Indirect Addressing Register


0 1 H M P
Location 00H is an indirect addressing register that is
0 2 H
not physically implemented. Any read/write operation of
0 3 H
0 4 H
[00H] accesses data memory pointed to by MP (01H).
0 5 H A C C Reading location 00H itself indirectly will return the re-
0 6 H P C L sult 00H. Writing indirectly results in no operation.
0 7 H T B L P
The memory pointer register MP (01H) is a 7-bit register.
0 8 H T B L H
The bit 7 of MP is undefined and reading will return the
0 9 H
0 A H S T A T U S result ²1². Any writing operation to MP will only transfer the
0 B H IN T C lower 7-bit data to MP.
0 C H
0 D H T M R Accumulator
0 E H T M R C
The accumulator is closely related to ALU operations. It
0 F H
1 0 H is also mapped to location 05H of the data memory and
1 1 H can carry out immediate data operations. The data
1 2 H P A movement between two data memory locations must
S p e c ia l P u r p o s e
1 3 H P A C pass through the accumulator.
D A T A M E M O R Y
1 4 H P B
1 5 H P B C Arithmetic and Logic Unit - ALU
1 6 H
1 7 H This circuit performs 8-bit arithmetic and logic opera-
1 8 H P D tions. The ALU provides the following functions:
1 9 H P D C · Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
1 A H P W M
· Logic operations (AND, OR, XOR, CPL)
1 B H
1 C H · Rotation (RL, RR, RLC, RRC)
1 D H · Increment and Decrement (INC, DEC)
1 E H
· Branch decision (SZ, SNZ, SIZ, SDZ ....)
1 F H
2 0 H A D R L The ALU not only saves the results of a data operation but
2 1 H A D R H also changes the status register.
2 2 H A D C R
2 3 H A C S R
2 4 H Status Register - STATUS
This 8-bit register (0AH) contains the zero flag (Z), carry
3 F H
4 0 H flag (C), auxiliary carry flag (AC), overflow flag (OV),
G e n e ra l P u rp o s e
: U n u s e d power down flag (PDF), and watchdog time-out flag
D A T A M E M O R Y
(6 4 B y te s ) (TO). It also records the status information and controls
R e a d a s "0 0 "
7 F H the operation sequence.

RAM Mapping for the HT46R47/HT46C47

Bit No. Label Function


C is set if an operation results in a carry during an addition operation or if a borrow does not take
0 C place during a subtraction operation, otherwise C is cleared. C is also affected by a rotate
through carry instruction.
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the
1 AC
high nibble into the low nibble in subtraction, otherwise AC is cleared.
2 Z Z is set if the result of an arithmetic or logic operation is zero, otherwise Z is cleared.
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the high-
3 OV
est-order bit, or vice versa, otherwise OV is cleared.
PDF is cleared by a system power-up or executing the ²CLR WDT² instruction. PDF is set by exe-
4 PDF
cuting the ²HALT² instruction.
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is
5 TO
set by a WDT time-out.
6, 7 ¾ Unused bit, read as ²0²

Status (0AH) Register

Rev. 1.30 9 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

With the exception of the TO and PDF flags, bits in a branch to a subroutine at specified location in the pro-
the status register can be altered by instructions like gram memory. Only the program counter is pushed onto
most other registers. Any data written into the status the stack. If the contents of the register or status register
register will not change the TO or PDF flag. In addi- (STATUS) are altered by the interrupt service program
tion operations related to the status register may give which corrupts the desired control sequence, the con-
different results from those intended. The TO flag tents should be saved in advance.
can be affected only by system power-up, a WDT External interrupts are triggered by a high to low transi-
time-out or executing the ²CLR WDT² or ²HALT² in- tion of INT and the related interrupt request flag (EIF; bit
struction. The PDF flag can be affected only by exe- 4 of INTC) will be set. When the interrupt is enabled, the
cuting the ²HALT² or ²CLR WDT² instruction or a stack is not full and the external interrupt is active, a sub-
system power-up. routine call to location 04H will occur. The interrupt re-
The Z, OV, AC and C flags generally reflect the status of quest flag (EIF) and EMI bits will be cleared to disable
the latest operations. other interrupts.

In addition, on entering the interrupt sequence or exe- The internal timer/event counter interrupt is initialized by
cuting the subroutine call, the status register will not be setting the timer/event counter interrupt request flag
pushed onto the stack automatically. If the contents of (TF;bit 5 of INTC), caused by a timer overflow. When the
the status are important and if the subroutine can cor- interrupt is enabled, the stack is not full and the TF bit is
rupt the status register, precautions must be taken to set, a subroutine call to location 08H will occur. The re-
save it properly. lated interrupt request flag (TF) will be reset and the EMI
bit cleared to disable further interrupts.
Interrupt
The A/D converter interrupt is initialized by setting the
The device provides an external interrupt, internal A/D converter request flag (ADF; bit 6 of INTC), caused
timer/event counter interrupt and A/D converter inter- by an end of A/D conversion. When the interrupt is en-
rupts. The Interrupt Control Register (INTC;0BH) con- abled, the stack is not full and the ADF is set, a subrou-
tains the interrupt control bits to set the enable or disable tine call to location 0CH will occur. The related interrupt
and the interrupt request flags. request flag (ADF) will be reset and the EMI bit cleared
Once an interrupt subroutine is serviced, all the other in- to disable further interrupts.
terrupts will be blocked (by clearing the EMI bit). This During the execution of an interrupt subroutine, other in-
scheme may prevent any further interrupt nesting. Other terrupt acknowledgments are held until the RETI in-
interrupt requests may happen during this interval but struction is executed or the EMI bit and the related
only the interrupt request flag is recorded. If a certain in- interrupt control bit are set to 1 (of course, if the stack is
terrupt requires servicing within the service routine, the not full). To return from the interrupt subroutine, RET or
EMI bit and the corresponding bit of INTC may be set to RETI may be invoked. RETI will set the EMI bit to enable
allow interrupt nesting. If the stack is full, the interrupt re- an interrupt service, but RET will not.
quest will not be acknowledged, even if the related inter-
Interrupts, occurring in the interval between the rising
rupt is enabled, until the SP is decremented. If immediate
edges of two consecutive T2 pulses, will be serviced on
service is desired, the stack must be prevented from be-
the latter of the two T2 pulses, if the corresponding inter-
coming full.
rupts are enabled. In the case of simultaneous requests
All these kinds of interrupts have a wake-up capability. the following table shows the priority that is applied.
As an interrupt is serviced, a control transfer occurs by These can be masked by resetting the EMI bit.
pushing the program counter onto the stack, followed by

Bit No. Label Function


0 EMI Controls the master (global) interrupt (1=enabled; 0=disabled)
1 EEI Controls the external interrupt (1=enabled; 0=disabled)
2 ETI Controls the Timer/Event Counter interrupt (1=enabled; 0=disabled)
3 EADI Controls the A/D converter interrupt (1=enabled; 0=disabled)
4 EIF External interrupt request flag (1=active; 0=inactive)
5 TF Internal Timer/Event Counter request flag (1=active; 0=inactive)
6 ADF A/D converter request flag (1=active; 0=inactive)
For test mode used only.
7 ¾
Must be written as ²0²; otherwise may result in unpredictable operation.

INTC (0BH) Register

Rev. 1.30 10 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

Interrupt Source Priority Vector If the Crystal oscillator is used, a crystal across OSC1
and OSC2 is needed to provide the feedback and phase
External Interrupt 1 04H
shift required for the oscillator, and no other external
Timer/Event Counter Overflow 2 08H components are required. Instead of a crystal, a resona-
A/D Converter Interrupt 3 0CH tor can also be connected between OSC1 and OSC2 to
get a frequency reference, but two external capacitors in
The timer/event counter interrupt request flag (TF), ex- OSC1 and OSC2 are required (If the oscillating fre-
ternal interrupt request flag (EIF), A/D converter request quency is less than 1MHz).
flag (ADF), enable timer/event counter bit (ETI), enable The WDT oscillator is a free running on-chip RC oscilla-
external interrupt bit (EEI), enable A/D converter inter- tor, and no external components are required. Even if
rupt bit (EADI) and enable master interrupt bit (EMI) the system enters the power down mode, the system
constitute an interrupt control register (INTC) which is clock is stopped, but the WDT oscillator still works with a
located at 0BH in the data memory. EMI, EEI, ETI, EADI period of approximately 65ms@5V. The WDT oscillator
are used to control the enabling/disabling of interrupts. can be disabled by options to conserve power.
These bits prevent the requested interrupt from being
serviced. Once the interrupt request flags (TF, EIF, ADF) Watchdog Timer - WDT
are set, they will remain in the INTC register until the in-
The clock source of WDT is implemented by a dedicated
terrupts are serviced or cleared by a software instruc-
RC oscillator (WDT oscillator) or instruction clock (sys-
tion.
tem clock divided by 4), decided by options. This timer is
It is recommended that a program does not use the CALL designed to prevent a software malfunction or sequence
subroutine within the interrupt subroutine. Interrupts of- from jumping to an unknown location with unpredictable
ten occur in an unpredictable manner or need to be ser- results. The Watchdog Timer can be disabled by an op-
viced immediately in some applications. If only one stack tion. If the Watchdog Timer is disabled, all the execu-
is left and enabling the interrupt is not well controlled, the tions related to the WDT result in no operation.
original control sequence will be damaged once the
Once the internal oscillator (RC oscillator with a period
²CALL² operates in the interrupt subroutine.
of 65ms@5V normally) is selected, it is divided by
Oscillator Configuration 32768~65536 to get the time-out period of approxi-
mately 2.1s~4.3s. This time-out period may vary with
There are two oscillator circuits in the microcontroller.
temperatures, VDD and process variations. If the WDT
V D D oscillator is disabled, the WDT clock may still come from
4 7 0 p F
O S C 1 O S C 1 the instruction clock and operate in the same manner
except that in the HALT state the WDT may stop count-
ing and lose its protecting purpose. In this situation the
O S C 2 fS Y S /4 O S C 2 logic can only be restarted by external logic.

C r y s ta l O s c illa to r R C O s c illa to r If the device operates in a noisy environment, using the


on-chip RC oscillator (WDT OSC) is strongly recom-
System Oscillator mended, since the HALT will stop the system clock.
The WDT overflow under normal operation will initialize
Both are designed for system clocks, namely the RC os-
²chip reset² and set the status bit ²TO². But in the HALT
cillator and the Crystal oscillator, which are determined
by the options. No matter what oscillator type is se- mode, the overflow will initialize a ²warm reset², and
lected, the signal provides the system clock. The HALT only the program counter and SP are reset to zero. To
mode stops the system oscillator and ignores an exter- clear the contents of WDT, three methods are adopted;
nal signal to conserve power. external reset (a low level to RES), software instruction
and a HALT instruction. The software instruction include
If an RC oscillator is used, an external resistor between
²CLR WDT² and the other set - ²CLR WDT1² and ²CLR
OSC1 and VSS is required and the resistance must
WDT2². Of these two types of instruction, only one can
range from 30kW to 750kW. The system clock, divided
be active depending on the options - ²CLR WDT times
by 4, is available on OSC2 with pull-high resistor, which
selection option². If the ²CLR WDT² is selected (i.e. CLR
can be used to synchronize external logic. The RC os-
cillator provides the most cost effective solution. How- WDT times equal one), any execution of the ²CLR
ever, the frequency of oscillation may vary with VDD, WDT² instruction will clear the WDT. In the case that
temperatures and the chip itself due to process varia- ²CLR WDT1² and ²CLR WDT2² are chosen (i.e. CLR
tions. It is, therefore, not suitable for timing sensitive WDT times equal two), these two instructions must be
operations where an accurate oscillator frequency is executed to clear the WDT; otherwise, the WDT may re-
desired. set the chip as a result of time-out.

Rev. 1.30 11 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

S y s te m C lo c k /4

O p tio n fS W D T T im e - o u t
8 - b it C o u n te r 7 - b it C o u n te r T T 1 5 1 6
S e le c t fS /2 ~ fS /2
W D T
O S C C L R W D T

Watchdog Timer

Power Down Operation - HALT Once a wake-up event occurs, it takes 1024 tSYS (sys-
tem clock period) to resume normal operation. In other
The HALT mode is initialized by the ²HALT² instruction
words, a dummy period will be inserted after wake-up. If
and results in the following...
the wake-up results from an interrupt acknowledgment,
· The system oscillator will be turned off but the WDT
the actual interrupt subroutine execution will be delayed
oscillator keeps running (if the WDT oscillator is se-
by one or more cycles. If the wake-up results in the next
lected).
instruction execution, this will be executed immediately
· The contents of the on chip RAM and registers remain
after the dummy period is finished.
unchanged.
· WDT will be cleared and recounted again (if the WDT To minimize power consumption, all the I/O pins should
clock is from the WDT oscillator). be carefully managed before entering the HALT status.
· All of the I/O ports maintain their original status.
Reset
· The PDF flag is set and the TO flag is cleared.
There are three ways in which a reset can occur:
The system can leave the HALT mode by means of an · RES reset during normal operation
external reset, an interrupt, an external falling edge sig-
· RES reset during HALT
nal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow per- · WDT time-out reset during normal operation

forms a ²warm reset². After the TO and PDF flags are The WDT time-out during HALT is different from other
examined, the reason for chip reset can be determined. chip reset conditions, since it can perform a ²warm re -
The PDF flag is cleared by system power-up or execut- set² that resets only the program counter and SP, leav-
ing the ²CLR WDT² instruction and is set when execut- ing the other circuits in their original state. Some regis-
ing the ²HALT² instruction. The TO flag is set if the WDT ters remain unchanged during other reset conditions.
time-out occurs, and causes a wake-up that only resets Most registers are reset to the ²initial condition² when
the program counter and SP; the others keep their origi- the reset conditions are met. By examining the PDF and
nal status. TO flags, the program can distinguish between different
The port A wake-up and interrupt methods can be con- ²chip resets².
sidered as a continuation of normal execution. Each bit
TO PDF RESET Conditions
in port A can be independently selected to wake up the
device by the options. Awakening from an I/O port stim- 0 0 RES reset during power-up
ulus, the program will resume execution of the next in- u u RES reset during normal operation
struction. If it is awakening from an interrupt, two
0 1 RES wake-up HALT
sequences may happen. If the related interrupt is dis-
abled or the interrupt is enabled but the stack is full, the 1 u WDT time-out during normal operation
program will resume execution at the next instruction. If 1 1 WDT wake-up HALT
the interrupt is enabled and the stack is not full, the regu-
lar interrupt response takes place. If an interrupt request Note: ²u² means ²unchanged²
flag is set to ²1² before entering the HALT mode, the
wake-up function of the related interrupt will be disabled.

Rev. 1.30 12 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

V D D
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an 0 .0 1 m F *

extra-delay of 1024 system clock pulses when the sys- 1 0 0 k W


tem reset (power-up, WDT time-out or RES reset) or the
R E S
system awakes from the HALT state.
1 0 k W
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will en- 0 .1 m F *

able the SST delay.


Reset Circuit
An extra option load time delay is added during system
reset (power-up, WDT time-out at normal mode or RES Note: ²*² Make the length of the wiring, which is con-
reset). nected to the RES pin as short as possible, to
The functional unit chip reset status are shown below. avoid noise interference.

Program Counter 000H


Interrupt Disable H A L T W a rm R e s e t
Clear. After master reset,
WDT W D T
WDT begins counting
Timer/Event Counter Off R E S
Input/Output Ports Input mode C o ld
R e s e t
Stack Pointer Points to the top of the stack S S T
O S C 1 1 0 - b it R ip p le
C o u n te r

V D D S y s te m R e s e t

R E S
tS S T
Reset Configuration
S S T T im e - o u t

C h ip R e s e t

Reset Timing Chart

Rev. 1.30 13 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

The registers¢ states are summarized in the following table.

Reset WDT Time-out RES Reset RES Reset WDT Times-out


Register
(Power On) (Normal Operation) (Normal Operation) (HALT) (HALT)*
MP -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu
ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
Program Counter 000H 000H 000H 000H 000H
TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
TBLH --xx xxxx --uu uuuu --uu uuuu --uu uuuu --uu uuuu
STATUS --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu
INTC -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu
TMR xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu
TMRC 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu
PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PB ---- 1111 ---- 1111 ---- 1111 ---- 1111 ---- uuuu
PBC ---- 1111 ---- 1111 ---- 1111 ---- 1111 ---- uuuu
PD ---- ---1 ---- ---1 ---- ---1 ---- ---1 ---- ---u
PDC ---- ---1 ---- ---1 ---- ---1 ---- ---1 ---- ---u
PWM xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu
ADR
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu
(HT46R46/HT46C46)

ADRL
x--- ---- x--- ---- x--- ---- x--- ---- u--- ----
(HT46R47/HT46C47)

ADRH
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu
(HT46R47/HT46C47)

ADCR 0100 0000 0100 0000 0100 0000 0100 0000 uuuu uuuu
ACSR 1--- --00 1--- --00 1--- --00 1--- --00 u--- --uu

Note: ²*² stands for warm reset


²u² stands for unchanged
²x² stands for unknown

Rev. 1.30 14 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

Timer/Event Counter In the event count or timer mode, once the timer/event
A timer/event counter (TMR) is implemented in the counter starts counting, it will count from the current
microcontroller. The timer/event counter contains an contents in the timer/event counter to FFH. Once over-
flow occurs, the counter is reloaded from the timer/event
8-bit programmable count-up counter and the clock may
counter preload register and generates the interrupt re-
come from an external source or the system clock.
quest flag (TF; bit 5 of INTC) at the same time.
Using external clock input allows the user to count exter-
nal events, measure time internals or pulse widths, or In the pulse width measurement mode with the TON
generate an accurate time base. While using the inter- and TE bits equal to one, once the TMR has received a
nal clock allows the user to generate an accurate time transient from low to high (or high to low if the TE bits is
base. ²0²) it will start counting until the TMR returns to the orig-
inal level and resets the TON. The measured result will
The timer/event counter can generate PFD signal by us- remain in the timer/event counter even if the activated
ing external or internal clock and PFD frequency is de- transient occurs again. In other words, only one cycle
termine by the equation fINT/[2´(256-N)]. measurement can be done. Until setting the TON, the
There are 2 registers related to the timer/event counter; cycle measurement will function again as long as it re-
TMR ([0DH]), TMRC ([0EH]). Two physical registers are ceives further transient pulse. Note that, in this operat-
mapped to TMR location; writing TMR makes the start- ing mode, the timer/event counter starts counting not
ing value be placed in the timer/event counter preload according to the logic level but according to the transient
register and reading TMR retrieves the contents of the edges. In the case of counter overflows, the counter is
timer/event counter. The TMRC is a timer/event counter reloaded from the timer/event counter preload register
control register, which defines some options. and issues the interrupt request just like the other two
modes. To enable the counting operation, the timer ON
The TM0, TM1 bits define the operating mode. The
bit (TON; bit 4 of TMRC) should be set to 1. In the pulse
event count mode is used to count external events,
width measurement mode, the TON will be cleared au-
which means the clock source comes from an external
tomatically after the measurement cycle is completed.
(TMR) pin. The timer mode functions as a normal timer
But in the other two modes the TON can only be reset by
with the clock source coming from the fINT clock. The
instructions. The overflow of the timer/event counter is
pulse width measurement mode can be used to count the
one of the wake-up sources. No matter what the opera-
high or low level duration of the external signal (TMR). The
tion mode is, writing a 0 to ETI can disable the interrupt
counting is based on the fINT.
service.

Bit No. Label Function


Defines the prescaler stages, PSC2, PSC1, PSC0=
000: fINT=fSYS
001: fINT=fSYS/2
0 PSC0 010: fINT=fSYS/4
1 PSC1 011: fINT=fSYS/8
2 PSC2 100: fINT=fSYS/16
101: fINT=fSYS/32
110: fINT=fSYS/64
111: fINT=fSYS/128
Defines the TMR active edge of the timer/event counter:
In Event Counter Mode (TM1,TM0)=(0,1):
1:count on falling edge;
3 TE 0:count on rising edge
In Pulse Width measurement mode (TM1,TM0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
Enable or disable the timer counting
4 TON
(0=disable; 1=enable)
5 ¾ Unused bits, read as ²0²
Defines the operating mode (TM1, TM0)=
01=Event count mode (external clock)
6 TM0
10=Timer mode (internal clock)
7 TM1
11=Pulse width measurement mode
00=Unused

TMRC (0EH) Register

Rev. 1.30 15 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

P W M

(6 + 2 ) C o m p a re T o P D 0 C ir c u it

fS Y S 8 - s ta g e P r e s c a le r
f IN T D a ta B u s
8 -1 M U X
T M 1
T M 0 8 - B it T im e r /E v e n t R e lo a d
C o u n te r P r e lo a d
P S C 2 ~ P S C 0 T M R R e g is te r
T E

P u ls e W id th 8 - B it T im e r /E v e n t O v e r flo w
T M 1 M e a s u re m e n t C o u n te r
T M 0 to In te rru p t
M o d e C o n tro l
T O N
1 /2 P F D

Timer/Event Counter

In the case of timer/event counter OFF condition, writing respectively. All of these I/O ports can be used for input
data to the timer/event counter preload register will also and output operations. For input operation, these ports
reload that data to the timer/event counter. But if the are non-latching, that is, the inputs must be ready at the
timer/event counter is turned on, data written to it will T2 rising edge of instruction ²MOV A,[m]² (m=12H, 14H
only be kept in the timer/event counter preload register. or 18H). For output operation, all the data is latched and
The timer/event counter will still operate until overflow remains unchanged until the output latch is rewritten.
occurs. When the timer/event counter (reading TMR) is
Each I/O line has its own control register (PAC, PBC,
read, the clock will be blocked to avoid errors. As clock
PDC) to control the input/output configuration. With this
blocking may results in a counting error, this must be
control register, CMOS output or Schmitt trigger input
taken into consideration by the programmer.
with or without pull-high resistor structures can be re-
The bit0~bit2 of the TMRC can be used to define the configured dynamically (i.e. on-the-fly) under software
pre-scaling stages of the internal clock sources of control. To function as an input, the corresponding latch
timer/event counter. The definitions are as shown. The of the control register must write ²1². The input source
overflow signal of timer/event counter can be used to also depends on the control register. If the control regis-
generate the PFD signal. ter bit is ²1², the input will read the pad state. If the con-
trol register bit is ²0², the contents of the latches will
Input/Output Ports
move to the internal bus. The latter is possible in the
There are 13 bidirectional input/output lines in the ²read-modify-write² instruction.
microcontroller, labeled as PA, PB and PD, which are
mapped to the data memory of [12H], [14H] and [18H]
V D D

C o n tr o l B it P U
D a ta B u s D Q

W r ite C o n tr o l R e g is te r C K Q B
C h ip R e s e t S P A 0 ~ P A 2
P A 3 /P F D
P A 4 /T M R
R e a d C o n tr o l R e g is te r P A 5 /IN T
D a ta B it P A 6 , P A 7
D Q P B 0 /A N 0 ~ P B 3 /A N 3
P D 0 /P W M
W r ite D a ta R e g is te r C K Q B
S
M
U
(P D 0 o r P W M ) P A 3 X
P F D
P F D E N
M (P A 3 )
U
X
R e a d D a ta R e g is te r
S y s te m W a k e -u p
( P A o n ly ) W a k e - u p o p tio n
IN T fo r P A 5 O n ly
T M R fo r P A 4 O n ly
Input/Output Ports

Rev. 1.30 16 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

For output function, CMOS is the only configuration. will enable the PWM output function and writing ²0² will
These control registers are mapped to locations 13H, force the PD0 to remain at ²0². The I/O functions of PD0
15H and 19H. are as shown.
After a chip reset, these input/output lines remain at high I/O I/P O/P I/P O/P
levels or floating state (dependent on pull-high options). Mode (Normal) (Normal) (PWM) (PWM)
Each bit of these input/output latches can be set or
Logical Logical Logical
cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H or PD0 PWM
Input Output Input
18H) instructions.
Some instructions first input data and then follow the It is recommended that unused or not bonded out I/O
lines should be set as output pins by software instruction
output operations. For example, ²SET [m].i², ²CLR
to avoid consuming power under input floating state.
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations PWM
(bit-operation), and then write the results back to the
latches or the accumulator. The microcontroller provides 1 channel (6+2) bits PWM
output shared with PD0. The PWM channel has its data
Each line of port A has the capability of waking-up the register denoted as PWM (1AH). The frequency source
device. The highest 4-bit of port B and 7 bits of port D of the PWM counter comes from fSYS. The PWM register
are not physically implemented; on reading them a ²0² is is an eight bits register. The waveforms of PWM output
returned whereas writing then results in a no-operation. are as shown. Once the PD0 is selected as the PWM
See Application note. output and the output function of PD0 is enabled
Each I/O line has a pull-high option. Once the pull-high (PDC.0=²0²), writing 1 to PD0 data register will enable
option is selected, the I/O line has a pull-high resistor, the PWM output function and writing ²0² will force the
otherwise, there¢s none. Take note that a non-pull-high PD0 to stay at ²0².
I/O line operating in input mode will cause a floating
A PWM cycle is divided into four modulation cycles
state.
(modulation cycle 0~modulation cycle 3). Each modula-
The PA3 is pin-shared with the PFD signal. If the PFD tion cycle has 64 PWM input clock period. In a (6+2) bit
option is selected, the output signal in output mode of PWM function, the contents of the PWM register is di-
PA3 will be the PFD signal generated by the timer/event vided into two groups. Group 1 of the PWM register is
counter overflow signal. The input mode always remain- denoted by DC which is the value of PWM.7~PWM.2.
ing its original functions. Once the PFD option is se-
The group 2 is denoted by AC which is the value of
lected, the PFD output signal is controlled by PA3 data
PWM.1~PWM.0.
register only. Writing ²1² to PA3 data register will enable
the PFD output function and writing ²0² will force the In a PWM cycle, the duty cycle of each modulation cycle
is shown in the table.
PA3 to remain at ²0². The I/O functions of PA3 are
shown below. Parameter AC (0~3) Duty Cycle
I/O I/P O/P I/P O/P DC+1
i<AC
Mode (Normal) (Normal) (PFD) (PFD) Modulation cycle i 64
Logical Logical Logical PFD (i=0~3) DC
PA3 i³AC
Input Output Input (Timer on) 64

Note: The PFD frequency is the timer/event counter The modulation frequency, cycle frequency and cycle
overflow frequency divided by 2. duty of the PWM output signal are summarized in the
The PA5 and PA4 are pin-shared with INT and TMR pins following table.
respectively.
PWM
PWM Cycle PWM Cycle
The PB can also be used as A/D converter inputs. The Modulation
Frequency Duty
A/D function will be described later. There is a PWM Frequency
function shared with PD0. If the PWM function is en- fSYS/64 fSYS/256 [PWM]/256
abled, the PWM signal will appear on PD0 (if PD0 is op-
erating in output mode). Writing ²1² to PD0 data register

Rev. 1.30 17 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

fS Y S /2

[P W M ] = 1 0 0

P W M
2 5 /6 4 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 5 /6 4
[P W M ] = 1 0 1

P W M
2 6 /6 4 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 6 /6 4
[P W M ] = 1 0 2

P W M
2 6 /6 4 2 6 /6 4 2 5 /6 4 2 5 /6 4 2 6 /6 4
[P W M ] = 1 0 3

P W M
2 6 /6 4 2 6 /6 4 2 6 /6 4 2 5 /6 4 2 6 /6 4

P W M m o d u la tio n p e r io d : 6 4 /fS Y S
M o d u la tio n c y c le 0 M o d u la tio n c y c le 1 M o d u la tio n c y c le 2 M o d u la tio n c y c le 3 M o d u la tio n c y c le 0

P W M c y c le : 2 5 6 /fS Y S

PWM

A/D Converter to set PB configurations. PB can be an analog input or


The 4 channels and 8-bit resolution for the HT46R46/ as digital I/O line decided by these 3 bits. Once a PB line
HT46C46 or 9-bit resolution for the HT46R47/HT46C47 is selected as an analog input, the I/O functions and
A/D converter are implemented in this microcontroller. pull-high resistor of this I/O line are disabled, and the
The reference voltage is VDD. The A/D converter con- A/D converter circuit is power on. The EOCB bit (bit6 of
tains 3 special registers for the HT46R46/HT46C46 the ADCR) is end of A/D conversion flag. Check this bit
which are; ADR (21H), ADCR (22H) and ACSR (23H) or to know when A/D conversion is completed. The START
contains 4 special registers for the HT46R47/HT46C47 bit of the ADCR is used to begin the conversion of A/D
whice are; ADRL (20H), ADRH (21H), ADCR (22H) and converter. Give START bit a raising edge and falling
ACSR (23H). The ADR is HT46R46/ HT46C46 an A/D edge that means the A/D conversion has started. In or-
result register that is read-only. The ADRH and ADRL der to ensure the A/D conversion is completed, the
are HT46R47/HT46C47 A/D result register higher-order START should stay at ²0² until the EOCB is cleared to
byte and lower-order byte which are read-only. After the ²0² (end of A/D conversion).
A/D conversion is completed, the ADR (HT46R46/ Bit 7 of the ACSR register is used for test purposes only
HT46C46) or ADRL, ADRH (HT46R47/HT46C47) and must not be used for other purposes by the applica-
should be read to get the conversion result data. The tion program. Bit1 and bit0 of the ACSR register are
ADCR is an A/D converter control register, which de- used to select the A/D clock source.
fines the A/D channel number, analog channel select,
When the A/D conversion has completed, the A/D inter-
start A/D conversion control bit and the end of A/D con-
version flag. If the users want to start an A/D conversion, rupt request flag will be set. The EOCB bit is set to ²1²
define PB configuration, select the converted analog when the START bit is set from ²0² to ²1².
channel, and give START bit a raising edge and a falling Important Note for A/D initialization:
edge (0®1®0). At the end of A/D conversion, the Special care must be taken to initialize the A/D con-
EOCB bit is cleared and an A/D converter interrupt oc- verter each time the Port B A/D channel selection bits
curs (if the A/D converter interrupt is enabled). The are modified, otherwise the EOCB flag may be in an un-
ACSR is A/D clock setting register, which is used to se- defined condition. An A/D initialization is implemented
lect the A/D clock source. by setting the START bit high and then clearing it to zero
The A/D converter control register is used to control the within 10 instruction cycles of the Port B channel selec-
A/D converter. The bit2~bit0 of the ADCR are used to tion bits being modified. Note that if the Port B channel
select an analog input channel. There are a total of four selection bits are all cleared to zero then an A/D initial-
channels to select. The bit5~bit3 of the ADCR are used ization is not required.

Rev. 1.30 18 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0


ADR D7 D6 D5 D4 D3 D2 D1 D0

Note: D0~D7 is A/D conversion result data bit LSB~MSB.


ADR (21H) Register for HT46R46/HT46C46

Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0


ADRL D0 ¾ ¾ ¾ ¾ ¾ ¾ ¾
ADRH D8 D7 D6 D5 D4 D3 D2 D1

Note: D0~D8 is A/D conversion result data bit LSB~MSB.


ADRL (20H), ADRH (21H) Register for HT46R47/HT46C47

Bit No. Label Function


ACS2, ACS1, ACS0: Select A/D channel
0, 0, 0: AN0
0 ACS0
0, 0, 1: AN1
1 ACS1
0, 1, 0: AN2
2 ACS2
0, 1, 1: AN3
1, X, X: undefined, cannot be used
PCR2, PCR1, PCR0: PB3~PB0 configurations
0, 0, 0: PB3 PB2 PB1 PB0 (The ADC circuit is power off to reduce power consumption.)
3 PCR0
0, 0, 1: PB3 PB2 PB1 AN0
4 PCR1
0, 1, 0: PB3 PB2 AN1 AN0
5 PCR2
0, 1, 1: PB3 AN2 AN1 AN0
1, x, x: AN3 AN2 AN1 AN0
Indicates end of A/D conversion. (0 = end of A/D conversion)
6 EOCB Each time bits 3~5 change state the A/D should be initialized by issuing a START signal, other-
wise the EOCB flag may have an undefined condition. See ²Important note for A/D initialization².
7 START Starts the A/D conversion. (0®1®0= start; 0®1= Reset A/D converter and set EOCB to ²1²)

ADCR (22H) Register

Bit No. Label Function


Select the A/D converter clock source.
0, 0: fSYS/2
0 ADCS0
0, 1: fSYS/8
1 ADCS1
1, 0: fSYS/32
1, 1: Undefined
2~6 ¾ Unused bit, read as ²0².
7 TEST For internal test only.

ACSR (23H) Register

Rev. 1.30 19 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

The following two programming examples illustrate how to setup and implement an A/D conversion. In the first exam-
ple, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete,
whereas in the second example, the A/D interrupt is used to determine when the conversion is complete.
Example: using EOCB Polling Method to detect end of conversion for the HT46R46/HT46C46
clr EADI ; disable ADC interrupt
mov a,00000001B
mov ACSR,a ; setup the ACSR register to select fSYS/8 as the A/D clock
mov a,00100000B ; setup ADCR register to configure Port PB0~PB3 as A/D inputs
mov ADCR,a ; and select AN0 to be connected to the A/D converter
:
: ; As the Port B channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
:
Start_conversion:
clr START
set START ; reset A/D
clr START ; start A/D
Polling_EOC:
sz EOCB ; poll the ADCR register EOCB bit to detect end of A/D conversion
jmp polling_EOC ; continue polling
mov a,ADR ; read conversion result value from the ADR register
mov adr_buffer,a ; save result to user defined memory
:
:
jmp start_conversion ; start next A/D conversion

Example: using interrupt method to detect end of conversion for the HT46R46/HT46C46
clr EADI ; disable ADC interrupt
mov a,00000001B
mov ACSR,a ; setup the ACSR register to select fSYS/8 as the A/D clock

mov a,00100000B ; setup ADCR register to configure Port PB0~PB3 as A/D inputs
mov ADCR,a ; and select AN0 to be connected to the A/D converter
:
; As the Port B channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
:
Start_conversion:
clr START
set START ; reset A/D
clr START ; start A/D
clr ADF ; clear ADC interrupt request flag
set EADI ; enable ADC interrupt
set EMI ; enable global interrupt
:
:
:
; ADC interrupt service routine
ADC_ISR:
mov acc_stack,a ; save ACC to user defined memory
mov a,STATUS
mov status_stack,a ; save STATUS to user defined memory

Rev. 1.30 20 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

:
:
mov a,ADR ; read conversion result value from the ADR register
mov adr_buffer,a ; save result to user defined register
clr START
set START ; reset A/D
clr START ; start A/D
:
:
EXIT_INT_ISR:
mov a,status_stack
mov STATUS,a ; restore STATUS from user defined memory
mov a,acc_stack ; restore ACC from user defined memory
reti

Example: using EOCB Polling Method to detect end of conversion for the HT46R47/HT46C47
clr EADI ; disable ADC interrupt
mov a,00000001B
mov ACSR,a ; setup the ACSR register to select fSYS/8 as the A/D clock
mov a,00100000B ; setup ADCR register to configure Port PB0~PB3 as A/D inputs
mov ADCR,a ; and select AN0 to be connected to the A/D converter
:
: ; As the Port B channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
:
Start_conversion:
clr START
set START ; reset A/D
clr START ; start A/D
Polling_EOC:
sz EOCB ; poll the ADCR register EOCB bit to detect end of A/D conversion
jmp polling_EOC ; continue polling
mov a,ADRH ; read conversion result high byte value from the ADRH register
mov adrh_buffer,a ; save result to user defined memory
mov a,ADRL ; read conversion result low byte value from the ADRL register
mov adrl_buffer,a ; save result to user defined memory
:
:
jmp start_conversion ; start next A/D conversion

Example: using interrupt method to detect end of conversion for the HT46R47/HT46C47
clr EADI ; disable ADC interrupt
mov a,00000001B
mov ACSR,a ; setup the ACSR register to select fSYS/8 as the A/D clock

mov a,00100000B ; setup ADCR register to configure Port PB0~PB3 as A/D inputs
mov ADCR,a ; and select AN0 to be connected to the A/D converter
:
; As the Port B channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
:

Rev. 1.30 21 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

Start_conversion:
clr START
set START ; reset A/D
clr START ; start A/D
clr ADF ; clear ADC interrupt request flag
set EADI ; enable ADC interrupt
set EMI ; enable global interrupt
:
:
:
; ADC interrupt service routine
ADC_ISR:
mov acc_stack,a ; save ACC to user defined memory
mov a,STATUS
mov status_stack,a ; save STATUS to user defined memory
:
:
mov a,ADRH ; read conversion result high byte value from the ADRH register
mov adrh_buffer,a ; save result to user defined register
mov a,ADRL ; read conversion result low byte value from the ADRL register
mov adrl_buffer,a ; save result to user defined register
clr START
set START ; reset A/D
clr START ; start A/D
:
:
EXIT_INT_ISR:
mov a,status_stack
mov STATUS,a ; restore STATUS from user defined memory
mov a,acc_stack ; restore ACC from user defined memory
reti

M in im u m o n e in s tr u c tio n c y c le n e e d e d , M a x im u m te n in s tr u c tio n c y c le s a llo w e d

S T A R T

E O C B A /D s a m p lin g tim e A /D s a m p lin g tim e A /D s a m p lin g tim e


tA D C S 1 tA D C S 1 tA D C S 1
tA D C S 2 tA D C S 2 tA D C S 2

P C R 2 ~ 0 0 0 B 1 0 0 B 1 0 0 B 1 0 1 B 0 0 0 B
P C R 0
1 . P B p o rt s e tu p a s I/O s
2 . A /D c o n v e r te r is p o w e r e d o ff
to r e d u c e p o w e r c o n s u m p tio n
A C S 2 ~
0 0 0 B 0 1 0 B 0 0 0 B 0 0 1 B d o n 't c a r e
A C S 0
P o w e r-o n S ta rt o f A /D S ta rt o f A /D S ta rt o f A /D
R e s e t c o n v e r s io n c o n v e r s io n c o n v e r s io n
R e s e t A /D R e s e t A /D R e s e t A /D
c o n v e rte r c o n v e rte r c o n v e rte r
E n d o f A /D E n d o f A /D E n d o f A /D
1 : D e fin e P B c o n fig u r a tio n c o n v e r s io n c o n v e r s io n c o n v e r s io n
2 : S e le c t a n a lo g c h a n n e l
tA D C 1 tA D C 1 tA D C 1
tA D C 2 tA D C 2 tA D C 2
A /D c o n v e r s io n tim e A /D c o n v e r s io n tim e A /D c o n v e r s io n tim e

N o te : A /D c lo c k m u s t b e fS Y S /2 , fS Y S /8 o r fS Y S /3 2
tA D C S 1 = 3 2 tA D fo r H T 4 6 R 4 6 /H T 4 6 C 4 6
tA D C S 2 = 3 2 tA D fo r H T 4 6 R 4 7 /H T 4 6 C 4 7
tA D C 1 = 6 4 tA D fo r H T 4 6 R 4 6 /H T 4 6 C 4 6
tA D C 2 = 7 6 tA D fo r H T 4 6 R 4 7 /H T 4 6 C 4 7

A/D Conversion Timing

Rev. 1.30 22 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

Low Voltage Reset - LVR The relationship between VDD and VLVR is shown below.
The microcontroller provides low voltage reset circuit in V D D V O P R
order to monitor the supply voltage of the device. If the 5 .5 V 5 .5 V
supply voltage of the device is within the range
0.9V~3.3V, such as changing a battery, the LVR will au-
tomatically reset the device internally.
V L V R
The LVR includes the following specifications:
3 .0 V
· The low voltage (0.9V~VLVR) has to remain in their 2 .2 V
original state to exceed 1ms. If the low voltage state
does not exceed 1ms, the LVR will ignore it and do not
perform a reset function.
0 .9 V
· The LVR uses the ²OR² function with the external RES
Note: VOPR is the voltage range for proper chip
signal to perform chip reset.
operation at 4MHz system clock.

V D D

5 .5 V

V L V R L V R D e te c t V o lta g e

0 .9 V

0 V

R e s e t S ig n a l

R e s e t N o r m a l O p e r a tio n R e s e t

*1 *2

Low Voltage Reset

Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before entering the normal operation.
*2: Since the low voltage has to maintain in its original state and exceed 1ms, therefore 1ms delay enter the
reset mode.

Options
The following table shows all kinds of options in the microcontroller. All of the options must be defined to ensure proper
system functioning.

No. Options
1 WDT clock source: WDTOSC or T1 (fSYS/4)
2 WDT function: enable or disable
3 CLRWDT instruction(s): one or two clear WDT instruction(s)
4 System oscillator: RC or crystal
5 Pull-high resistors (PA, PB, PD): none or pull-high
6 PWM enable or disable
7 PA0~PA7 wake-up: enable or disable
8 PFD enable or disable
9 Low voltage reset selection: enable or disable LVR function.

Rev. 1.30 23 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

Application Circuits

V D D

0 .0 1 m F *
V D D P A 0 ~ P A 2
V D D
1 0 0 k W P A 3 /P F D
0 .1 m F R E S P A 4 /T M R 4 7 0 p F R C S y s te m O s c illa to r
O S C 1
1 0 k W P A 5 /IN T 3 0 k W < R O S C < 7 5 0 k W
R O S C
P A 6 ~ P A 7 fS Y S /4
0 .1 m F * O S C 2
V S S P B 0 /A N 0 C 1

~
P B 3 /A N 3 O S C 1 C ry s ta l S y s te m O s c illa to r
F o r th e v a lu e s ,
P D 0 /P W M s e e ta b le b e lo w
O S C O S C 1 C 2
C ir c u it O S C 2 O S C 2
R 1
S e e R ig h t S id e
H T 4 6 R 4 6 /H T 4 6 C 4 6 O S C C ir c u it
H T 4 6 R 4 7 /H T 4 6 C 4 7

The following table shows the C1, C2 and R1 values corresponding to the different crystal values. (For reference only)

Crystal or Resonator C1, C2 R1


4MHz Crystal 0pF 10kW
4MHz Resonator 10pF 12kW
3.58MHz Crystal 0pF 10kW
3.58MHz Resonator 25pF 10kW
2MHz Crystal & Resonator 25pF 10kW
1MHz Crystal 35pF 27kW
480kHz Resonator 300pF 9.1kW
455kHz Resonator 300pF 10kW
429kHz Resonator 300pF 10kW
The function of the resistor R1 is to ensure that the oscillator will switch off should low voltage condi-
tions occur. Such a low voltage, as mentioned here, is one which is less than the lowest value of the
MCU operating voltage. Note however that if the LVR is enabled then R1 can be removed.

Note: The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is
stable and remains within a valid operating voltage range before bringing RES to high.
²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise
interference.

Rev. 1.30 24 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

Instruction Set Summary


Instruction Flag
Mnemonic Description
Cycle Affected
Arithmetic
ADD A,[m] Add data memory to ACC 1 Z,C,AC,OV
ADDM A,[m] Add ACC to data memory 1(1) Z,C,AC,OV
ADD A,x Add immediate data to ACC 1 Z,C,AC,OV
ADC A,[m] Add data memory to ACC with carry 1 Z,C,AC,OV
ADCM A,[m] Add ACC to data memory with carry 1(1) Z,C,AC,OV
SUB A,x Subtract immediate data from ACC 1 Z,C,AC,OV
SUB A,[m] Subtract data memory from ACC 1 Z,C,AC,OV
SUBM A,[m] Subtract data memory from ACC with result in data memory 1(1) Z,C,AC,OV
SBC A,[m] Subtract data memory from ACC with carry 1 Z,C,AC,OV
SBCM A,[m] Subtract data memory from ACC with carry and result in data memory 1(1) Z,C,AC,OV
DAA [m] Decimal adjust ACC for addition with result in data memory 1(1) C
Logic Operation
AND A,[m] AND data memory to ACC 1 Z
OR A,[m] OR data memory to ACC 1 Z
XOR A,[m] Exclusive-OR data memory to ACC 1 Z
ANDM A,[m] AND ACC to data memory 1(1) Z
ORM A,[m] OR ACC to data memory 1(1) Z
XORM A,[m] Exclusive-OR ACC to data memory 1(1) Z
AND A,x AND immediate data to ACC 1 Z
OR A,x OR immediate data to ACC 1 Z
XOR A,x Exclusive-OR immediate data to ACC 1 Z
CPL [m] Complement data memory 1(1) Z
CPLA [m] Complement data memory with result in ACC 1 Z
Increment & Decrement
INCA [m] Increment data memory with result in ACC 1 Z
INC [m] Increment data memory 1(1) Z
DECA [m] Decrement data memory with result in ACC 1 Z
DEC [m] Decrement data memory 1(1) Z
Rotate
RRA [m] Rotate data memory right with result in ACC 1 None
RR [m] Rotate data memory right 1(1) None
RRCA [m] Rotate data memory right through carry with result in ACC 1 C
RRC [m] Rotate data memory right through carry 1(1) C
RLA [m] Rotate data memory left with result in ACC 1 None
RL [m] Rotate data memory left 1(1) None
RLCA [m] Rotate data memory left through carry with result in ACC 1 C
RLC [m] Rotate data memory left through carry 1(1) C
Data Move
MOV A,[m] Move data memory to ACC 1 None
MOV [m],A Move ACC to data memory 1(1) None
MOV A,x Move immediate data to ACC 1 None
Bit Operation
CLR [m].i Clear bit of data memory 1(1) None
SET [m].i Set bit of data memory 1(1) None

Rev. 1.30 25 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

Instruction Flag
Mnemonic Description
Cycle Affected
Branch
JMP addr Jump unconditionally 2 None
SZ [m] Skip if data memory is zero 1(2) None
SZA [m] Skip if data memory is zero with data movement to ACC 1(2) None
SZ [m].i Skip if bit i of data memory is zero 1(2) None
SNZ [m].i Skip if bit i of data memory is not zero 1(2) None
SIZ [m] Skip if increment data memory is zero 1(3) None
SDZ [m] Skip if decrement data memory is zero 1(3) None
SIZA [m] Skip if increment data memory is zero with result in ACC 1(2) None
SDZA [m] Skip if decrement data memory is zero with result in ACC 1(2) None
CALL addr Subroutine call 2 None
RET Return from subroutine 2 None
RET A,x Return from subroutine and load immediate data to ACC 2 None
RETI Return from interrupt 2 None
Table Read
TABRDC [m] Read ROM code (current page) to data memory and TBLH 2(1) None
TABRDL [m] Read ROM code (last page) to data memory and TBLH 2(1) None
Miscellaneous
NOP No operation 1 None
CLR [m] Clear data memory 1(1) None
SET [m] Set data memory 1(1) None
CLR WDT Clear Watchdog Timer 1 TO,PDF
CLR WDT1 Pre-clear Watchdog Timer 1 TO(4),PDF(4)
CLR WDT2 Pre-clear Watchdog Timer 1 TO(4),PDF(4)
SWAP [m] Swap nibbles of data memory 1(1) None
SWAPA [m] Swap nibbles of data memory with result in ACC 1 None
HALT Enter power down mode 1 TO,PDF

Note: x: Immediate data

m: Data memory address


A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
(four system clocks).
(2)
: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3) (1)
: and (2)
(4)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared.
Otherwise the TO and PDF flags remain unchanged.

Rev. 1.30 26 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

Instruction Definition

ADC A,[m] Add data memory and carry to the accumulator


Description The contents of the specified data memory, accumulator and the carry flag are added si-
multaneously, leaving the result in the accumulator.
Operation ACC ¬ ACC+[m]+C
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ Ö Ö Ö Ö

ADCM A,[m] Add the accumulator and carry to data memory


Description The contents of the specified data memory, accumulator and the carry flag are added si-
multaneously, leaving the result in the specified data memory.
Operation [m] ¬ ACC+[m]+C
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ Ö Ö Ö Ö

ADD A,[m] Add data memory to the accumulator


Description The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation ACC ¬ ACC+[m]
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ Ö Ö Ö Ö

ADD A,x Add immediate data to the accumulator


Description The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.
Operation ACC ¬ ACC+x
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ Ö Ö Ö Ö

ADDM A,[m] Add the accumulator to the data memory


Description The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation [m] ¬ ACC+[m]
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ Ö Ö Ö Ö

Rev. 1.30 27 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

AND A,[m] Logical AND accumulator with data memory


Description Data in the accumulator and the specified data memory perform a bitwise logical_AND op-
eration. The result is stored in the accumulator.
Operation ACC ¬ ACC ²AND² [m]
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ Ö ¾ ¾

AND A,x Logical AND immediate data to the accumulator


Description Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.
Operation ACC ¬ ACC ²AND² x
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ Ö ¾ ¾

ANDM A,[m] Logical AND data memory with the accumulator


Description Data in the specified data memory and the accumulator perform a bitwise logical_AND op-
eration. The result is stored in the data memory.
Operation [m] ¬ ACC ²AND² [m]
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ Ö ¾ ¾

CALL addr Subroutine call


Description The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.
Operation Stack ¬ Program Counter+1
Program Counter ¬ addr
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

CLR [m] Clear data memory


Description The contents of the specified data memory are cleared to 0.
Operation [m] ¬ 00H
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

Rev. 1.30 28 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

CLR [m].i Clear bit of data memory


Description The bit i of the specified data memory is cleared to 0.
Operation [m].i ¬ 0
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

CLR WDT Clear Watchdog Timer


Description The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are
cleared.
Operation WDT ¬ 00H
PDF and TO ¬ 0
Affected flag(s)
TO PDF OV Z AC C
0 0 ¾ ¾ ¾ ¾

CLR WDT1 Preclear Watchdog Timer


Description Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction just sets the indicated flag which im-
plies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO PDF OV Z AC C
0* 0* ¾ ¾ ¾ ¾

CLR WDT2 Preclear Watchdog Timer


Description Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction, sets the indicated flag which im-
plies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO PDF OV Z AC C
0* 0* ¾ ¾ ¾ ¾

CPL [m] Complement data memory


Description Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation [m] ¬ [m]
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ Ö ¾ ¾

Rev. 1.30 29 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

CPLA [m] Complement data memory and place result in the accumulator
Description Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation ACC ¬ [m]
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ Ö ¾ ¾

DAA [m] Decimal-Adjust accumulator for addition


Description The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumu-
lator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD ad-
justment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.
Operation If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ Ö

DEC [m] Decrement data memory


Description Data in the specified data memory is decremented by 1.
Operation [m] ¬ [m]-1
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ Ö ¾ ¾

DECA [m] Decrement data memory and place result in the accumulator
Description Data in the specified data memory is decremented by 1, leaving the result in the accumula-
tor. The contents of the data memory remain unchanged.
Operation ACC ¬ [m]-1
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ Ö ¾ ¾

Rev. 1.30 30 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

HALT Enter power down mode


Description This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PDF) is set and the WDT time-out bit (TO) is cleared.
Operation Program Counter ¬ Program Counter+1
PDF ¬ 1
TO ¬ 0
Affected flag(s)
TO PDF OV Z AC C
0 1 ¾ ¾ ¾ ¾

INC [m] Increment data memory


Description Data in the specified data memory is incremented by 1
Operation [m] ¬ [m]+1
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ Ö ¾ ¾

INCA [m] Increment data memory and place result in the accumulator
Description Data in the specified data memory is incremented by 1, leaving the result in the accumula-
tor. The contents of the data memory remain unchanged.
Operation ACC ¬ [m]+1
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ Ö ¾ ¾

JMP addr Directly jump


Description The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.
Operation Program Counter ¬addr
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

MOV A,[m] Move data memory to the accumulator


Description The contents of the specified data memory are copied to the accumulator.
Operation ACC ¬ [m]
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

Rev. 1.30 31 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

MOV A,x Move immediate data to the accumulator


Description The 8-bit data specified by the code is loaded into the accumulator.
Operation ACC ¬ x
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

MOV [m],A Move the accumulator to data memory


Description The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation [m] ¬ACC
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

NOP No operation
Description No operation is performed. Execution continues with the next instruction.
Operation Program Counter ¬ Program Counter+1
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

OR A,[m] Logical OR accumulator with data memory


Description Data in the accumulator and the specified data memory (one of the data memories) per-
form a bitwise logical_OR operation. The result is stored in the accumulator.
Operation ACC ¬ ACC ²OR² [m]
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ Ö ¾ ¾

OR A,x Logical OR immediate data to the accumulator


Description Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.
Operation ACC ¬ ACC ²OR² x
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ Ö ¾ ¾

ORM A,[m] Logical OR data memory with the accumulator


Description Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.
Operation [m] ¬ACC ²OR² [m]
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ Ö ¾ ¾

Rev. 1.30 32 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

RET Return from subroutine


Description The program counter is restored from the stack. This is a 2-cycle instruction.
Operation Program Counter ¬ Stack
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

RET A,x Return and place immediate data in the accumulator


Description The program counter is restored from the stack and the accumulator loaded with the speci-
fied 8-bit immediate data.
Operation Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

RETI Return from interrupt


Description The program counter is restored from the stack, and interrupts are enabled by setting the
EMI bit. EMI is the enable master (global) interrupt bit.
Operation Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

RL [m] Rotate data memory left


Description The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
Operation [m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

RLA [m] Rotate data memory left and place result in the accumulator
Description Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

Rev. 1.30 33 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

RLC [m] Rotate data memory left through carry


Description The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 re-
places the carry bit; the original carry flag is rotated into the bit 0 position.
Operation [m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TO PDF OV Z AC C
¾ ¾ ¾ ¾ ¾ Ö

RLCA [m] Rotate left through carry and place result in the accumulator
Description Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TO PDF OV Z AC C
¾ ¾ ¾ ¾ ¾ Ö

RR [m] Rotate data memory right


Description The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
Operation [m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TO PDF OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾

RRA [m] Rotate right and place result in the accumulator


Description Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TO PDF OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾

RRC [m] Rotate data memory right through carry


Description The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation [m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
TO PDF OV Z AC C
¾ ¾ ¾ ¾ ¾ Ö

Rev. 1.30 34 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

RRCA [m] Rotate right through carry and place result in the accumulator
Description Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ Ö

SBC A,[m] Subtract data memory and carry from the accumulator
Description The contents of the specified data memory and the complement of the carry flag are sub-
tracted from the accumulator, leaving the result in the accumulator.
Operation ACC ¬ ACC+[m]+C
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ Ö Ö Ö Ö

SBCM A,[m] Subtract data memory and carry from the accumulator
Description The contents of the specified data memory and the complement of the carry flag are sub-
tracted from the accumulator, leaving the result in the data memory.
Operation [m] ¬ ACC+[m]+C
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ Ö Ö Ö Ö

SDZ [m] Skip if decrement data memory is 0


Description The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc-
tion (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

SDZA [m] Decrement data memory and place result in ACC, skip if 0
Description The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy-
cles). Otherwise proceed with the next instruction (1 cycle).
Operation Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

Rev. 1.30 35 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

SET [m] Set data memory


Description Each bit of the specified data memory is set to 1.
Operation [m] ¬ FFH
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

SET [m]. i Set bit of data memory


Description Bit i of the specified data memory is set to 1.
Operation [m].i ¬ 1
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

SIZ [m] Skip if increment data memory is 0


Description The contents of the specified data memory are incremented by 1. If the result is 0, the fol-
lowing instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).
Operation Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

SIZA [m] Increment data memory and place result in ACC, skip if 0
Description The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory re-
mains unchanged. If the result is 0, the following instruction, fetched during the current in-
struction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

SNZ [m].i Skip if bit i of the data memory is not 0


Description If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Other-
wise proceed with the next instruction (1 cycle).
Operation Skip if [m].i¹0
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

Rev. 1.30 36 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

SUB A,[m] Subtract data memory from the accumulator


Description The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.
Operation ACC ¬ ACC+[m]+1
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ Ö Ö Ö Ö

SUBM A,[m] Subtract data memory from the accumulator


Description The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.
Operation [m] ¬ ACC+[m]+1
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ Ö Ö Ö Ö

SUB A,x Subtract immediate data from the accumulator


Description The immediate data specified by the code is subtracted from the contents of the accumula-
tor, leaving the result in the accumulator.
Operation ACC ¬ ACC+x+1
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ Ö Ö Ö Ö

SWAP [m] Swap nibbles within the data memory


Description The low-order and high-order nibbles of the specified data memory (1 of the data memo-
ries) are interchanged.
Operation [m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

SWAPA [m] Swap data memory and place result in the accumulator
Description The low-order and high-order nibbles of the specified data memory are interchanged, writ-
ing the result to the accumulator. The contents of the data memory remain unchanged.
Operation ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

Rev. 1.30 37 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

SZ [m] Skip if data memory is 0


Description If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation Skip if [m]=0
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

SZA [m] Move data memory to ACC, skip if 0


Description The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation Skip if [m]=0
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

SZ [m].i Skip if bit i of the data memory is 0


Description If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc-
tion (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation Skip if [m].i=0
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

TABRDC [m] Move the ROM code (current page) to TBLH and data memory
Description The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation [m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

TABRDL [m] Move the ROM code (last page) to TBLH and data memory
Description The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Operation [m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

Rev. 1.30 38 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

XOR A,[m] Logical XOR accumulator with data memory


Description Data in the accumulator and the indicated data memory perform a bitwise logical Exclu-
sive_OR operation and the result is stored in the accumulator.
Operation ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ Ö ¾ ¾

XORM A,[m] Logical XOR data memory with the accumulator


Description Data in the indicated data memory and the accumulator perform a bitwise logical Exclu-
sive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation [m] ¬ ACC ²XOR² [m]
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ Ö ¾ ¾

XOR A,x Logical XOR immediate data to the accumulator


Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op-
eration. The result is stored in the accumulator. The 0 flag is affected.
Operation ACC ¬ ACC ²XOR² x
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ Ö ¾ ¾

Rev. 1.30 39 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

Package Information
18-pin DIP (300mil) Outline Dimensions

1 8 1 0
B
1 9

D
a
E G I
F

Dimensions in mil
Symbol
Min. Nom. Max.
A 895 ¾ 915
B 240 ¾ 260
C 125 ¾ 135
D 125 ¾ 145
E 16 ¾ 20
F 50 ¾ 70
G ¾ 100 ¾
H 295 ¾ 315
I 335 ¾ 375
a 0° ¾ 15°

Rev. 1.30 40 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

18-pin SOP (300mil) Outline Dimensions

1 8 1 0

A B

1 9

C '
G
D H

E F a

Dimensions in mil
Symbol
Min. Nom. Max.
A 394 ¾ 419
B 290 ¾ 300
C 14 ¾ 20
C¢ 447 ¾ 460
D 92 ¾ 104
E ¾ 50 ¾
F 4 ¾ ¾
G 32 ¾ 38
H 4 ¾ 12
a 0° ¾ 10°

Rev. 1.30 41 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

20-pin SSOP (150mil) Outline Dimensions

2 0 1 1

A B

1 1 0

C '
G
D H

E F a

Dimensions in mil
Symbol
Min. Nom. Max.
A 228 ¾ 244
B 150 ¾ 158
C 8 ¾ 12
C¢ 335 ¾ 347
D 49 ¾ 65
E ¾ 25 ¾
F 4 ¾ 10
G 15 ¾ 50
H 7 ¾ 10
a 0° ¾ 8°

Rev. 1.30 42 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

Product Tape and Reel Specifications


Reel Dimensions

D
T 2

A B C

T 1

SOP 18W

Symbol Description Dimensions in mm


A Reel Outer Diameter 330±1.0
B Reel Inner Diameter 62±1.5
13.0+0.5
C Spindle Hole Diameter
-0.2
D Key Slit Width 2.0±0.5
24.8+0.3
T1 Space Between Flange
-0.2
T2 Reel Thickness 30.2±0.2

SSOP 20S (150mil)

Symbol Description Dimensions in mm


A Reel Outer Diameter 330±1.0
B Reel Inner Diameter 62±1.5
13.0+0.5
C Spindle Hole Diameter
-0.2
D Key Slit Width 2.0±0.5
16.8+0.3
T1 Space Between Flange
-0.2
T2 Reel Thickness 22.2±0.2

Rev. 1.30 43 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

Carrier Tape Dimensions

P 0 P 1
D t

F
W
B 0
C

D 1 P
K 0

A 0

SOP 18W

Symbol Description Dimensions in mm


24.0+0.3
W Carrier Tape Width
-0.1
P Cavity Pitch 16.0±0.1
E Perforation Position 1.75±0.1
F Cavity to Perforation (Width Direction) 11.5±0.1
D Perforation Diameter 1.5±0.1
D1 Cavity Hole Diameter 1.5+0.25
P0 Perforation Pitch 4.0±0.1
P1 Cavity to Perforation (Length Direction) 2.0±0.1
A0 Cavity Length 10.9±0.1
B0 Cavity Width 12.0±0.1
K0 Cavity Depth 2.8±0.1
t Carrier Tape Thickness 0.3±0.05
C Cover Tape Width 21.3

SSOP 20S (150mil)

Symbol Description Dimensions in mm


16.0+0.3
W Carrier Tape Width
-0.1
P Cavity Pitch 8.0±0.1
E Perforation Position 1.75±0.1
F Cavity to Perforation (Width Direction) 7.5±0.1
D Perforation Diameter 1.5+0.1
D1 Cavity Hole Diameter 1.5+0.25
P0 Perforation Pitch 4.0±0.1
P1 Cavity to Perforation (Length Direction) 2.0±0.1
A0 Cavity Length 6.5±0.1
B0 Cavity Width 9.0±0.1
K0 Cavity Depth 2.3±0.1
t Carrier Tape Thickness 0.30±0.05
C Cover Tape Width 13.3

Rev. 1.30 44 July 26, 2005


HT46R46/HT46C46/HT46R47/HT46C47

Holtek Semiconductor Inc. (Headquarters)


No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw

Holtek Semiconductor Inc. (Taipei Sales Office)


4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)

Holtek Semiconductor Inc. (Shanghai Sales Office)


7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233
Tel: 021-6485-5560
Fax: 021-6485-0313
http://www.holtek.com.cn

Holtek Semiconductor Inc. (Shenzhen Sales Office)


5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District,
Shenzhen, China 518057
Tel: 0755-8616-9908, 8616-9308
Fax: 0755-8616-9533

Holtek Semiconductor Inc. (Beijing Sales Office)


Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031
Tel: 010-6641-0030, 6641-7751, 6641-7752
Fax: 010-6641-0125

Holtek Semiconductor Inc. (Chengdu Sales Office)


709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016
Tel: 028-6653-6590
Fax: 028-6653-6591

Holmate Semiconductor, Inc. (North America Sales Office)


46729 Fremont Blvd., Fremont, CA 94538
Tel: 510-252-9880
Fax: 510-252-9885
http://www.holmate.com

Copyright Ó 2005 by HOLTEK SEMICONDUCTOR INC.


The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-
sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.

Rev. 1.30 45 July 26, 2005

Potrebbero piacerti anche