Memory and Programmable
Random-Access Memory
Logic Devices
A memory unit is a collection of cells capable of
storing a large quantity of binary information.
There are two types of memories that are used in
digital systems:
ƒ Random-Access Memory (RAM): Accepts
new data for storage to be available later for
use. RAM can perform both write and read
operations. A RAM loses its stored data when
power is turned off, thus it is a volatile memory.
ƒ Read-Only Memory (ROM): Cannot have its
contents changed during normal operation. Its
contents are determined either at the time of
manufacture or during a special write mode. A
ROM retains stored data even if power is
switched off, thus it is a non-volatile memory.
The ROM is an example of a programmable logic
device. Other such units are the programmable
logic array (PLA), the programmable array logic
(PAL), and the field-programmable gate array
(FPGA). Programming of these devices involves
blowing fuses at specified locations.
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Each word in memory is assigned an identification
number, called an address (0 up to 2k-1). The
selection of a specific word inside the memory is
done by applying the k-bit address to the address
lines. A decoder accepts this address and opens
the paths needed to select the word specified.
Memories vary greatly in size and may range from
1024 words, requiring an address of 10 bits. To 232
word requiring 32 address bits.
The possible content of the first three and the last
three words in a 1024 x 16 memory (2K bytes) are:
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1.
The time it takes to transfer information to or from
any desired random location is always the same,
hence, the name random-access memory (RAM).
A memory unit stores binary information in groups
of bits called words. A group of eight bits is called
a byte. The capacity of a memory unit is usually
stated as the total number of bytes it can store.
A block diagram of the memory unit is:
The n data input lines provide the information to
be stored in memory and the n output lines specify
the binary data coming out of the memory. The k
address lines specify the particular word chosen.
The two control inputs specify the direction of data
transfer required.
1.1 Write and Read Operations
The steps that must be taken for the purpose of
transferring a new word to be stored into memory
are as follows:
1. Apply the binary address of the desired word
to the address lines.
2. Apply the data bits that must be stored in
memory to the data input lines.
3. Activate the write input.
The steps that must be taken for the purpose of
transferring a stored word out of memory are as
follows:
1. Apply the binary address of the desired word
to the address lines.
2. Activate the read input.
Some memory chips have a different configuration
of control inputs; one input selects the unit and the
other decides the operation. The operations that
result from these control inputs are:
1.2 Timing Waveforms
The operation of a memory is usually controlled by
the CPU. The access time of a memory is the time
required to select a word and read it. The cycle
time of a memory is the time required to complete
a write operation. The access time and cycle time
must be within a time equal to a fixed number of
CPU clock cycles. The memory timing below is for
a CPU with 50MHz clock and memory with 50ns
cycle time:
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2. RAM Memory Decoding
In addition to the storage elements in a memory
unit, there is a need for decoding circuits to select
the memory word specified by the input address.
2.1 Internal Construction
The internal construction of a RAM of m words
and n bits per word consists of m x n binary
storage cells and associated decoding circuits for
selecting individual words. The binary storage cell
is the basic building block of a memory unit. The
logic of a binary cell (BC) that stores one bit of
information is shown below:
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1.3 Types of RAM
Integrated circuit RAM units are available in two
possible operating modes:
ƒ Static RAM (SRAM): Consists essentially of
internal latches that store the binary data. The
stored information remains valid as long as
power is applied to the unit.
ƒ Dynamic RAM (DRAM): Stores the binary data
in the form of electric charges on capacitors.
The capacitors are provided inside the chip by
MOS transistors. The stored charge on the
capacitor tends to discharge with time and the
capacitors must be periodically recharged by
refreshing the DRAM. Refreshing is done by
cycling through the words every 2 to 10ms to
restore the decaying charge. DRAM is also a
volatile memory.
DRAM offers reduced power consumption and
larger storage capacity in a single memory chip.
SRAM is easier to use and has shorter read and
write cycles.
The logical realization of a small 4 x 4 RAM is:
The decoder is enabled with the memory enable
input. Once a word is selected, the Read/Write
input determines the operation. During the read
operation, the four bits of the selected word go
through OR gates to the output terminals. During
the write operation, the data available in the input
lines are transferred into the four binary cells of the
selected word.
2.2 Coincident Decoding 2.3 Address Multiplexing

A decoder with k inputs and 2k outputs requires 2k
AND gates with k inputs per gate. The number of
gates and the number of inputs per stage can be
reduced by employing two decoders in a two-
dimensional selection scheme. In this scheme,
two k/2-input decoders are used instead of one k-
input decoder. One decoder performs the row
selection and the other the column selection. This
technique is demonstrated below for a 1K-word
memory:
DRAM is the preferred technology for large
memories. To reduce the number of pins in the IC
package, designers utilize address multiplexing;
one set of address input pins accommodates the
address components. The idea is demonstrated in
a 64K-word memory:

The address strobes (RAS and CAS) are included

for enabling the row and column address into their
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respective registers. 10

Each parity bit is calculated as follows:

3. Error Detection and Correction
Occasional errors appear in storing and retrieving
the binary data. The reliability of a memory unit
may be improved by employing error detecting
and correcting codes.
The most common error-detection is the parity bit. So the 12-bit code word stored in memory is:
A parity bit is generated and stored along with the
data word in memory. The data word is accepted if
the parity of the bits read out is correct.
An error-correcting code generates multiple parity When the 12 bits are read from memory, they are
check bits that are stored with the data word in checked again for possible errors. The read parity
memory. One of the most common codes used bits are checked over the same combination of bits
with RAMs is the Hamming code. including the parity bit. The four check bits are
evaluated as follows:
3.1 Hamming Code (n + k, n)
In the Hamming code, k parity bits are added to an
n-bit data word, forming a code word of n + k bits.
In the code word, those positions numbered as a
power of 2 are reserved for the parity bits.
A 0 check bit designates an even parity over the
Suppose that four parity bits are added to the 8-bit
checked bits and a 1 designates an odd parity. The
word 11000100:
result C = C8C4C2C1 = 0000, indicates that no error
has occurred.

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Consider the following three cases:
By evaluating the XOR of the corresponding bits,
the four check bits are determined as follows:
The error can be corrected by complementing the
corresponding bit. Note that an error can occur in
the data word or in one of the parity bits.
The Hamming code can be used for data words of
any length. Ranges of n for various values of k are
tabulated below:
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4. Read-Only Memory
A read-only memory (ROM) is a memory in which
permanent binary information is stored. A block
diagram of a ROM is shown below:
The inputs give the address for the memory and
the outputs give the data bits of the stored word
selected. ROM chips also have enable inputs.
Consider the following 32 X 8 ROM:
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3.2 Single-Error Correction, Double-Error
Detection
The Hamming code can detect and correct only a
single error. By adding of another parity bit to the
code word, the hamming code can be used to
correct a single error and detect double errors.
With an additional parity bit, the previous 12-bit
code word becomes:
001110010100P13
where P13 is evaluated from the XOR of the other
12 bits. The resulting code word is:
0011100101001 (even parity)
When the word is read from memory, the check
bits are evaluated and also the parity over the
entire 13-bits. The following four cases can occur:
ƒ If C = 0 and P = 0, no error occurred
ƒ If C ≠ 0 and P = 1, a single error occurred that
can be corrected
ƒ If C ≠ 0 and P = 0, a double error occurred that
is detected but cannot be corrected
ƒ If C = 0 and P = 1, an error occurred in the P13
bit.
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The 256 interconnections are programmable. For
example, the partial content of a 32 x 8 ROM may
be specified by the following truth table:
hardware procedure that programs the ROM
results in blowing fuse links according to a given
truth table. The above truth table results in:
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4.1 Combinational Circuit Implementation Only outputs B3 – B6 need be generated with a
ROM; the other two are readily obtained. The ROM
The programmed ROM shown previously may be required must be of size 8 X 4.
considered as a combinational circuit with eight
The ROM realization is shown below:
outputs, each being a function of five input
variables. E.g., output A7 can be expressed in sum
of minterms as:

A7 (I 4 , I3 , I2 , I1, I0 ) = ∑ (0, 2, 3,..., 29)

Example: Design a combinational circuit using a

ROM. The circuit accepts a 3-bit number and
generates an output binary number equal to the
square of the input number.
The following truth table specifies the information
Solution: needed for programming the ROM:
The first step is to generate the truth table of the
combinational circuit:

Note that when implementing Boolean functions

with a ROM, minimisations are not necessary.
Boolean functions are realized as sum of P-terms.
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4.2 Types of ROMs 4.3 Combinational PLDs

There are three main types or ROMs and they
differ in the way they are programmed:
ƒ Mask ROM: Contents programmed at factory
according to the desired specification, and no
changes are possible afterwards. This type is
uneconomical for small quantities because the
vendor charges the customer a special fee for
custom masking the particular ROM.
The PROM is a combinational programmable logic
device (PLD). A combinational PLD is an IC with
programmable gates divided into an AND array
and an OR array to provide an AND-OR sum-of-
product implementation.
There are three major types of combinational
PLDs and they differ in the placement of the
programmable connections in the AND-OR array:

ƒ PROM: User programmable using a PROM

programmer. Once programmed the contents
can not be changed. The factory settings are
all 1’s and the user sets specified bits to 0’s by
blowing up fusible links. Fairly economical for
small quantities.
ƒ EPROM: User programmable and erasable by
means of ultraviolet radiation (UV EPROM) or
electrical pulses (EEPROM). It use an n-MOS
memory array with isolated-gate structure. The
isolated gate has no electrical connections and
can store electrical charge for indefinite
periods of time. Erasure of data bits is done by
removing the gate charge.

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5. Programmable Logic Array
Consists programmable AND and OR arrays and
output XOR gates (controllable inverters). The
internal logic of a PLA with three inputs and two
outputs is shown below:
The particular Boolean functions implemented are:
F1 = AB′ + AC + A′BC ′
F2 = ( AC + BC )′
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Example: Implement the following Boolean
functions with a PLA:
F1( A, B, C ) = ∑ (0, 1, 2, 4)
F2 ( A, B, C ) = ∑ (0, 5, 6, 7)
Solution:
Both the true and complement of the functions are
simplified in the following two K-maps.
The combination that gives the minimum number
of product terms is:
F1 = ( AB + AC + BC )′
F2 = AB + AC + A′B′C ′
The PLA programming table for this combination
is:
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The fuse map of a PLA may be specified in a
tabular form. For example, the programming table
that specifies the PLA shown previously is:
The first section list the product terms numerically.
The second section specifies the required paths
between inputs and AND gates. The third section
specifies the paths between the AND and OR
gates. The product terms listed on the left are
included for reference only.
As with a ROM, the PLA may be mask or field
programmable.
When implementing a combinational circuit with a
PLA, care must be taken to reduce the number of
distinct product terms, since a PLA has a finite
number of AND gates. This can be done by
simplifying each Boolean function (both the true
and complement).
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Note that output F1 is the true output even though a
C is marked over it in the table. This is because F1
is generated with an AND-OR circuit. The XOR
gate complements the function to produce the true
F1 output.
A typical PLA has a large number of inputs and
product terms. In such cases, minimisation is done
using computer-assisted simplification procedures.
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 Consider the following Boolean functions:
6. Programmable Array Logic
w ( A, B, C, D ) = ∑ (2, 12, 13 )
The PLA is a device with a fixed OR array and a x ( A, B, C, D ) = ∑ (7, 8, 9, 10, 11, 12, 13, 14, 15 )
programmable AND array. Unlike a PLA, a product
term cannot be shared amongst two or more OR y ( A, B, C, D ) = ∑ (0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15 )
gates. Thus, no optimum solutions are required as w ( A, B, C, D ) = ∑ (1, 2, 8, 12, 13 )
would be the case for PLA implementations.
The simplified Boolean functions are:
The logic configuration of a typical PAL is:
w = ABC ′ + A′B′CD′
x = A + BCD
y = A′B + CD + B′D′
z = ABC ′ + A′B′CD′ + AC ′D′ + A′B′C ′D
= w + AC ′D′ + A′B′C ′D

The resulting PLA programming table is:

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The logic diagram of the programmed PAL is:

7. Sequential Programmable Devices
Sequential PLDs include both gates and flip-flops.
In this way, the device can be programmed to
perform a variety of sequential-circuit functions.
Three major types are:

ƒ Sequential programmable logic device (SPLD)

ƒ Complex programmable logic device (CPLD)
ƒ Field programmable gate array (FPGA)

SPLD includes flip-flops within the IC chip in

addition to the AND-OR array. The result is a
sequential circuit as shown below:

The circuit outputs can be taken from the OR

gates or from the outputs of the flip-flops. The flip-
flops may be of the D or JK type.
The first SPLD was the field-programmable logic
sequencer (FPLS). It was not a great commercial
success because it has too many programmable
connections.
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The configuration mostly used for SPLD is the PAL
together with D flip-flops. Each section of a SPLD
is called a macrocell:
The flip-flop is connected to a common clock input.
The output of the clock is connected to a three-
stage buffer controlled by a common output enable
OE signal. A typical SPLD has from 8 to 10
macrocells within one IC package.
Extra programming features of a macrocell include:
ƒ Ability to bypass the flip-flop
ƒ Selection of clock-edge polarity
ƒ Selection of true or complement output
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For large digital designs, it is more economical to
use a complex PLD (CPLD) IC chip:
Each input/output (IO) pin is driven by a three-
stage buffer and can be programmed to act as
input or output. Each PLD typically contains 8 to 16
macrocells.
For very complex designs an FPGA may be used.
A typical FPGA consists of look-up tables, gates,
multiplexers, and flip-flops.
The design with PLD, CPLD and FPGA requires
extensive CAD tools to facilitate the synthesis
procedure. A variety of tools are available such as
schematic entry and hardware description
languages (HDL) such as ABEL, VHDL and
Verilog.
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