FinFET and other New

Transistor Technologies

Chenming Hu
Univ. of California

Chenming Hu, July 2011

May 4 2011 NY Times Front Page
NY Times news article:
• Intel will use 3D FinFET for 22nm
• Most radical change in decades
• There is a competing SOI technology

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Chenming Hu, July 2011
 Other Background Info
• TSMC, IBM…new transistors soon
• Since 2001 ITRS shows FinFET and
ultra-thin-body UTB-SOI as the two
successor MOSFETs
• SOITEC UTB-SOI recently available
• IBM 2009 5nm UTB SOI paper

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Chenming Hu, July 2011
New MOSFET Structures

Cylindrical FET

Ultra Thin Body SOI

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Chenming Hu, July 2011
Good Old MOSFET Nearing Limits
Vt, S (swing) and Ioff
are sensitive to Lg &
dopant variations.

• high design cost

• high Vdd, hence
high power usage

Finally painful enough for change.

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Chenming Hu, July 2011
 Power Consumption Problems
1.Not just a chip and package thermal
issue.
2.ICs use a few % of world’s electricity
today and
• Power per chip is growing.
• IC units in use also growing.
3.If power consumption is not reduced,
industry future growth is at risk.

Chenming Hu, July 2011

 Want Low Vt and Low Ioff

Need smaller
S and less
variations of
S and Vt

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Chenming Hu, July 2011
 How Vt Variation & S Got So Bad
MOSFET becomes “resistor” at very
small L –- Drain competes with Gate to
control the channel barrier.
Drain Current, IDS (A/µm)

10-3
L
Gate
Gate
10-5
Cg Insulator
10-7 Smaller
Size
Source Drain
size
shrink
10-9
or larger Vd Cd
10-11
0.0 0.3 0.6 0.9
Gate Voltage, VGS (V)
Chenming Hu, July 2011
Reducing EOT is Not Enough
Gate

Source Drain

Leakage Path

Gate cannot control the

leakage current paths
that are far from the gate.

Chenming Hu, July 2011

One of Two Ways to Better Vt and S
The gate controls a thin body from
more than one side. Gate Length

Source
Gate

Source Drain
Gate

Drain
Fin Height
FinFET body is a  Fin Width
thin fin N. Lindert et al., DRC paper II.A.6, 2001

Chenming Hu, July 2011

 FinFET- 1999
Undoped Body. 30nm etched thin fin.
Vt set with gate work-function (SiGe).
0.6
Vt at 100 nA/μm, Vd = 0.05 V
0.4

0.2

ΔVt [V]
0.0

-0.2

-0.4
Fin width: 20 nm
-0.6
0 10 20 30 40 50
Lg [nm]

X. Huang et al., IEDM, p. 67, 1999

Chenming Hu, July 2011

State-of-the-Art FinFET on Buk Si
20nm Hi Perf
C.C. Wu et al.,
Gate 2010 IEDM

STI Si
STI

28nm SoC
C.C. Yeh et al.,
2010 IEDM

Chenming Hu, July 2011

 FinFET is “Easy” to Scale
10nm Lg AMD 5nm Lg TSMC 3nm Lg KAIST
2002 IEDM 2004 VLSI Symp 2006 VLSI Symp

Lg =
5 nm

because leakage is well suppressed if

Fin thickness =or< Lg
• Thin fin can be made with the same Lg
patterning/etching tools.
Chenming Hu, July 2011
 Second Way to Better Vt and S
Ultra-thin-body SOI (UTB-SOI) 
No leakage path far from the gate.
1.E-02

Drain Current [A/um]

Gate 1.E-04

Source UTB Drain 1.E-06

SiO2 1.E-08 Tsi=8nm
Tsi=6nm
Si 1.E-10 Tsi=4nm

1.E-12
0 0.2 0.4 0.6 0.8 1
Y-K. Choi, IEEE EDL, p. 254, 2000
Gate Voltage [V]

Chenming Hu, July 2011

Most Leakage Flows >5nm Below Surface

Y-K. Choi et al., IEEE Electron Device Letters, p. 254, 2000

Chenming Hu, July 2011
 Silicon Body Needs to be <Lg/3
For good swing and device variation

Y-K. Choi et al., IEEE Electron Device Letters, p. 254, 2000

Chenming Hu, July 2011
 UTB-SOI
3nm Silicon Body, Raised S/D

Y-K. Choi et al, VLSI Tech. Symposium, p. 19, 2001

Chenming Hu, July 2011
State-of-the-Art 5nm
Thin-Body SOI

ETSOI, IBM
K. Cheng et al, IEDM, 2009

Chenming Hu, July 2011

 Both Thin-Body Transistors Provide
• Better swing.
• S & Vt less sensitive to Lg and Vd.
• No random dopant fluctuation.
• No impurity scattering.
• Less surface scattering (lower Eeff).

•Higher on-current and lower leakage

•Lower Vdd and power consumption
•Further scaling and lower cost
Chenming Hu, July 2011
 Back-Gate Bias Option
UTB-SOI FinFET

Gate 1
Gate 2

Si

STI
STI

Chenming Hu, July 2011

 Similarities
• 1996: UC Berkeley proposed to DARPA two
“25nm Transistors”. Both of them
•use body thickness as a new scaling parameter
•can use undoped body for high µ and no RDF
• 1999: demonstrated FinFET
2000: demonstrated UTB-SOI (Ultra-Thin Body)
• Since 2001: ITRS highlights FinFET and UTBSOI
• Now: Intel will use Trigate FinFET.
Soitec readies +-0.5nm substrates for UTBSOI
• Both FinFET & UTBSOI better than planar bulk!
Chenming Hu, July 2011
 Main Differences
• FinFET body thickness ~ Lg. Investment by fabs
UTBSOI thickness ~1/3 Lg. Investment by Soitec
• FinFET has clear long term scalability. UTBSOI
may be ready sooner depending on each firm’s
readiness with FinFET.
• FinFET has larger Ion or can use lower Vdd.
UTBSOI has a good back-gate bias option.
UTBSOI
Gate 1 Gate 2
Si
STI
FinFET STI
Chenming Hu, July 2011
 What May Happen
• FinFET will be used at 22nm by Intel and later
by more firms through and beyond 10nm.
• Some firms may use UTBSOI to gain/protect
market at 20 or 18nm if FinFET is not option.
If so, competition between FinFET and UTBSOI
will bring out the best of both.
If not----- back to first bullet.

Chenming Hu, July 2011

Chenming Hu, July 2011
 FinFET BSIM Compact Model Verified
FinFET Fabricated at TSMC.
Lg = 30 nm-10um

50µ Id-Vg 1m Ibulk Id-Vd

Lg = 50nm Lg = 50nm 50 Lg = 50nm

Drain Current (µA)

Vg = 1.2 - 0.4V
Drain Current (A)

1µ Bulk Current (A)

100p
Vd = 50mV Vd = 1.2V Id-Vd
25µ
25
Vd = 1.2V 1n 10p

0 1p 1p
0.0 0.4 0.8 1.2 0.0 0.4 0.8 1.2 0
0.0 0.4 0.8 1.2
Gate Voltage (V)
Gate Voltage (V) Drain Voltage (V)
M. Dunga, 2008 VLSI Tech Sym
Chenming Hu, July 2011
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Chenming Hu, July 2011
 Reduce C

f ⋅ C ⋅Vdd
2

Reduce all capacitances.

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Chenming Hu, July 2011
Vacuum-Sheath Interconnect

 CTOTAL ∝ Delay, CM ∝ Crosstalk Noise

Load Capacitance : CO
Dielectric Beam

Etch Stop layer Mutual Capacitance : CM

Metal
Total Capacitance : CTOTAL

J. Park, Electronics Letters, p. 1294, 2009

Chenming Hu, July 2011

Effective k of Vacuum-Sheath
Interconnects
2.25
1.3
Beam Dielectric Constant

1.4
1.5
1.6
2.9
1.7
1.8
1.9
2.0
3.3
2.1
2.3 2.2
2.4 No Solution
3.6 2.5
No Solution
2.6

3.9
20 30 40 50 60 70 80
Air Percentage (%)

J. Park, Electronics Letters, p. 1294, 2009

Chenming Hu, July 2011
Vacuum Spacer to Reduce CGC

 CGOX : Gate Oxide Capacitance

 CGC : Gate-to-Contact Capacitance

CGOX » CGC CGOX < CGC

Contacts

Gate

Scale Down

Chenming Hu, July 2011

Vacuum Spacer Self-Aligned Contact
20nm MOSFET comparison

Vacuum
Spacer
Oxide
Self-
Spacer
aligned
Vacuum contact
Oxide (SAC)
Inverter 6.15 5.05
Delay, ps (1) (0.82)
Inverter
24.2 18.8
switching
(1) (0.78)
energy, fJ
Relative
1 0.7
Area

J. Park, IEEE EDL, p.1368, 2009

Chenming Hu, July 2011

Future Low Voltage Green Transistor

S<60mV/dec
Log Drain Current Id
S>60mV/dec

Gate Voltage Vg

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Chenming Hu, July 2011
 How to reduce Vdd to 0.15V?

1.Reduce Vdd – Vt to < 0.1V with high-

mobility-channel material, or sub-
threshold circuits.

2. Reduce Vt to 50mV. Need a device

that is free of the 60mV/decade
turn-off limit.

Chenming Hu, July 2011

 Origin of the 60mV/decade Limit
VG

COX
A potential
barrier controls Ec
the electron flow. Ev
Source Channel Drain

Leakage current is determined by Boltzmann

distribution or 60 mV/decade, limiting MOSFET, bipolar,
graphene MOSFET…
So, let electrons go through, not over, the
energy barrier  semiconductor tunneling
or MEMS
Chenming Hu, July 2011
 Semiconductor Band-to-Band Tunneling:
EC generating electron/hole pairs
EV
N+ P- N+

A known mechanism of leakage current since

1985.
Called Gate Induce Drain Leakage (GIDL).
J. Chen, P. Ko, C. Hu, IEDM 1985

Chenming Hu, July 2011

 Green Transistor --Simulation
P+ Pocket G C. Hu, 2008 VLSI-TSA, p.14, April, 2008

S N+ N-
- P+ D

Buried Oxide

P+ Gate
Pocket
Hole flow

Electronband
Energy flow diagram P+ Drain
N+ Source

Simulated carrier generation rates

Abrupt turn-on due to over-lap of valence/conduction

bands; adjustable turn-on voltage.
C. Hu, 2008 VLSI-TSA, p.14, April, 2008
Chenming Hu, July 2011
 Reduce Vdd by Reducing Eg
Simulated impact of Eg scaling
1E-02 Eg=0.36eV, Vdd=0.2V, EOT=5 Å, CV/I=0.42pS
1E-03
1E-04
1E-05
IDS (µ/µm)

1E-06
Eg=0.69eV, Vdd=0.5V, EOT=7 Å, CV/I=2.2pS
1E-07
1E-08 Eg=1.1eV, Vdd=1V, EOT=10 Å, CV/I=4.2pS
1E-09 Eg=0.36eV

1E-10 Eg=0.69eV
Eg=1.1eV Lg=40nm
1E-11
0.0 0.2 0.4 0.6 0.8 1.0

Gate Voltage, VGS (V)

Vdd scales down faster than Eg.

C. Hu, 2008 VLSI-TSA, p.14, April, 2008
Chenming Hu, July 2011
Simulated gFET Inverter VTC
Good voltage gain at 0.1V
200
VDD: 0.2 V
VDD: 0.15 V
150
VDD: 0.1 V
Output Voltage, VOUT (mV)

100

50

0
0 50 100 150 200
Input Voltage, VIN (mV)

C. Hu, 2008 VLSI-TSA, p.14, April, 2008

Chenming Hu, July 2011
 Hetero-junction gFET
• Strained Si on Ge has 0.18eV “effective
tunneling Eg”.
• III-V.
Gate EC
~ ~
P+ Source N+ Drain EC offset
EV
Si

Gate Oxide
Gate

Ge Substrate Ge tFET
~ ~ Si-Ge HtFET

Si Ge

A. Bowonder, Intern’l Workshop Junction Tech., 2008

Chenming Hu, July 2011

 Summary
• FinFET and UTB-SOI are viable new
sub-22nm transistors.
• Different performances, investment
costs, wafer costs, scaling barriers.
• Their BSIM SPICE models are
available – free 
• Capacitance and tunnel gFET are
potential opportunities.
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Chenming Hu, July 2011