University of Bahrain

College of Information Technology

Department of Computer Engineering

ITCE362: Computer Architecture

Experiment No. 5
VHDL design of a Simple General Purpose Processor

Name: Halima Mohamed Ismail Alturabi

ID: 20133684
Sec NO:1
Date of submission: \ \
Objective:
The aim of this experiment is to design and construct a simple Processor (CPU) using VHDL and to test its
functionality.

Introduction:

A central processing unit (CPU) is the physical component within a computer that is responsible of executing
the instructions of a computer program. A computer would have at least one CPU which is usually divided
into a control unit, buses, temporary storages, and an ALU. Control Units fetch the signals/instructions,
while the bus is used to provide an access to the data, and the ALU to perform actual arithmetic and logical
operations. Finally a temporary storage unit such as register files or latches is used to provide an easy access
to data within the CPU.

In this laboratory students will develop and test a processor with all the previously specified components.

Equipments Required:

 Xilinx ISE 6.1 i

 ModelSim XE II

Procedure and results:

Problem Statement:

Design a General Purpose Processor with the following specifications:

 ALU: has two 8-bits inputs for the operands (user provided), one 8-bits input selector that
selects the operation to be performed, and one 8-bits output for the result. The operation
of the ALU is clocked. Table1 illustrates the functionality of this circuit (Hint: Refer to
Experiment 1).
 Control Unit: consists of a synchronous up-counter synchronized with the clock and used
in conjunction with a decoder to generate a different bit pattern for each of the ALU
functions. For example, when the counter value equals 1, the first bit of the decoder (bit(0))
should be active which in turn drives the add function of the ALU, whereas when the
counter equals 2 the second bit of the decoder should be active to drive the second
function of the ALU and so on. Table 1 illustrates this.
 Storage Units: two strobed latches will be used to provide a temporary storage for the
input values for 8-bit A and B.
 Counter
Decoder Operation
value
1 00000001 AND
2 00000010 OR
3 00000100 XOR
4 00001000 NOR
5 00010000 NOT
6 00100000 ADD
7 01000000 SUB
8 10000000 NEG

Table 1: ALU instructions

For Additional Details, refer to Figure 1 below:

Procedure:
1. Write the VHDL code for the above circuit.
Hint: Use Components to write the code for individual elements of the circuits then connect them all
in a single design.
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are

-- provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;

entity Fdesign is

port(a:in std_logic_vector (7 downto 0);

b:in std_logic_vector (7 downto 0);

strobe_a : in std_logic;

strobe_b : in std_logic;

z:out std_logic_vector (7 downto 0);

clk,rst : in std_logic);

end Fdesign;

architecture Behavioral of Fdesign is

component Storage_Unit is

Port ( input : in STD_LOGIC_VECTOR (7 downto 0);

strobe : in STD_LOGIC;

q : out STD_LOGIC_VECTOR (7 downto 0));

end component;

component ALU is

Port ( a : in STD_LOGIC_VECTOR (7 downto 0);

b : in STD_LOGIC_VECTOR (7 downto 0);

op : in STD_LOGIC_VECTOR (7 downto 0);

clk : in STD_LOGIC;

aluo : out STD_LOGIC_VECTOR (7 downto 0));

end component;

component Decoder is

Port ( reset : in STD_LOGIC;

clk : in STD_LOGIC;

q : out STD_LOGIC_VECTOR (7 downto 0));

end component;
signal q0,q1,q2 : std_logic_vector (7 downto 0);

begin

u0: Storage_Unit port map (a, strobe_a, q0);

u1: Storage_Unit port map (b, strobe_b, q1);

u2: Decoder port map (rst, clk, q2);

u3: ALU port map (q0, q1, q2, clk, z);

end Behavioral;

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are

-- provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;

entity ALU is

Port ( a : in STD_LOGIC_VECTOR (7 downto 0);

b : in STD_LOGIC_VECTOR (7 downto 0);

op : in STD_LOGIC_VECTOR (7 downto 0);

clk : in STD_LOGIC;

aluo : out STD_LOGIC_VECTOR (7 downto 0));

end ALU;

architecture Behavioral of ALU is

begin

process (clk)

begin

if (clk'event and clk='1') then

if (op = "00000001") then aluo <= a and b;

elsif (op = "00000010") then aluo <= a or b;

elsif (op = "00000100") then aluo <= a xor b;

elsif (op = "00001000") then aluo <= a nor b;

elsif (op = "00010000") then aluo <= not a;

 elsif (op = "00100000") then aluo <= a + b;

elsif (op = "01000000") then aluo <= a - b;

elsif (op = "10000000") then aluo <= (not a) + 1;

end if;

end if;

end process;

end Behavioral;

===============================================

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are

-- provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;

entity Decoder is

Port ( reset : in STD_LOGIC;

clk : in STD_LOGIC;

q : out STD_LOGIC_VECTOR (7 downto 0));

end Decoder;

architecture Behavioral of Decoder is

signal counter: STD_LOGIC_VECTOR (2 downto 0);

begin

q(0) <= ((not counter(2)) and (not counter(1)) and (not counter(0)));

q(1) <= ((not counter(2)) and (not counter(1)) and (counter(0)));

q(2) <= ((not counter(2)) and (counter(1)) and (not counter(0)));

q(3) <= ((not counter(2)) and (counter(1)) and (counter(0)));

q(4) <= ((counter(2)) and (not counter(1)) and (not counter(0)));

q(5) <= ((counter(2)) and (not counter(1)) and (counter(0)));

q(6) <= ((counter(2)) and (counter(1)) and (not counter(0)));

q(7) <= ((counter(2)) and (counter(1)) and (counter(0)));

process (clk, reset, counter)

begin

if (clk'event and clk = '1') then

if (counter = "111" or reset = '1') then

counter <= "000";

else

counter <= counter +1;

end if;

end if;

end process;

end Behavioral;

==========================

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are

-- provided for instantiating Xilinx primitive components.

--library UNISIM;

--use UNISIM.VComponents.all;

entity Storage_Unit is

Port ( input : in STD_LOGIC_VECTOR (7 downto 0);

strobe : in STD_LOGIC;

q : out STD_LOGIC_VECTOR (7 downto 0));

end Storage_Unit;

architecture Behavioral of Storage_Unit is

begin

process (strobe,input)

begin

if(strobe='1') then

q<=input;

end if;

end process;
end Behavioral;

3- Synthesize your code and make sure it has no syntax errors.

2. Show the RTL schematic for your circuit for each component and for the whole circuit (up to
2 levels).

3. Simulate your code.

Report:
Include snapshots of your code, RTLs and Simulation in your report.

Conclusion:
Finally at this experiment we design and construct a simple Processor (CPU) using VHDL and test its
functionality. The CPU is the primary component of a computer that processes instructions. It runs
the operating system and applications .The computer would have at least one CPU which is usually
divided into a control unit, buses, temporary storages, and an ALU. our design of CPU is with Control
Unit that consists of a synchronous up-counter , Storage Units which is two strobed latches and ALU.

There was no difficulties in this experiment.