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XlNP
XlNN
MIP
MIN
' FHM
LSP
LSN
D-- HOP
HON
Specification Measured
111. ERRORAMPLIFIERS
An often-used topology for the error amplifiers is a
standard differential stage with current mirror load as
shown in Fig. 4 together with the corresponding n-channel
output transistor. For the upper branch of the output the L - - - - - - _ - - . - - - - - - -
same structure is used with n and p transistors exchanged. Fig. 4. Standard error amplifier.
The maximum voltage swing on the gate of the output
transistor of the structure shown can be approximately de- ~ . . . . . . . . .. . . . . . . . . . . ,
rived as follows: 1 : I
VGSM10 - VGSMl - vD\atMI
with
VGSMI = VTMI+ I/GSeffMI
and
vGSeffM1 - VDsatM1
we get
VGSMIO= Vin
3 ,
out
8.0 1.6 2.0 3.0 4.0 5.6 6.0 7.8 9.0 9.6 18.8
F r e q u e n z CkHzl
Fig. 8. Output spectrum for 7.4-V, output signal at 1 kHz into 50-n load.
The amplifier is in the bridge configuration ( V = 4.5 dB).
Fig. 7. Photomicrograph of two power amplifiers in bridge configuration.
ACKNOWLEDGMENT
Low-resistive connections via double bonding must be The authors wish to thank E. Engelhardt for the layout
provided for the high currents of up to k64 mA. In the of the amplifier and J. Feldmann for helpful discussions.
complete ARCOFI circuit the power amplifiers have their
own power supplies separated from the other chip sup- REFERENCES
plies. The width of the supply lines is 100 pm maximum. [ l ] J. A. Fisher and R . Koch, “A highly linear buffer amplifier,” IEEE
The measured results summarized in Table I were taken J . Solid-Stare Circuits, vol. SC-22, pp. 330-334, June 1987.
from two amplifiers set up in bridge connection. The dif- [2] L. Tomasini et al., “A low-voltage high-drive differential amplifier
for ISDN applications, ” in Proc. ESSCIRC’88.
ferential load consisted of a 5 0 4 resistor in parallel with [3] J. A . Fisher, “A high performance CMOS power amplifier,” IEEE J .
a 300-pF capacitor. Fig. 8 shows the distortion of the am- Solid-state Circuits, vol. SC-20, pp. 1200-1205, Dec. 1983.
plifier at 1 kHz with an output voltage of 7.4 Vp.p. The [4] K . E. Brehmer and J. B. Wieser, “Large swing CMOS power arnpli-
fier,” IEEE J . Solid-State Circuits, vol. SC-18, pp. 624-629, Dec.
second and third harmonic coefficients are below 75 dB, 1983.
which is far better than specified so that further optimi- [5] K. Nagaraj, “Large-swing CMOS buffer amplifier,” IEEE J . Solid-
zation of the circuit towards reduced area and current con- State Circuits, vol. 24, pp. 181-183, Feb. 1989.
[6] D. M. Monticelli, “A quad CMOS single-supply op amp with rail-to-
sumption is possible. The measured differential PSRR at rail output swing,” IEEEJ. Solid-state Circuits, vol. SC-21, pp. 1026-
1 kHz is better than 80 dB and at 1 MHz it is still 35 dB. 1034, Dec. 1986.