16#01#24

So#you#want#to#learn#Verilog#
!  Verilog(is(a(new(language(that(is(used(a(lot(in(
the(CSC258(labs.(It’s(not(hard(to(learn,(but(it(is(
different(from(other(languages(that(you’ve(
The$Verilog$Primer$ seen(before.((
!  This(primer(is(meant(to(give(you(a(sense(of(
what(Verilog(is(about,(and(what(you(need(to(
know(in(order(to(get(by(in(the(labs.((
!  It’s(a(living(document,(so(if(there’s(anything(
that’s(missing(or(unclear,(let(us(know!(

Understanding#Verilog# Basic#Verilog#Example#

!  The(first(thing(to(realize(about(Verilog(is(that(it( !  For(instance,(this(is(a(simple(AND(gate:(
is(not(a(programming(language,(but(is(a(
hardware(description(language((HDL).( A
Y
!  It’s(used(to(describe(what(the ( ((circuit( B
layout(needs(to(look(like, ( ( ((once(we(
start(designing(circuits ( ( ((that(are( !  If(you(had(to(create(a(software(language(that(
too(large(or(complicated ( (((((to( would(allow(you(to(specify(an(AND(gate(with(
implement(with(actual(chips ( ( (( these(inputs(and(outputs,(what(would(the(
and(wires.( specification(look(like?(

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 16#01#24

Basic#Verilog#Example#(cont’d)# The#basics#of#Verilog#
!  It(would(have(to(have(a ( ( ((name( !  Verilog(is(based(off(the(idea(that(the(designer(of(the(
that(you(could(use ( ( A ( ((((to( Y circuit(needs(a(simple(way(to(describe(the(
B components(of(a(circuit(in(software.(
describe(the(gate.(
!  There(are(several(basic(primitive(gates(that(are(built(
"  e.g.((((“and”(
into(Verilog.(
!  It(would(have(to(allow(you(to(specify(the(inputs(
#  and(out,in,in) #  or(out,in,in) #  not(out,in)
and(outputs(of(the(gate.(
#  nand(out,in,in) #  nor(out,in,in) #  buf(out,in)
"  e.g.(((((and(Y, A, B)
#  xor(out,in,in) #  xnor(out,in,in)
"  Since(gates(can(have(many(inputs(but(only(one(
output,(the(output(is(listed(first,(followed(by(all(of( "  twoSinput(gates(shown(here,(but(multiSinput(also(possible.(
the(gate’s(inputs.(

Creating#modules# Module#Example#
!  Using(builtSin(gates(is(one(thing,(but(what(if( !  Making(an(XOR(gate.(
you(want(to(create(logical(units(of(your(own?( "  An(XOR(gate(can(be( ( ( A ( (( Y
!  Modules(help(to(specify(a(combination(of(gates( represented(with(the( ( B ( ((((
with(a(set(of(overall(input(and(output(signals.( following(logic(statement:(
"  Specified(similarly(to(C(and ( ( ( ((
Python(functions.( Y = A·B + A·B
"  Less(like(functions(though, ( ( ( ((
and(more(like(specifying(a ( ( ( (( "  How(would(we(describe(a(logic(equation(like(this(in(a(
part(of(a(car.( hardware(design(language?(

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 16#01#24

Module#Example#(cont’d)# Module#Example#(cont’d)#
!  Not(to(hard(to(represent(it(in(logic(gates.(
A
B and(__,B,__)
A Y and(__,A,__)
B A
B or(Y,__,__)
Y
A
B
!  Wires(that(are(used(internally(in(the(circuit(to(
!  How(would(you(specify(the(AND(and(OR(gates?( connect(components(together(are(declared(
and(labeled(using(the(wire(keyword.(
and(__,B,__) "  Label(the(output(of(each(gate,(so(that(you(can(refer(
and(__,A,__) to(it(when(specifying(the(inputs(of(other(gates.(
or(Y,__,__)

Module#Example#(cont’d)# Module#Example#(cont’d)#
not_a b_not_a !  The(result(is ( (
wire (
not_a,( not_b;
( ((
the(circuit ( (
wire ( ( b_not_a;
a_not_b, ( ((
A
B description ( ( ( ( ( (((((
Y on(the(right.( and(b_not_a, B, not_a);
A and(a_not_b, A, not_b);
B !  The(order(of ( (
or(Y, (b_not_a,
( ( (((
a_not_b);
not_b a_not_b the(five(lines ( ( ( ( ( ((((
at(the(bottom ( not(not_a,
( ( (A); ( (((
not(not_b, B);
!  Note:(the(wire(names(are(not(built(in(or(named( doesn’t(matter.(
according(to(any(convention.(The(names(of(the( "  Remember:(Verilog(is(a(hardware(description,(not(a(
wires(is(at(the(discretion(of(the(designer.( programming(language,(so(the(result(is(the(same.(

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 16#01#24

Module#Example#(cont’d)# Module#Example#(cont’d)#
!  The(module(is( input A, B; !  Last(missing( module xor_gate(A, B, Y);
input A, B;
nearly(done!( output Y; feature:( output Y;
!  Only(missing( 3.  Keywords(
wire not_a, not_b;
three(things:( laying(out( wire not_a, not_b;
wire a_not_b, b_not_a;
1.  Semicolons(at( the(start( wire a_not_b, b_not_a;
the(end(of( and(b_not_a, B, not_a); and(end(of(
each(line.( the(module,( and(b_not_a, B, not_a);
and(a_not_b, A, not_b);
as(well(as( and(a_not_b, A, not_b);
2.  Statements( or(Y, b_not_a, a_not_b);
the(input( or(Y, b_not_a, a_not_b);
describing(the(
circuit’s(input( not(not_a, A); and(output(
not(not_a, A);
and(outputs.( not(not_b, B); signals.(
not(not_b, B);
endmodule

Module#review# A#note#about#Step##4#
!  Creating(a(module(follows(a(few(simple(steps:( !  There(are(alternate(ways(to(express(the(
1.  Declare(the(module((along(with(its(name,(its(input( internal(logic(of(a(module.(
and(output(signals,(and(where(it(ends).( "  assign(statements.(
2.  Specify(which(of(the(module’s(external(signals(are(
inputs(and(which(are(outputs.( and(Y, A, B); assign Y = A & B;
3.  Provide(labels(for(the(internal(wires(that(will(be(
needed(in(the(circuit.(
or(Y, A, B); assign Y = A | B;
4.  Specify(the(components(of(the(circuit(and(how(
they’re(connected(together.(
not(Y, A); assign Y = ~A;

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 16#01#24

Verilog#operators# Module#Example,#revisited#
!  C(and(Python(have(operators,(such(as:( module xor_gate(A, B, Y);
"  +,(-,(<,(==,(etc.( input A, B;
Operator( Operation( output Y;
!  Verilog(operators( ~( Bitwise(NOT((1’s(complement)(
"  “Bitwise”(operations ( &(( ( (
Bitwise(AND( (((( assign Y = A & ~B | B & ~A;
take(multiSbit(input ( |(( (
Bitwise(OR(( (((( endmodule
values,(and(perform( (( ^(( ( (
Bitwise(XOR( (((((
the(operation(on ( !(( (
NOT( ( (((((
&&( AND( !  This(also(works,(but(can(be(easier(to(express.(
the(corresponding( ( ( ( ( ((((((
||( OR(
bits(of(each(value.(
==( Test(equality(
"  More(operators(exist,( ( ( ( ((((((
but(this(is(enough(for(now.(

Using#modules# Making#a#mux#in#Verilog#
S
!  Once(a(module(is(created,(it(can(be(used(as(a( !  Remember(how(a(mux(works:(
component(of(other(modules(that(you(create.( X 0
M
"  Example:(half(adder(circuit.( M = X·S + Y·S Y 1

module half_adder(X, Y, C, S);

input X, Y; module mux(X, Y, S, M);
output C, S; input X, Y, S;
output M;
and(C, X, Y);
xor_gate(S, X, Y); assign M = X & ~S | Y & S;
endmodule endmodule

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 16#01#24

S
3Ibit#mux#in#Verilog# 3Ibit#mux#in#Verilog#
n
X
!  How(are(multiple(inputs( ( (
0 n
((handled(
M
!  Continuing(3Sbit(mux(example:(
n
by(Verilog?( Y 1

"  e.g.(3Sinput(multiplexers.( module mux(X, Y, S, M);

input [2:0] X, Y; // 3-bit input
!  Use(square(bracket(characters(to(indicate(a(
input S; // 1-bit input
range(of(values(for(that(signal.( output [2:0] M; // 3-bit output

module mux(X, Y, S, M); assign M[0] = X[0] & ~S | Y[0] & S;

input [2:0] X, Y; // 3-bit input assign M[1] = X[1] & ~S | Y[1] & S;
input S; // 1-bit input assign M[2] = X[2] & ~S | Y[2] & S;
output [2:0] M; // 3-bit output endmodule
...

A#note#about#ranges# End#of#combinational#design#
!  When(indicating(that(a(labeled(signal(represents(
!  Everything(so(far(has(been(about(specifying(
several(input(wires,(the(notation(for(the(range( combinational(circuits.(The(next(section(will(
can(vary:( discuss(the(elements(of(Verilog(that(arise(when(
"  e.g.((((input [2:0] X, Y; or ( (
you(incorporate(sequential(circuits.(
((((((((((input [0:2] X, Y;
!  If(you’ve(been(reading(all(these(slides(in(one(
!  Both(are(legal;(the(first(means(that(the(first(bits(
sitting,(this(is(a(good(time(to(stand(up,(get(
of(the(inputs(are(referred(to(as(X[2](and(Y[2].(
something(to(eat(or(drink,(and(stretch(while(
The(second(means(that(the(first(bits(of(the(
you(absorb(the(things(you’ve(just(read.(
inputs(are(referred(to(as(X[0](and(Y[0].(

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 16#01#24

Reflections#on#Verilog#
!  By(now,(you’ve(seen(several(elements(of(the(
Verilog(language,(but(it’s(good(to(put(them(into(
perspective(again.((
!  Verilog(is(used(to(specify(circuit(diagrams.(
"  If(you(had(to(describe(a(circuit(diagram(in(text(form,(
the(result(would(strongly(resemble(Verilog(syntax.(

“I(need(two(AND(gates,(one(with(inputs(
wire ab, cd;
A(and(B,(the(other(with(inputs(C(and(D,(
and(ab, A, B);
with(an(OR(gate(whose(inputs(are(the(
and(cd, C, D);
outputs(of(the(two(AND(gates(and(with(
or(Y, ab, cd);
an(output(called(Y…”(

More#reflections#on#Verilog# Other#simplification#syntax#
!  What(about(sequential(circuits?(
!  If(you(can(describe(a(circuit(diagram,(you(have(
"  i.e.(circuits(involving(flipSflops.(
the(ability(to(specify(your(circuit(in(Verilog!(
!  One(way(to(specify(them(is(using(gate(design:(
!  Verilog(also(tries(to(provide(shorter(syntax(for(
describing(certain(circuits.( // A gated D latch
module d_latch (D, Clk, Q);
"  Example:(Simple(boolean(circuits:( input D, Clk;
output Q;

wire R, S, Qa, Qb /* synthesis keep */ ;

wire ab, cd; nand (R, D, Clk);

and(ab, A, B); nand (S, ~D, Clk);
assign Y = A & B | C & D; nand (Qa, R, Qb);
and(cd, C, D);
nand (Qb, S, Qa);
or(Y, ab, cd);
assign Q = Qa;
*Quartus(makes(these(equivalent(at(compile(time!( endmodule

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 16#01#24

Other#simplification#syntax# Using#always
!  Another(way(of(specifying(this(latch(is:(
!  The(always(keyword(provides(even(more(
"  “Set(Q(to(the(value(of(D(whenever(Clk(is(high.”(
abstraction(than(boolean(equations,(but(in(the(
!  This(is(based(on(the(concept(of(polling,(where(the(
software(keeps(checking(the(values(of(D(and(Clk(to(see( end,(everything(is(translated(into(simple(gates.(
if(the(output(Q(needs(to(be(updated.( !  Other(related ( ( ( ( ( ((
!  The(better(version(is(based(on(interrupts,(where(the( highSlevel ( ( ( ( ((
circuit(reacts(when(certain(signal(values(change…(
keywords:(
"  “(Whenever(D(or(Clk(change,(do(the(following.”(
"  if/else
always @ (D, Clk) "  for
begin
... "  case
end

Using#always Always#example:#SR#latch#
module sr_latch(R, S, Clk, Q, Q_not);
!  Best(to(show(always(through(examples.( input R, S, Clk;
output reg Q, Q_not;
"  Example(#1:(An(RS(latch.(
always @ (R, S, Clk)
!  If(R(and(S(are(0(and(0,(output(is(unchanged.( if (Clk & (R | S))
!  If(R(and(S(are(1(and(0,(Q(is(set(high(and(Q(is(set(low.( begin
if (R & ~S)
R
!  If(R(and(S(are(0(and(1,(Q(is(set(low(and(Q(is(set(high.( Q_not = 1; Q
else
!  If(R(and(S(are(1(and(1,(Q(and(Q(are(both(set(low.( Q_not = 0;
if (S & ~R)
Q = 1;
else Q
S
Q = 0;
end

endmodule

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 16#01#24

Using#if,#else#&#else#if# if/else,#begin#and#end#
!  Just(like(in(other(languages,( if (S & ~R)
!  The(if(and(else(keywords(are(most(useful( the(if(condition(can(be( Q = 1;
within(an(always(block.( followed(by(a(single( else
Q = 0;
"  Using(them(outside(the(always(block(doesn’t(work.((
statement.(
!  If(you(want(the(circuit(to(
"  The(if/else(statements(are(meant(to(turn(signals(
perform(multiple(statements( if (S & ~R)
on(or(off(in(response(to(certain(conditions.(The( in(response(to(a(condition,(use( begin
Q = 1;
always(statement(is(needed(to(tell(the(Verilog( the(begin(and(end( Q_not = 0;
compiler(when(to(test(for(those(conditions.( keywords,(like(braces(in(C(or( end
Java.(
!  The(if,(else if(and(else(statements(can(be( "  Note:(If(you(forget(to(use(begin(
nested,(just(like(any(other(language.( and(end,(the(compiler(will(
assume(that(only(the(next(line(
belongs(in(the(if(statement.(

always#and#initial# for#loops#
!  The(always(keyword(tells(the(compiler(to( !  The(initial(keyword(and(for(loops(go(well(
listen(for(conditions(in(certain(signals,(and( together,(as(a(result.(
make(the(circuit(respond(in(those(cases.( "  for(loop(syntax(is(similar(to(C(and(Java:(
!  The(initial(keyword(does(something( reg [15:0] memory [255:0];
similar((makes(the(circuit(perform(a(set(of( integer index;

operations),(but(only(when(the(circuit(starts.( initial
begin
"  Only(occurs(once,(at(beginning.( for(index = 0; index < 256; index = index + 1)
"  Useful(for(initiating(circuit(elements.( begin
memory [index] = 0;
end
end

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 16#01#24

case#statements# case#example:#7Iseg#decoder#
!  One(more(important(control(statement!(( !  Easier(to(specify( module SevenSegmentDisplayDecoder(ss_out, bcd_in);
output reg [6:0] ss_out;

!  The(case(statement(works(similarly(to(its(Python,( decoders(like( input [3:0] bcd_in;

C(and(Java(counterparts:( the(sevenS always @(bcd_in)

case (bcd_in)

segment(
4'h0: ss_out = 7'b0111111;
4'h1: ss_out = 7'b0000110;
4'h2: ss_out = 7'b1011011;
case (<variable name>) decoder(using( 4'h3: ss_out = 7'b1001111;
4'h4: ss_out = 7'b1100110;
< case1 > : < statement >
< case2 > : < statement > case(syntax.( 4'h5: ss_out = 7'b1101101;
4'h6: ss_out = 7'b1111101;
4'h7: ss_out = 7'b0000111;
...
"  Result(is(the( 4'h8: ss_out = 7'b1111111;
default : < statement > 4'h9: ss_out = 7'b1100111;
endcase same(as(the( 4'hA: ss_out = 7'b1110111;
4'hB: ss_out = 7'b1111100;
version(obtained( 4'hC: ss_out = 7'b0111001;
4'hD: ss_out = 7'b1011110;
through(KSmaps( 4'hE: ss_out = 7'b1111001;
!  Good(for(creating(decoders,(or(reacting(to(inputs( 4'hF: ss_out = 7'b1110001;
and(reduction.(
that(could(have(many(possible(values.(
default: ss_out = 7'b1111001;
endcase
endmodule

Reflection#time# Reflection#time#
!  Remember:(This(course(is(about(circuits,(not(Verilog($( !  Take(a(moment(to(think(about(this!(People(
!  However…designing(and(testing(these(circuits(is( often(get(unduly(distressed(about(higherSlevel(
easier(with(tools(or(specification(languages.(
Verilog(statements.(
"  Designing(complex(circuits(by(wiring(chips(and(gates(
together(can(take(forever(and(be(full(of(bugs.( !  Really(though,(these( ( ((statements(
"  Designing(gateSbySgate(in(Verilog(is(faster,(reproducible,(( make(life ( ( ( ((((((a(lot(easier,(
and(yields(fewer(bugs.(
once(you ( ( ( (((get(the(hang(
"  More(powerful(keywords(like(always,(if/else(and(case(
create(the(same(logic(with(less(work,(by(simply(specifying( of(using ( ( ( (((((these(keywords(to(
the(behaviour(that(you(want(instead(of(the(specific(circuit.( say ( ( ( ((what(the(circuit’s(
!  Like(specifying(string(and(dictionary(behaviour(in(Python(or(C,( ( ( ( ( ((behaviour(should(
instead(of(creating(your(own(objects(from(scratch.(
be.(

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 16#01#24

Storing#and#assigning#data# Storing#and#assigning#data#
!  FlipSflops(and(sequential(circuits(allow(us(to( !  Labels(can(be(given(to(both(
A
design(circuits(that(can(store(values.( wire(and(reg(values.(( B
Y
"  Some(are(implicit,(in(latchSstyle(feedback(circuits.( "  Main(difference:(reg(values(
"  Others(can(be(made(explicit,(using(reg(values.( can(drive(output;(wire (((
module reg_example( a, b, y);
values(can’t.(
!  We’ve(used(reg(before, ( ( (((((in(the( input a, b;
output y;
SR(latch(example.( reg y;
module wire_example( a, b, y); wire a, b;
input a, b;
output y; always @ ( a or b)
wire a, b, y; begin
y = a & b;
assign y = a & b; end

endmodule endmodule

Reg#versus#wire#
!  “Driving(output”?(What(does(that(mean?(
"  Remember(that(Verilog(is(used(to(specify(a(circuit(
layout.(The(wire(keyword(specifies(where(an(actual(
wire(would(be,(and(connecting(two(points(with(a(
wire((or(wire)(just(makes(them(logically(equivalent.((
"  A(reg((short(for(register)(can(actually(store(a(value(
and(drive(an(output(signal.(Any(always(or(
initial(blocks(that(need(to(set(a(value(must(do(
so(by(setting(reg(values.(
!  Similarly,(wires(can’t(be(reassigned(to(connect(new(
points(together(partway(through(a(circuit’s(operation.(
Literal#values#
!  Sometimes(you(need(to(assign(a(set(of(wire(or(
reg(values(at(the(same(time.(
"  Example:(the(sevenSsegment(display.(
"  Possible(to(assign(each(segment(one(at(a(time,(but(
easier(to(assign(them(all(at(once.(
!  Literal(values(in(Python(and(C(are(values(like(
42,(3.14(and(“Hello”.(
!  Verilog(has(literal(values(as(well.(
"  But(exactly(what(does(101(represent(in(Verilog?(

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 16#01#24

Literal#values# Example:#sevenIseg#decoder#
!  101(can(represent(different(values,(depending( !  The(instructions(in(the( ( ( ((sevenS
on(what(type(of(number(it(is.( seg(decoder( ( ( ( ( ((code(
"  Decimal:(101(=(one(hundred(and(one((base(10).(
translate(to(the ( ( ( ((
"  Binary:(101(base(2(=(5(base(10(
following:(
"  Hexadecimal:(101(base(16(=(257(base(10(
"  “in(the(case(where(the ( ( ( ((
"  (Octal:(101(base(8(=(65(base(10)(
fourSbit(BCD(input(has(a(hexadecimal(value(of(0…”(
!  In(Verilog:( "  “…set(the(value(ss_out(to(a(7Sdigit(binary(value(of(
"  Binary: ( ( (‘b101 0111111.”(
"  Decimal: ( (‘d101
"  Hexadecimal: ( (‘h101

References#

!  Verilog(Language(Reference(Guide:(
"  http://verilog.renerta.com/(
!  Verilog(Page:(
"  http://www.asicSworld.com/verilog/(
!  Verilog(Tutorial:(
"  http://www.fullchipdesign.com/verilog_tutorial.htm(

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