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Low voltage Low power CMOS Analog Building Blocks for Mobile
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Low voltage Low power CMOS Analog Building Blocks for Mobile
Microelectronics Applications

Changku Hwang1 2 , Akira Hyogo3 , Mohammed Ismail2, Ali Motamed4 and Hong-sun Kim2
;

1. Micrys, Inc., Columbus, Ohio, USA

2. Department of Electrical Engineering, Ohio State University, Columbus, Ohio, USA
3. Department of Electrical Engineering, Science University of Tokyo, Japan and currently
on leave at the Ohio State University as a visiting scholar
4. Exar, Corp., Fremont, California, USA, previously at the Ohio State University
 I. Introduction

Recently there is a great demand for lighter hand-held mobile microelectronics with longer battery life-
time. This type of microelectronics requires reduced supply voltage and low power consumption. Hence it
is no doubt that LV/LP IC circuits must be developed.
As the level of integration in RF transceivers increases, CMOS will emerge as the technology with the
greatest potential for cost eectiveness. This will be particularly true when mobile, wireless communication
is integrated in future multimedia systems [1, 2, 3]. Most of the key building blocks for a complete RF front-
end for personal communication systems applications have recently been demonstrated in CMOS, including
complete RF ICs [4]. Because baseband digital circuitry is currently implemented in standard sub-micron
CMOS, there is a tendency to use the same digital CMOS processes for baseband data converters and analog
building blocks.
In this paper we introduce several CMOS analog building blocks useful for such baseband analog signal
processing, especially operating with low supply voltage and low power consumption;LV CMOS composite
cells, LV OpAmp input stage with rail-to-rail constant-gm, single-ended-input fully balanced-output circuit,
LV multiplier and CMOS pseudo exponential current-to-voltage converter for variable gain amplier(VGA).

II. LV CMOS composite cells

A single CMOS transistor (see Fig.1) exhibits the square law dependency on the gate-source voltage
required in numerous signal processing applications. However, the low input impedance at the source of
the transistor limits the applicability of the single transistor solution and calls for more elaborate designs in
many cases. As one of such elaborate designs new LV composite cells with two high impedance terminals
which control current ow through the transistors are introduced in this section and they are shown in Fig.1.

Cell1[5] and Cell2[6] in Fig.1 have the drain current Id expressed as

Id = K2eq (Vgs , VTeq1 )2 (1)

where Keq and VTeq1 are the equivalent transconductance parameter and the threshold voltage, respectively,

1
 Vd
VDD Mpcm VDD
Vd
Id IB
Vg Id

Id Vg Id Vg
Vtn+|Vtp| Mn1 Mn2 Mn1 Mn2
Vg
Mp1
Vtn Vs Vs Vs
Vs IB
IB Mp1 Id
Id

VSS VSS

Conventional
Single Composite
Tr Tr Cell1 Cell2

VDD Mpcm VDD Mpcm VDD Mpcm

IB
Id Id Id
Mn3 Id
Id1 Id2 Id
Vg (=Id1) Vg
Mn1 Mn2 Mp1 Vy Mn1 Mn2
Mp1
Vs Vg Mn1 Mn2
Mp1 Vs
Id Id
Id Vx Vs Id
Id
IB Id3 IB
Mn5 Mn4

VSS VSS
VSS

Cell3 Cell4
Cell5

VDD VDD VDD

IB
IB IB
Id Id Id Id Id Id

Id Id
Id
Vg Vg Vg
Mn1 Mn2 Mn1 Mn2 Mn1 Mn2
Mp1 Mp1
Mp1 Vs
Vs
Id Id Id
Id Vs Id

IB IB IB
Id

VSS VSS VSS

Cell6 Cell7 Cell8

Figure 1: Single, conventional and LV composite cells.

given by
,2
Keq = (p 1 + p1 ) (2)
Kn1 Kp1
s
VTeq1 = j VTp j , 2(IBK, Id ) (3)
n2

2
In the case where IB  Id the above equation can be simplied as
r
VTeq1
2IB
= j VTp j , K (4)
n2

which is much less than the equivalent threshold voltage VTeq =j VTp j +VTn of the conventional composite
transistor[7](see Fig.1) and hence is suited for LV application.
Modications[8] of Cell1 and Cell2
As described previously, both circuits should satisfy the assumption that IB  Id to reduce VTeq1
variation in Eq.(3). Otherwise it could degrade the accuracy of signal. Therefore, IB has to be set at much
larger value than the maximum Id , implying that Id can not be increased more than IB . This causes high
power consumption at quiescent conditions due to the large IB . This problem can be overcame by using the
following methods;

1. a constant voltage shifter (Cell3 based on Cell1).

The feedback loop formed by transistors Mn2 , Mn3 , Mn4 and Mn5 and the bias current IB always
keeps the drain current of Mn2 equal to IB . This makes the voltage drop Vgs2 (or Vgs2 , VTn ) of Mn2
constant.

2. an adaptive bias technique (Cell4&5 based on Cell1 and Cell6; 7&8 based on Cell2).
In order to cancel Id eect in Eq.(3), the current IB + Id can be used instead of the constant current
IB . For this purpose, a current mirror circuit is used to copy Id and add it to IB . The summed current
IB +Id is replaced with IB in the second term of the right hand side in Eq.(3). Thereby, Eq.(3) becomes
Eq.(4) which is constant regardless of the input voltages applied.

The proposed circuits have been simulated using MOSIS 2m n-well process with VTn =0:82V and
VTp =,0:88V and a supply voltage of 3V . The drain currents of each cell(Cell1-4; 6; 8) with IB =120A,
a single NMOS transistor with Kn and VTn equivalent to Keq and VTeq1 (Eq.(4)), respectively and numerical
evaluations of Eq.(1) with Keq and VTeq1 (Eq.(4)) are shown in Fig.2 (a) as a function of Vg with Vs =0:5V
where each cell exhibits square law drain current characteristic on Vgs . Similar simulation is performed with
IB =12A in Fig.2 (b). It should be noted in this gure that the drain currents of Cell3 , 8 can increase

3
 80u 80u
Id Id
[A] Vs=0.5V [A] Vs=0.5V
60u 60u

40u 40u

20u 20u

0 0
1 1.5 2 2.5 3 1 1.5 2 2.5 3
Vg [V] Vg [V]
cell1 cell2 cell1 cell2
cell3 cell4 cell3 cell4
cell6 cell8 cell6 cell8
single Tr Eq.(1) single Tr Eq.(1)

(a) (b)
Figure 2: DC characteristics of Cell1-8 (a) IB =120A and (b) IB =12A.

beyond IB (=12A).

III. LV multiplier with wide input operating voltage range

Owing to the versatility of analog multiplier, it can be found in numerous applications such as commu-
nications and analog signal processing circuits. With the supply voltage reduction, however, many existing
CMOS multipliers are faced with a serious design problem which was insignicant with a relatively high
supply voltage and now becomes important with low supply voltage; that is, input operating voltage range
for a linear output signal swing. As supply voltage decreases, the input voltage range of the multiplier is
limited signicantly or in worst case diminishes. In this section as an application of the new LV composite
cell introduced in the previous section, it has been used in four-quadrant analog multiplier[6] and its circuit
implementation is shown in Fig.3 (a) where four new composite cells are elaborately combined to form the
multiplier.
Using Eq.(1), the output current io can be evaluated as

io = I2 + I3 , I1 , I4 (5)
= Keq (V1 , V2 ) (V3 , V4 )

Fig.3 (b) shows the region of operation for this multiplier. For a symmetric operation, i.e. when the

4
 I1 I3 I4 I2
IB

V1 V1
V3 V4
V2

IB

(a)
V3,4
Maximum
3 Symmetric
Operating
Region

3-|Vtp|-|Vds,sat|

1 Operating
Region
0.5

0 V1,2
Vtn+Vds,sat 2 2.5 3
(b)

Figure 3: (a) Multiplier and (b) its operating region.

0.12 0.12
Vout V34=1.0V Vout
[V] [V]

0.06 0.6V 0.06

0.2V
0.00 0.0V 0.00

-0.2V
-0.06 -0.6V -0.06

-1.0V
-0.12 -0.12
-1 -0.5 0 0.5 1 100n 150n 200n 250n 300n
V12 [V] Time [s]

(a) (b)
Figure 4: Multiplier characteristics (a) DC and (b) Transient

5
input voltages have the same dierential input magnitudes
v12;max =
v34;max =1Vpp , VCM 1 and VCM 2
should be set to 2.5V and 0.5V, respectively and it is pictorially illustrated as rectangular, double cross
hatched region. Fig.4 (a) and (b) show DC and transient characteristics of the multiplier with simple
resistor/capacitor load(Ro=5k
/Co=0.1pF), respectively. In (b) two 1Vpp input signals with frequencies
of 10MHz and 100MHz are modulated. For the simulations, the input common mode voltages used are
VCM 1 =2.5V and VCM 2 =0.5V with a single supply of 3V.

IV. A CMOS exponential current-to-voltage converter for VGA

V1 Io
ANALOG MULTIPLIER
V2
V3 V4
V3-V4

Ic or Vc

Ic or Vc

Figure 5: Block diagram of a VGA with exponential gain control.

A VGA with an exponential gain control characteristic is desired in applications where wide range gain
control is required; that is, the gain should increase monotonically on a decibel scale with linear increments
in gain control signal. To fulll this need, a new pseudo-exponential voltage generator[9] is introduced in
this section. This very compact and power ecient CMOS circuit oers a superb exponential characteristic.
The generated voltage is ideally suited as a gain control voltage, VV GA;C , in a CMOS VGA circuit built,
e.g., using a voltage multiplier introduced in section 4 with VV GA;C applied to two of the multiplier's four
inputs as shown in Fig.5.
The gain control signal IC of the pseudo-exponential voltage generator shown in Fig.6 (a) is a bidirectional

6
 VDD 3
10

f(y), n=1
f(y), n=2
P2 P1 2
10
f(y), n=3
Exp(2ny), n=2

1
I1 I1 10
Ic
Vc 0
10

I2 I2
−1
10
|−−−−− Error < 2% −−−−−|
−0.24 0.24

N2 N1 −2
10 |−−−−−−−− Error < 5% −−−−−−−−|
−0.32 0.32

−0.8 −0.6 −0.4 −0.2 0 0.2 0.4 0.6 0.8

VSS y

(a) (b)
Figure 6: (a) Back-to-Back connection of two 1:1 current mirrors. (b) Exp(2ny) with n=2 and f (y) with
n=1, 2 and 3 as a function of y. This gure also shows the regions where the error is less than 2% and 5%
when n=2.

current with positive direction chosen to be outward. Assuming K = Kn1 = Kn2 = Kp1 = Kp2 , we have

I1 = K2 (VDD , VC , j VTp j)2 I2 = K2 (VC , VTn )2 (6)

Using the fact that I2 = I1 - IC , we obtain

VC = VDD , j V2Tp j +VTn , K (V IC

(7)
DD , j VTp j ,VTn )

Substituting Eq.( 7) into Eq.( 6) yields

 V , j V j ,V 2
I1 = K2 DD Tp
2
Tn + IC
K (VDD , j VTp j ,VTn )
(8)
 2
K V , j V j ,V
DD Tp I
Tn
I2 = 2 2 , K (V , j VC j ,V ) (9)
DD Tp Tn

The ratio of the two currents I1 and I2 can be written as

 + y n
f (y ) =
I1
I2
= 11 , y
(10)

IC 2 and = VDD ,jVTp j,VTn .

where n=2, y= 2K 2

The function f (y) is a close approximation of the exponential function Exp(2ny). Fig.6 (b) shows f (y) with
n=1 [10], 2 and 3 and Exp(2ny) with n=2 on semi-logarithmic coordinates and denes the range where the

7
approximation with n=2 holds within less than 2% and 5% error. Note that a larger n yields a larger control
range for f (y).
−5 −5
x 10 x 10
4 4
I2 I1
I1 and I2 [A]

2 3

Kn=7.1E−5
2
0
−4 −3 −2 −1 0 1 2 3 4 Kp=7.1E−5
(a−1) Ic [A] −5
10 x 10
1
I1/I2

Ic [A]
5 0

0 −1
−4 −3 −2 −1 0 1 2 3 4
(a−2) Ic [A] −5
x 10
20 −2
I1/I2 [dB]

0
−3
−20

−4 −3 −2 −1 0 1 2 3 4 −4
(a−3) Ic [A] 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2
−5
x 10 Vc [V]

(a) (b)
Figure 7: (a) (a-1):Simulated currents I1 and I2 of the circuit of Fig.6 (a) (a-2):the ratio II21 (a-3):the ratio
I1 expressed in dB. (b) Simulated input voltage-current characteristic of Fig.6 (a)
I2

Fig.7 (a-1) shows the simulated currents I1 and I2 in Fig.6 (a) as function of the control current IC . As
stated previously IC can assume both positive and negative values. Fig.7 (a-2) depicts the ratio II12 as IC is
varied from -30A to 30A. The accuracy of the approximation is shown more clearly by plotting the graph
on a semi-logarithmic scale as depicted in Fig.7 (a-3) which shows a control range of 40dB.
The two current mirrors of Fig.6 (a) have another interesting characteristic as revealed by Eq.( 7), which
is a constant linear resistance at the input terminal. The resistance can simply be found by examining
Eq.( 7) and can be expressed as

Rin = K (V 1 (11)
DD , j VTp j ,VTn )

The negative sign in Eq.( 7) appears because the positive direction of IC is chosen to be outward as shown
in Fig.6 (a). A constant input resistance implies that the circuit is responsive to a gain control voltage VC as
well as a gain control current. This property is useful if the gain control signal is in voltage form. Fig.7 (b)
shows the simulated input voltage-current characteristics of this circuit where the slope of the line represents

8
the input conductance. Note that VC should vary from almost 1.2V to 1.9V in order to obtain the same
eect as sweeping IC from -30A to 30A.
VDD
P5 P3 P1
P4 P2

I1 I1
I2
Ic

vds Vd
To Vd
I2 I2
vds VG

N4 N3 N2 N1
To Vs
Ic
VSS
(a)
0.5

0.4
Vds [V]

0.3

0.2

0.1

0
−4 −3 −2 −1 0 1 2 3 4
−5
x 10
Ic [A]
0

−10
Vds [dB]

−20

−30

−40
−4 −3 −2 −1 0 1 2 3 4
−5
x 10
Ic [A]

(b)

Figure 8: (a) The complete circuit diagram of the exponential current-to-voltage converter (b) the simulated
output voltage, vds

Fig.8 (a) shows the complete circuit diagram of the pseudo-exponential voltage generator. The current
mirror P3-P4 is used to direct the current I2 to the drains of P5 and N4. A constant resistance, similar to
Rin in Eq.(11), is seen at the common drain node of the two diode connected transistors, P 5 and N 4 which
is also the gate of N 3. It converts the current I2 to a voltage, VG3 , which can be expressed by Eq.(7) with
IC replaced by I2 . Transistor N3 operates in the triode region and acts as a voltage controlled resistor. For
small drain-source voltages, the resistance exhibited by N3 is RDS ' Kn3 (VG13 ,VTn) . Hence, I1 ows through
N3 and generates a drain-source voltage, VDS = RDS I1 , proportional to II12 . Fig.8 (b) shows the simulated

9
drain-source voltage of N3 using both linear and logarithmic scales versus IC which shows close to 30dB
control voltage range. This has been veried experimentally in a 3V CMOS AGC test chip [5] fabricated in
a 2m process.

V. LV/LP OpAmp input stage with rail-to-rail constant-gm

In LV OpAmp design the rail-to-rail complementary input pair [11] is often used. However, the use
of complementary input pairs results in the variation of the input stage transconductance, gm, with the
common-mode input voltage. When both input pairs operate, the overall transconductance, gmt , varies by
a factor of two from the level at which only one pair operates. Such variation causes signal distortion and
introduces similar variation in the unity gain bandwidth. In this section, we use a novel and universal concept
which is independent of the input transistor types (MOS, Bipolar, or BiCMOS) and their operating regions
(weak or strong inversion for MOS and active for Bipolar) to obtain rail-to-rail constant-gm using simple,
traditional bias circuitry. The main idea is that if a current pair (Io1 ,Io2 )= (max[In1 ,Ip1 ],max[In2 ,Ip2 ]) in
Fig.9 (a) is selected at any common mode input voltage, a constant gm equal to gm;max can be obtained in
the entire common mode input range regardless of their operating regions(see [12, 13, 14, 15] for verications
in detail).
A new CMOS complementary input stage based on the proposed idea is shown in Fig.9 (a). It consists
of a complementary input stage N1 , N2 , P1 and P2 , two Max-circuits, N3 -N7 and N8 -N12, bias transistors.
After the input voltages are converted to currents, the Max-circuit N3-N7 takes a current pair [In1 , Ip1 ] as
its input, while the Max-circuit N8 -N12 takes the pair [In2 , Ip2 ] as its input. The two Max-circuits generate
the two output currents Io1 and Io2 in the form of
IB vid
Io1 = 2 + gm;max
2 (12)
IB vid
Io2 = 2 , gm;max 2 (13)

and constant gm can be obtained by subtracting them at the following gain (or output) stage at any common
mode input voltage.
The measured transconductance of n-, p-pair and total, namely gmn, gmp and gmt in strong inversion is
shown in Fig.9 (b-1) with dierent bias currents (IB =4, 6 and 8 A). This gure depicts that the maximum

10
 VDD

P6 P5 IB P3 P4

In2 Ip In1
M1 M2
Vb

P2 N2 N1 P1

Vin+ Vin- Vin+ Vin-

Ip2 Ip1
Io2
In
Io1
IB

N12 N11 N10 N9 N8 N3 N4 N5 N6 N7

VSS

(a)
−5
x 10
8
gmn, gmp and gmt (A/V)

gmt(8u)
6
gmt(6u)
4
gmt(4u)

2 gmn(4u) gmp(4u)

0
0 0.5 1 1.5 2 2.5 3
(b−1)
−7
x 10
5
gmn, gmp and gmt(A/V)

3
gmt(20n)
2

1 gmn(20n) gmp(20n)

0
0 0.5 1 1.5 2 2.5 3
(b−2) VCM

(b)

Figure 9: (a) A new, simple input stage to achieve programmable rail-to-rail constant-gm and (b) measured
transconductances (b-1) in strong inversion (IB =4, 6 and 8A) and (b-2) weak inversion (IB =20nA)

gmt variation is less than 5%. The transconductance in weak inversion is also measured and shown in Fig.9
(b-2), where the maximum gmt variation is around 17% which is mainly cause by the larger slopes of the gmn
and gmp curves near both ends of the input common mode voltage and the mismatch of the slope factors of
n- and p-MOS transistors.

VI. A single-ended-input to fully-balanced-output CMOS circuit (SFC)

For fully balanced circuit architecture(FBCA) it is necessary to generate fully balanced signals from
single-ended input signal at the front-end of the system. In general, V-I converter with simple resistive load

11
at the outputs is useful for this purpose due to its symmetric circuit structure. In modern CMOS process,
however, the value of R varies by more than 30% from its nominal value and IB variation is not neglectable,
either. Thus, the output common mode voltage, Vo;com =R  IB is deviated from the targeted level by, in
worst case, more than 50%. This could cause malfunction of the following circuit due to the deviation of
the DC operating voltage from the desired value and limit signal swing at the outputs of SFC as well. In this
section we intorduce a new SFC composed of a voltage-to-current(V-I) converter with simple resistive load
at the outputs and active current common mode feedback(CMFB) circuit[16]. This SFC generates Vo;com
independent of process variation of resistors and is determined only by a preset dc common mode level Vcom .

Vin Io+
Vo+
V-I Converter
Vref Vo-
Io-

Icom,f Vc R R

Vcom CMS Icom

CMS corrector
generator

Figure 10: General block diagram of the proposed SFC

Fig.10 illustrates a general block diagram of the proposed SFC with a new active current CMFB circuit.
Vin is single-ended input signal with dc level of Vref . A common mode signal(CMS) corrector in the feedback
path generates a corrected signal Vc proportional to the dierence between Icom;f and Icom that are produced
in the V-I converter and bias circuitry, respectively. This Vc again stabilizes Icom;f in such a way that the
sum of the two output currents Io+ and Io, is equivalent to Icom . In this way, Vo;com of SFC is set at the
desired level, i.e. the preset DC voltage Vcom . This operation is explained in details with the MOS circuit
implementation shown in Fig.11. The CMS generator outputs a common mode current Icom given by

Icom = 2 Vcom
R
(14)

where Vcom is a preset DC voltage which Vo;com should track.

For common mode input voltage, Icom and the feedback current Icom;f , which is the sum of Icom;f + and

12
 V-I Converter CMS Corrector CMS Generator

M11 M9 M10 M12 2: 1

M3 M4 M15 M16
Rc Icom,f-
Vcom
Icom,f+ Icom M17 A
Vin M1 M2 Vref
Io+ Io-
Icom,f C
Vo+ Vo-
R
M7 M8
Ro M5 M6 Ro M13
M14
IB IB
R=Rc=Ro
Vc

Figure 11: Circuit diagram of the proposed SFC

Icom;f , owing through M 11 and M 12 in Fig.11, are compared at node C and CMS corrector generates
control voltage Vc proportional to the dierence between Icom and Icom;f . This Vc adjusts Icom;f to equal
to Icom by means of negative feedback formed by M 3 , M 8 and M 11 , M 15. Current mirrors M 3; M 9 and
M 4; M 10, copy Icom;f
2
at the two outputs, resulting in

IO+;com = IO,;com = Icom;f Icom

2 = 2 = R
Vcom
(15)

Then, we can have common mode output voltage as

VO+;,;com = IO+;,;com  R = Vcom (16)

Consequently, the common mode output voltage always equals to a preset dc voltage Vcom independent of
R variations.
On the contrary, the current Icom;f does not vary with dierential mode input voltage because any current
increase(decrease) in Icom;f + results in the same amount of current decrease(increase) in Icom;f , and thus
the CMFB circuit seems deactivated for the dierential mode input voltage. This makes the outputs of SFC
interact only with the dierential mode input voltage.
To verify that the proposed circuit should generate Vo;com equal to a preset DC voltage regardless of R
variations, the circuit was simulated with 4 dierent values of R, i.e. R=5, 10, 15 and 20k
and 0.5Vpp input
signal with frequency of 1MHz as shown in Fig.12 (a). The R variation corresponds to 100% deviation

13
 Vout [V] Vout [V] Vo+ Vo-
Vo+ Vo-
2

1.75

1.5

1.25

Time [s] Time [s]

(a) (b)
Figure 12: Output transient responses with dierent values of (a) resistor, R=5, 10, 15 and 20k
and (b)
preset DC voltage, Vcom =1.4, 1.6 and 1.8V with R=10k

from the designed value, R=10k

. Nonetheless, Fig.12 (a) depicts that Vo;com only varies in the range of
1.57 to 1.63V and its variation is within less than 2%, mainly caused by channel length modulation of
transistors in the CMFB circuit. Phase dierence between the two outputs was also measured and it shows
the desirable value, 180.
Similar simulations were performed with respect to dierent values of preset dc voltages, Vcom =1.4, 1.6
and 1.8V and R of 10k
to demonstrate the controllability of Vo;com. The result is shown in Fig.12 (b) where
respective Vo;com of 1.45, 1.68 and 1.82V were obtained. The absolute value dierence between the preset
dc Vcom and Vo;com is due to the low gain of amplier(marked as A in Fig.11) used in the CMS generator,
which is a simple source-coupled dierential amplier.

VII. Conclusion
Several analog basic building blocks for baseband analog signal processing in mobile microelectronics
applications have been introduced. These blocks are particulraly suitable for low voltage and low power
operation in standard CMOS VLSI technologies.

14
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