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NCV3063
1.5 A, Step-Up/Down/
Inverting Switching
Regulators
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The NCP3063 Series is a higher frequency upgrade to the popular
MC34063A and MC33063A monolithic DC−DC converters. These MARKING
devices consist of an internal temperature compensated reference, DIAGRAMS
comparator, a controlled duty cycle oscillator with an active current
limit circuit, a driver and a high current output switch. This series was
specifically designed to be incorporated in Step−Down, Step−Up and 3063x
Voltage−Inverting applications with a minimum number of external ALYW
components. 8 G
1 1
Features SOIC−8
• Operation to 40 V Input D SUFFIX V3063
CASE 751 ALYW
• Low Standby Current
G
• Output Switch Current to 1.5 A 1
• Output Voltage Adjustable
• Frequency Operation of 150 kHz
• Precision 1.5% Reference NCP3063x
AWL
• New Features: Internal Thermal Shutdown with Hysteresis YYWWG
New Features: Cycle−by−Cycle Current Limiting
1
• Pb−Free Packages are Available 8
1
Applications PDIP−8 NCV3063
• Step−Down, Step−Up and Inverting supply applications P, P1 SUFFIX AWL
CASE 626 YYWWG
• High Power LED Lighting
1
• Battery Chargers
8 1 NCP
NCP3063 3063x
TSD
SET dominant
ALYW
1 G
R
Q DFN−8
S CASE 488AF NCP
7 COMPARATOR
3063
− ALYW
+ S 2
SET dominant G
Rs Q
R
0.15 W
OSCILLATOR D NCP3063x = Specific Device Code
6 0.2 V 3
Vin x=B
CT L A = Assembly Location
12 V + 47 mH
COMPARATOR CT L, WL = Wafer Lot
Cin + 1.25 V
220 mF 2.2 nF Y, YY = Year
REFERENCE
5
− REGULATOR Vout W, WW = Work Week
4
3.3 V / G = Pb−Free Package
800 mA (Note: Microdot may be in either location)
R1 R2 3.9 kW 470 mF +
2.4 kW Cout
ORDERING INFORMATION
See detailed ordering and shipping information in the package
Figure 1. Typical Buck Application Circuit dimensions section on page 16 of this data sheet.
ÇÇ Ç
Switch Collector
Switch Emitter Ipk Sense
ÇÇ Ç
2 7 Switch Emitter Ipk Sense
EP Flag
Timing Capacitor
ÇÇ Ç
Timing Capacitor 3 6 VCC VCC
Comparator GND Comparator
GND 4 5
Inverting Inverting
(Top View) Input (Top View) Input
NOTE: EP Flag must be tied to GND Pin 4
on PCB
Figure 2. Pin Connections Figure 3. Pin Connections
NCP3063
8 1
N.C. TSD Switch Collector
SET dominant
R
Q
S
COMPARATOR
7
Ipk Sense − 2
+ S
Q Switch Emitter
SET dominant
R
0.2 V
OSCILLATOR 3
6 CT Timing Capacitor
+VCC
COMPARATOR
1.25 V
+ REFERENCE
− REGULATOR
5 4
Comparator Inverting Input GND
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2
NCP3063, NCP3063B, NCV3063
PIN DESCRIPTION
Pin No. Pin Name Description
1 Switch Collector Internal Darlington switch collector
2 Switch Emitter Internal Darlington switch emitter
3 Timing Capacitor Timing Capacitor
Oscillator Input
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NCP3063, NCP3063B, NCV3063
ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, TJ = Tlow to Thigh [Note 5], unless otherwise specified)
Symbol Characteristic Conditions Min Typ Max Unit
OSCILLATOR
fOSC Frequency (VPin 5 = 0 V, CT = 2.2 nF, 110 150 190 kHz
TJ = 25°C)
IDISCHG / Discharge to Charge Current Ratio (Pin 7 to VCC, TJ = 25°C) 5.5 6.0 6.5 −
ICHG
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4
NCP3063, NCP3063B, NCV3063
450 190
400 CT = 2.2 nF
180
TJ = 25°C
350
170
FREQUENCY (kHz)
FREQUENCY (kHz)
300
160
250
150
200
140
150
100 130
50 120
0 110
0 1 2 3 4 5 6 7 8 9 10 11 12 1314 1516 1718 1920 3 7 12 16 21 25 29 34 38 40
Ct, CAPACITANCE (nF) VCC, SUPPLY VOLTAGE (V)
Figure 5. Oscillator Frequency vs. Oscillator Figure 6. Oscillator Frequency vs. Supply
Timing Capacitor Voltage
2.4 1.25
VCC = 5.0 V
2.2 VCC = 5.0 V
IE = 1 A 1.20
IC = 1 A
VOLTAGE DROP (V)
1.8 1.15
1.6 1.10
1.4
1.05
1.2
1.0 1.0
−50 0 50 100 150 −50 0 50 100 150
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 7. Emitter Follower Configuration Output Figure 8. Common Emitter Configuration Output
Darlington Switch Voltage Drop vs. Temperature Darlington Switch Voltage Drop vs. Temperature
2.0 1.5
1.9 VCC = 5.0 V 1.4 VCC = 5.0 V
1.8 TJ = 25°C 1.3 TJ = 25°C
VOLTAGE DROP (V)
1.7 1.2
1.6 1.1
1.5 1.0
1.4 0.9
1.3 0.8
1.2 0.7
1.1 0.6
1.0 0.5
0 0.5 1.0 1.5 0 0.5 1.0 1.5
IE, EMITTER CURRENT (A) IC, COLLECTOR CURRENT (A)
Figure 9. Emitter Follower Configuration Output Figure 10. Common Emitter Configuration
Darlington Switch Voltage Drop vs. Emitter Current Output Darlington Switch Voltage Drop vs.
Collector Current
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NCP3063, NCP3063B, NCV3063
VOLTAGE (V)
1.26 0.22
0.20
1.24 0.18
0.16
1.22 0.14
0.12
1.20 0.10
−40 −25 −10 5 20 35 50 65 80 95 110 125 −40 −25 −10 5 20 35 50 65 80 95 110 125
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 11. Comparator Threshold Voltage vs. Figure 12. Current Limit Sense Voltage vs.
Temperature Temperature
6.0
5.5
ICC, SUPPLY CURRENT (mA)
5.0
4.5
4.0
3.5
3.0 CT = 2.2 nF
Pin 5, 7 = VCC
2.5 Pin 2 = GND
2.0
3.0 8.0 13 18 23 28 33 38 43
VCC, SUPPLY VOLTAGE (V)
Figure 13. Standby Supply Current vs. Supply Voltage
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NCP3063, NCP3063B, NCV3063
INTRODUCTION
The NCP3063 is a monolithic power switching regulator controlled by the oscillator, thus pumping up the output filter
optimized for dc to dc converter applications. The capacitor. When the output voltage level reaches nominal,
combination of its features enables the system designer to the output switch next cycle turning on is inhibited. The
directly implement step−up, step−down, and voltage− feedback comparator will enable the switching immediately
inverting converters with a minimum number of external when the load current causes the output voltage to fall below
components. Potential applications include cost sensitive nominal. Under these conditions, output switch conduction
consumer products as well as equipment for industrial can be enabled for a partial oscillator cycle, a partial cycle
markets. A representative block diagram is shown in plus a complete cycle, multiple cycles, or a partial cycle plus
Figure 4. multiple cycles. (See AN920/D for more information).
1
Feedback Comparator Output
0
1
IPK Comparator Output
0
Timing Capacitor, CT
On
Output Switch
Off
Output Voltage
Startup Operation
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NCP3063, NCP3063B, NCV3063
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8
NCP3063, NCP3063B, NCV3063
CT
CT + 381.6 @ 10 *6 * 343 @ 10 *12
fosc
IL(avg) Iout
ǒ
t
Iout on ) 1
toff
Ǔ ǒ
t
Iout on ) 1
toff
Ǔ
Ipk (Switch) DI DI DI
IL(avg) ) L IL(avg) ) L IL(avg) ) L
2 2 2
RSC 0.20 0.20 0.20
Ipk (Switch) Ipk (Switch) Ipk (Switch)
L
ǒVin * VSWCE
DIL
* Vout
Ǔ ton ǒVin *DIVLSWCEǓ ton ǒVin *DIVLSWCEǓ ton
Vripple(pp)
DIL Ǹǒ 1
8 f CO
Ǔ ) (ESR)
2
2 [
ton Iout
CO
) DIL @ ESR [
ton Iout
CO
) DIL @ ESR
Vout
VTH ǒRR2 ) 1Ǔ VTH ǒRR2 ) 1Ǔ VTH ǒRR2 ) 1Ǔ
1 1 1
9. VSWCE − Darlington Switch Collector to Emitter Voltage Drop, refer to Figures 7, 8, 9 and 10.
10. VF − Output rectifier forward voltage drop. Typical value for 1N5819 Schottky barrier rectifier is 0.4 V.
11. The calculated ton/toff must not exceed the minimum guaranteed oscillator charge to discharge ratio.
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NCP3063, NCP3063B, NCV3063
R201 U201
8 N.C. SWC 1 +VOUT = +3.3 V / 800 mA
0R15 L201 47 mH
+VIN = +12 V 7 SWE 2
IPK 1
6 3
1 VCC TCAP D201 C206 J203
5 COMP GND 4 C203 +
J201 C205
0.1 mF
C201 + NCP3063 2.2 nF 1N5819 470 mF / 25 V J204
C202
220 mF / 50 V 1
0.1 mF
J202 GND
R203
1
GND 3K9 ±1%
R202
2K4 ±1%
Value of Components
Name Value Name Value
L201 47 mH, Isat > 1.5 A R201 150 mW, 0.5 W
D201 1 A, 40 V Schottky Rectifier R202 2.40 kW
C202 220 mF, 50 V, Low ESR R203 3.90 kW
C205 470 mF, 25 V, Low ESR C201 100 nF Ceramic Capacitor
C203 2.2 nF Ceramic Capacitor C202 100 nF Ceramic Capacitor
Test Results
Test Condition Results
Line Regulation Vin = 9 V to 12 V, Io = 800 mA 8 mV
Load Regulation Vin = 12 V, Io = 80 mA to 800 mA 9 mV
Output Ripple Vin = 12 V, Io = 40 mA to 800 mA ≤ 85 mVpp
Efficiency Vin = 12 V, Io = 400 mA to 800 mA > 73%
Short Circuit Current Vin = 12 V, Rload = 0.15 W 1.25 A
76
74
EFFICIENCY (%)
72
70
68
66
64
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
OUTPUT LOAD (Adc)
Figure 18. Efficiency vs. Output Current for the Buck
Demo Board at Vin = 12 V, Vout = 3.3 V, TA = 255C
Figure 17. Buck Demoboard Layout
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NCP3063, NCP3063B, NCV3063
L101 100 mH
R101 U101 +VOUT = +24 V / 350 mA
8 D101 1N5819
0R15 N.C. SWC 1 1
+VIN = +12 V 7 SWE 2
IPK J103
6 3 +
1 VCC TCAP C106 C105
5 COMP GND 4 C103
J101 0.1 mF 330 mF / 50 V
C101 + NCP3063 2.2 nF J104
C102
470 mF / 25 V 1
0.1 mF
J102 GND
R103
1
GND 18K0 ±1%
R102
1K0 ±1%
Value of Components
Name Value Name Value
L101 100 mH, Isat > 1.5 A R101 150 mW, 0.5 W
D101 1 A, 40 V Schottky Rectifier R102 1.00 kW
C102 470 mF, 25 V, Low ESR R103 18.00 kW
C105 330 mF, 50 V, Low ESR C101 100 nF Ceramic Capacitor
C103 2.2 nF Ceramic Capacitor C106 100 nF Ceramic Capacitor
Test Results
Test Condition Results
Line Regulation Vin = 9 V to 15 V, Io = 250 mA 2 mV
Load Regulation Vin = 12 V, Io = 30 mA to 350 mA 5 mV
Output Ripple Vin = 12 V, Io = 10 mA to 350 mA ≤ 350 mVpp
Efficiency Vin = 12 V, Io = 50 mA to 350 mA > 85.5%
90
89
88
87
EFFICIENCY (%)
86
85
84
83
82
81
80
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
OUTPUT LOAD (Adc)
Figure 21. Efficiency vs. Output Current for the Boost
Demo Board at Vin = 12 V, Vout = 24 V, TA = 255C
Figure 20. Boost Demoboard Layout
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NCP3063, NCP3063B, NCV3063
R501 U501
8 N.C. SWC 1
0R15
+VIN = +5 V 7 SWE 2
IPK
6 3
1 VCC TCAP
5 COMP GND 4 C503 L501
J501
D501
C501 + NCP3063 2.2 nF 22 mH 1N5819
C502
0.1 mF 330 mF / 25 V
J502 VOUT = −12 V / 100 mA
R503
1 1 J503
1K96 ±1% C506
GND C505
R502 +
0.1 mF 470 mF / 35 V
16K9 ±1% 1 J504
GND
Figure 22. Typical Voltage Inverting Application Schematic
Value of Components
Name Value Name Value
L501 22 mH, Isat > 1.5 A R501 150 mW, 0.5 W
D501 1 A, 40 V Schottky Rectifier R502 16.9 kW
C502 330 mF, 25 V, Low ESR R503 1.96 kW
C505 470 mF, 35 V, Low ESR C501 100 nF Ceramic Capacitor
C503 2.2 nF Ceramic Capacitor C506 100 nF Ceramic Capacitor
Test Results
Test Condition Results
Line Regulation Vin = 4.5 V to 6 V, Io = 50 mA 1.5 mV
Load Regulation Vin = 5 V, Io = 10 mA to 100 mA 1.6 mV
Output Ripple Vin = 5 V, Io = 0 mA to 100 mA ≤ 300 mVpp
Efficiency Vin = 5 V, Io = 100 mA 49.8%
Short Circuit Current Vin = 5 V, Rload = 0.15 W 0.885 A
52
50
48
EFFICIENCY (%)
46
44
42
40
38
36
0 20 40 60 80 100
OUTPUT LOAD (mAdc)
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NCP3063, NCP3063B, NCV3063
R2 1k Q1 D1
NTD18N06
IC1 NCP3063 C5 6n8
D
8 N.C. SWC 1
R7 6 1G
7 SWE 2
IPK
6 2 4
VCC TC 3 470 S
5 COMP GND 4
5 3
IC2 BC846BPD
C3 10n
R5 24k
C1 C2 C4 C6 C7 +
R3 R4 R8
M18 1k 1k
330m 100n 1n2 100n 330m
0V GND
Figure 25. Typical Boost Application Schematic with External NMOS Transistor
80
circuit is controlled from SWE Pin of the NCP3063 through
frequency compensated resistor divider R7/R8. The driver
78 IC2 is ON Semiconductor low cost dual NPN/PNP
76
transistor BC846BPD. Its NPN transistor is connected as a
super diode for charging the gate capacitance. The PNP
74 transistor works as an emitter follower for discharging the
72
gate capacitor. This configuration assures sharp driving
ILOAD = 350 mA edge between 50 − 100 ns as well as it limits power
70 consumption of R7/R8 divider down to 50 mW. The output
6 8 10 12 14 16 18 20
current limit is balanced by resistor R3. The fast switching
INPUT VOLTAGE (V) with low RDS(on) NMOS transistor will achieve efficiencies
Figure 26. Typical Efficiency for Application up to 85% in automotive applications.
Shown in Figure 25.
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NCP3063, NCP3063B, NCV3063
Q2 VOUT = 3V3/3 A
VIN = 8 − 19 V R1 50m NTGS4111P L1 10m
T1 6
R5 BC848CPD 2
1k
1
IC1 NCP3063 5
8 N.C. SWC 1 3 4
7 SWE 2
IPK R6
6 TC 3
VCC
5 COMP GND 4 22k
R2 1k7
C1 + C2 C5 C4 D1 C6 C7 +
R3 R8
100n 1k 2n2 470 6n8 100n
330m 1N5822 330m
0V GND
Figure 27. Typical Buck Application Schematic with External PMOS Transistor
85
a pulsed feedback voltage. It is recommended to use this
VIN = 8 V
pulsed feedback approach on applications with a wide input
80 voltage range, applications with the input voltage over
VIN = 18 V +12 V or applications with tighter specifications on output
75
ripple. The suitable value of resistor R6 is between
70 10k − 68k. The pulse feedback approach increases the
operating frequency by about 20%. It also creates more
65
regular switching waveforms with constant operating
60 frequency which results in lower output ripple voltage and
0 0.5 1 1.5 2 2.5 3 improved efficiency.
OUTPUT LOAD (Adc) The pulse feedback resistor value has to be selected so that
Figure 28. NCP3063 Efficiency vs. Output Current for the capacitor charge and discharge currents as listed in the
Buck External PMOS at Vout = 3.3 V, f = 220 kHz, electrical characteristic table, are not exceeded. Improper
TA = 255C selection will lead to errors in the oscillator operation. The
maximum voltage at the TC Pin cannot exceed 1.4 V when
implementing pulse feedback.
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NCP3063, NCP3063B, NCV3063
R1 VOUT = 3V3/1 A
VIN = 8 − 19 V Q1 NSS35200 L1 33m
150m
D2
R4
33
NSR0130
IC1 NCP3063
8 N.C. SWC 1
R5
7 SWE 2
IPK
6 TC 3 33
VCC
5 COMP GND 4
R3 1k7
D1 C5 C6 +
C1 + C2 C3
R2
100m 100n 1k 2n2 1N5819 100n 100m
0V GND
Figure 29. Typical Buck Application Schematic with External Low VCE(sat) PNP Transistor
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NCP3063, NCP3063B, NCV3063
R1
IC1 NCP3063
8 N.C. SWC 1
7 2 L1
IPK SWE
6 TC 3
VCC
5 COMP GND 4 R5
22k
R2 10R R4
C1 C2 C3 D1 C4
R3
4n7
0V 0V
Figure 31. Typical Schematic of Buck Converter with RC Snubber and Pulse Feedback
In some cases where there are oscillations on the output minimize the oscillation. Typical usage is shown in the
due to the input/output combination, output load variations Figure 31. C3 values can be selected between 2.2 nF and
or PCB layout a snubber circuit on the SWE Pin will help 6.8 nF and R4 can be from 10 W to 22 W.
ORDERING INFORMATION
Device Package Shipping†
NCP3063PG PDIP−8 50 Units / Rail
(Pb−Free)
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NCP3063, NCP3063B, NCV3063
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AJ
NOTES:
1. DIMENSIONING AND TOLERANCING PER
−X− ANSI Y14.5M, 1982.
A 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
8 5 PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
1 IN EXCESS OF THE D DIMENSION AT
4 MAXIMUM MATERIAL CONDITION.
−Y− K 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
MILLIMETERS INCHES
G
DIM MIN MAX MIN MAX
A 4.80 5.00 0.189 0.197
C N X 45 _ B 3.80 4.00 0.150 0.157
SEATING C 1.35 1.75 0.053 0.069
PLANE D 0.33 0.51 0.013 0.020
−Z− G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
0.10 (0.004) J 0.19 0.25 0.007 0.010
H M J K 0.40 1.27 0.016 0.050
D
M 0_ 8_ 0 _ 8 _
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
0.25 (0.010) M Z Y S X S
SOLDERING FOOTPRINT*
1.52
0.060
7.0 4.0
0.275 0.155
0.6 1.270
0.024 0.050
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NCP3063, NCP3063B, NCV3063
PACKAGE DIMENSIONS
8 LEAD PDIP
CASE 626−05
ISSUE L NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
8 5 2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
−B− Y14.5M, 1982.
1 4 MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 9.40 10.16 0.370 0.400
B 6.10 6.60 0.240 0.260
F C 3.94 4.45 0.155 0.175
NOTE 2 −A− D
F
0.38
1.02
0.51
1.78
0.015
0.040
0.020
0.070
L G 2.54 BSC 0.100 BSC
H 0.76 1.27 0.030 0.050
J 0.20 0.30 0.008 0.012
K 2.92 3.43 0.115 0.135
C L 7.62 BSC 0.300 BSC
M --- 10_ --- 10_
SEATING N STYLE 1:
PLANE PIN 1. AC IN
M 2. DC + IN
D K 3. DC - IN
4. AC IN
H G 5. GROUND
6. OUTPUT
0.13 (0.005) M T A M B M
7. AUXILIARY
8. VCC
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NCP3063, NCP3063B, NCV3063
PACKAGE DIMENSIONS
D A NOTES:
1. DIMENSIONS AND TOLERANCING PER
B L L ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
L1 TERMINAL AND IS MEASURED BETWEEN
ÉÉ
0.15 AND 0.30MM FROM TERMINAL TIP.
PIN ONE
REFERENCE E DETAIL A 4. COPLANARITY APPLIES TO THE EXPOSED
ÉÉ
OPTIONAL PAD AS WELL AS THE TERMINALS.
CONSTRUCTIONS 5. DETAILS A AND B SHOW OPTIONAL
2X 0.15 C CONSTRUCTIONS FOR TERMINALS.
MILLIMETERS
ÇÇÇ ÉÉÉ
2X 0.15 C DIM MIN MAX
TOP VIEW A3 A 0.80 1.00
EXPOSED Cu MOLD CMPD
ÇÇÇ
ÉÉÉ ÉÉÉ
ÇÇÇ
A1 0.00 0.05
A3 0.20 REF
ÇÇÇÇ
DETAIL B b 0.25 0.35
0.10 C D 4.00 BSC
D2 1.91 2.21
A A1 E 4.00 BSC
8X 0.08 C DETAIL B E2 2.09 2.39
(A3) ALTERNATE e 0.80 BSC
NOTE 4 A1 SEATING CONSTRUCTIONS K 0.20 −−−
C PLANE L 0.30 0.50
SIDE VIEW L1 −−− 0.15
D2 SOLDERING FOOTPRINT*
DETAIL A
ÇÇÇ
ÇÇ 8X L
2.21 8X
ÇÇÇ
ÇÇ
1 4
0.63
E2
K ÇÇÇÇ
8 5
8X b
4.30 2.39
e 0.10 C A B PACKAGE
OUTLINE
0.05 C NOTE 3
BOTTOM VIEW 8X
0.80 0.35
PITCH
DIMENSIONS: MILLIMETERS
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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