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MBB ATN+CX IDEAL (Seamless MPLS) Solution Clock Synchronization Implementation and Configuration

Copyright © 2014 Huawei Technologies Co., Ltd. All rights reserved.

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Implementation and Configuration Copyright © 2014 Huawei Technologies Co., Ltd. All rights reserved. www.huawei.com
Foreword  Among various communication networks, mobile networks have the highest requirements on clock frequency

Foreword

Among various communication networks, mobile networks have the

highest requirements on clock frequency synchronization. As networks are

evolving from circuit switched synchronous digital hierarchy (SDH) networks to packet switched IP networks, packet switched networks (PSNs) are required to have the clock and time synchronization capabilities,

accommodating the development trend to IP interfaces on IP backhaul networks and wide application of Ethernet access devices.

PSNs were designed to transmit packet services, and therefore do not have strict requirements on synchronization between network nodes. In other words, PSNs are asynchronous transport networks. However, a packet switched IP backhaul network requires both clock and time synchronization capabilities.

Copyright © 2014 Huawei Technologies Co., Ltd. All rights reserved.

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clock and time synchronization capabilities. Copyright © 2014 Huawei Technologies Co., Ltd. All rights reserved. Page2
Objectives  After completing this course, you will be able to:  Describe differences for

Objectives

After completing this course, you will be able to:

Describe differences for two clock deployment solutions.

Describe Synchronous Ethernet Clock Guideline.

Describe 1588v2 Time Synchronization Guideline.

Describe configuration Roadmap - IPRAN Area & IP Core.

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Roadmap - IPRAN Area & IP Core. Copyright © 2014 Huawei Technologies Co., Ltd. All rights
Contents 1. Inter-AS Clock Solution Deployment Overview 2. The Guidelines for Designing Clock 3. Configuration

Contents

1. Inter-AS Clock Solution Deployment Overview

2. The Guidelines for Designing Clock

3. Configuration Roadmap

4. Data Planning

Copyright © 2014 Huawei Technologies Co., Ltd. All rights reserved.

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Clock 3. Configuration Roadmap 4. Data Planning Copyright © 2014 Huawei Technologies Co., Ltd. All rights
Contents 1. Inter-AS Clock Solution Deployment Overview 2. The Guidelines for Designing Clock 3. Configuration

Contents

1. Inter-AS Clock Solution Deployment Overview

2. The Guidelines for Designing Clock

3. Configuration Roadmap

4. Data Planning

Copyright © 2014 Huawei Technologies Co., Ltd. All rights reserved.

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Clock 3. Configuration Roadmap 4. Data Planning Copyright © 2014 Huawei Technologies Co., Ltd. All rights

Inter-AS Clock Solution Deployment

Solution 1: The clock is deployed in the Solution 2: The clock is deployed

same way as in a metropolitan area network.

in centralized manner.

GPS GPS BITS BITS IP Core ABR1
GPS
GPS
BITS
BITS
IP Core
ABR1

1588v2

SyncE

GPS GPS BITS BITS 1588v2 SyncE MASG1 SGW/MME ABR2 MASG2
GPS
GPS
BITS
BITS
1588v2
SyncE
MASG1
SGW/MME
ABR2
MASG2

IPRAN

BITS BITS 1588v2 SyncE MASG1 SGW/MME ABR2 MASG2 IPRAN CSG Aggregation Access RSG2 ASG1 RSG2 ASG2

CSG

Aggregation Access RSG2 ASG1 RSG2 ASG2
Aggregation
Access
RSG2
ASG1
RSG2
ASG2

After comprehensive comparison of the two solutions, solution 1 is recommended for inter-AS LTE bearer solutions.

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recommended for inter-AS LTE bearer solutions. Copyright © 2014 Huawei Technologies Co., Ltd. All rights reserved.
Contents 1. Inter-AS Clock Solution Deployment Overview 2. The Guidelines for Designing Clock 3. Configuration

Contents

1. Inter-AS Clock Solution Deployment Overview

2. The Guidelines for Designing Clock

3. Configuration Roadmap

4. Data Planning

Copyright © 2014 Huawei Technologies Co., Ltd. All rights reserved.

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Clock 3. Configuration Roadmap 4. Data Planning Copyright © 2014 Huawei Technologies Co., Ltd. All rights

Synchronous Ethernet Clock

Synchronous Ethernet Clock Copyright © 2014 Huawei Technologies Co., Ltd. All rights reserved. Page8

Copyright © 2014 Huawei Technologies Co., Ltd. All rights reserved.

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Synchronous Ethernet Clock Copyright © 2014 Huawei Technologies Co., Ltd. All rights reserved. Page8

1588v2 Time Synchronization

1588v2 Time Synchronization Copyright © 2014 Huawei Technologies Co., Ltd. All rights reserved. Page9

Copyright © 2014 Huawei Technologies Co., Ltd. All rights reserved.

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1588v2 Time Synchronization Copyright © 2014 Huawei Technologies Co., Ltd. All rights reserved. Page9
Contents 1. Inter-AS Clock Solution Deployment Overview 2. The Guidelines for Designing Clock 3. Configuration

Contents

1. Inter-AS Clock Solution Deployment Overview

2. The Guidelines for Designing Clock

3. Configuration Roadmap

4. Data Planning

Copyright © 2014 Huawei Technologies Co., Ltd. All rights reserved.

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3. Configuration Roadmap 4. Data Planning Copyright © 2014 Huawei Technologies Co., Ltd. All rights reserved.

E0/3/0

G1/0/1

G1/0/2

E0/3/0

Configuration Roadmap - IPRAN

Area

Last Mile

G1/0/2 E0/3/0 Configuration Roadmap - IPRAN Area Last Mile E1 BTS FE/GE NodeB Master BITS CSG1

E1

BTS

E0/3/0 Configuration Roadmap - IPRAN Area Last Mile E1 BTS FE/GE NodeB Master BITS CSG1 CSG2

FE/GE

NodeB

Master BITS

- IPRAN Area Last Mile E1 BTS FE/GE NodeB Master BITS CSG1 CSG2 ASG3 ASBR1 E0/3/1

CSG1

- IPRAN Area Last Mile E1 BTS FE/GE NodeB Master BITS CSG1 CSG2 ASG3 ASBR1 E0/3/1
- IPRAN Area Last Mile E1 BTS FE/GE NodeB Master BITS CSG1 CSG2 ASG3 ASBR1 E0/3/1

CSG2

ASG3

ASBR1

Mile E1 BTS FE/GE NodeB Master BITS CSG1 CSG2 ASG3 ASBR1 E0/3/1 G1/0/1 G1/0/0 G1/0/0 G1/0/0
Mile E1 BTS FE/GE NodeB Master BITS CSG1 CSG2 ASG3 ASBR1 E0/3/1 G1/0/1 G1/0/0 G1/0/0 G1/0/0

E0/3/1

G1/0/1

G1/0/0

G1/0/0

G1/0/0

G1/0/0

ASBR1 E0/3/1 G1/0/1 G1/0/0 G1/0/0 G1/0/0 G1/0/0 E0/3/1 G1/0/1 ASG4 A S B R 2 Synchronous
ASBR1 E0/3/1 G1/0/1 G1/0/0 G1/0/0 G1/0/0 G1/0/0 E0/3/1 G1/0/1 ASG4 A S B R 2 Synchronous

E0/3/1

G1/0/1

G1/0/1 G1/0/0 G1/0/0 G1/0/0 G1/0/0 E0/3/1 G1/0/1 ASG4 A S B R 2 Synchronous Ethernet Backup

ASG4

G1/0/0 G1/0/0 G1/0/0 G1/0/0 E0/3/1 G1/0/1 ASG4 A S B R 2 Synchronous Ethernet Backup BITS

ASBR2

G1/0/0 G1/0/0 G1/0/0 E0/3/1 G1/0/1 ASG4 A S B R 2 Synchronous Ethernet Backup BITS Copyright
G1/0/0 G1/0/0 G1/0/0 E0/3/1 G1/0/1 ASG4 A S B R 2 Synchronous Ethernet Backup BITS Copyright

Synchronous Ethernet

Backup BITS

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A S B R 2 Synchronous Ethernet Backup BITS Copyright © 2014 Huawei Technologies Co., Ltd.

Configuration Roadmap - IP Core

Master BITS Clock pri 10 ASBR3 Clock pri 10 MASG1 GE1/0/1 GE1/0/0 GE2/0/1 Clock pri
Master BITS
Clock pri 10
ASBR3
Clock pri 10
MASG1
GE1/0/1
GE1/0/0
GE2/0/1
Clock pri 20
Clock pri 10
GE2/0/1
GE1/0/0
GE1/0/1

ASBR4

Clock pri 10

Clock pri 10 GE2/0/1 GE1/0/0 GE1/0/1 ASBR4 Clock pri 10 MASG2 Clock pri 20 Clock Tracking

MASG2

Clock pri 20

GE1/0/0 GE1/0/1 ASBR4 Clock pri 10 MASG2 Clock pri 20 Clock Tracking Path Backup B I

Clock Tracking Path

Backup BITS

Clock pri n Priority of a reference clock source at a port

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Priority of a reference clock source at a port Copyright © 2014 Huawei Technologies Co., Ltd.
Contents 1. Inter-AS Clock Solution Deployment Overview 2. The Guidelines for Designing Clock 3. Configuration

Contents

1. Inter-AS Clock Solution Deployment Overview

2. The Guidelines for Designing Clock

3. Configuration Roadmap

4. Data Planning

Copyright © 2014 Huawei Technologies Co., Ltd. All rights reserved.

Page13

3. Configuration Roadmap 4. Data Planning Copyright © 2014 Huawei Technologies Co., Ltd. All rights reserved.

Parameters Planning - Synchronous Ethernet Clock

Device

Port

Priority

ASBR1

CLK0

5

 

G1/0/0

10

ASG3

G1/0/0

5

 

G1/0/1

10

CSG1

E0/3/1

5

 

E0/3/0

10

CSG2

E0/3/0

5

 

E0/3/1

10

ASG4

G1/0/1

5

 

G1/0/0

10

ASBR2

G1/0/0

5

 

CLK0

10

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ASBR2 G1/0/0 5   CLK0 10 Copyright © 2014 Huawei Technologies Co., Ltd. All rights reserved.

Parameters Planning - 1588v2 Time Synchronization

Configuratio n Item

Parameter

Value

Remark

s

 

Clock domain

9

All devices that synchronize time with one another using IEEE 1588v2 packets must belong to the same IEEE 1588v2 clock domain.The value range is 0255. The default value is 0.

Basic

Clock type

BC

The clock type is set to BC on all of the CSGs, AGGs, and RSGs.

parameters

Delay measuremen t mechanism

Pdelay

-

Pdelay

One-step

 
   

ASBR1

The smaller value, the higher priority. Both ASBR1 and ASBR2 are connected to an external clock source. The priority of clocks on ASBR1 and ASBR2 must be the highest on the network, so that NEs can trace the external

clock source of ASBR2 when the external clock source of ASBR1 fails.

Clock priority

Local

6

reference

ASBR2

 

7

An IEEE 1588v2 device will select the following clocks in a descending order of priority during dynamic source selection based on the BMC algorithm: priority 1 > clock- class > clock-accuracy > priority 2.

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class > clock-accuracy > priority 2 . Copyright © 2014 Huawei Technologies Co., Ltd. All rights
Summary 1. Differences for two clock deployment solutions. 2. Synchronous Ethernet Clock Guideline. 3.

Summary

1.

Differences for two clock deployment solutions.

2.

Synchronous Ethernet Clock Guideline.

3.

1588v2 Time Synchronization Guideline.

4.

Configuration Roadmap - IPRAN Area & IP Core.

Copyright © 2014 Huawei Technologies Co., Ltd. All rights reserved.

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Roadmap - IPRAN Area & IP Core. Copyright © 2014 Huawei Technologies Co., Ltd. All rights

Thank you

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