IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS –II: EXPRESS BRIEFS, VOL. , NO.

, MAY 2018 1

Analysis and Comparison of High-Resolution GS/s

Samplers in Advanced BiCMOS and CMOS
Deeksha Lal, Graduate Student Member, IEEE, Ahmed M. A. Ali, Senior Member, IEEE,
and David S. Ricketts, Senior Member, IEEE

Abstract—High-speed and high-resolution ADCs (10+ bits) are Envelope

180 Pipelined ADCs
essential components of modern wireless communication systems Calibrated Pipelines
and mmWave radios. Their performance is often limited by the GS/s SHAs
170
noise and distortion from the front-end samplers, the design BiCMOS ADCs
ADCs with fs>20GS/s
of which can be challenging. Modern ADC design has moved
160

heavily to scaled CMOS technologies due to its attractive digital
and integration capabilities, but these processes face challenges
of high fabrication costs, and diminishing analog performance
that has to be bolstered by extensive digital calibration. On
the other hand, BiCMOS processes have advanced and scaled
sufficiently that they may be able to offer the best of the mixed
signal world. This paper examines, both theoretically and through
simulations, the design of samplers for high-speed, low-distortion
in CMOS and BiCMOS for GS/s ADCs. Two fully differential
samplers, with an equivalent sampling frequency of 5GS/s and
an input frequency range of up to 10GHz, are designed in a
90nm BiCMOS and a 28nm CMOS process respectively, and their
distortion performance is analyzed, simulated and compared.
Index Terms—28nm CMOS, 90nm SiGe BiCMOS, ADC, HD3,
mmWave, Sample and Hold Amplifier, Sampler, SFDR, SHA,
switched-capacitor
I. I NTRODUCTION
W IRELESS communication technologies of the near
future are being enabled by the mmWave spectrum,
which provides faster data rates. For very high performance
radios, challenges still exist in meeting the diverse dynamic
range, bandwidth and integration needs, particularly for
Analog to Digital Converters (ADCs) in applications requiring
10 or more bits of resolution. A plot of state-of-the-art ADCs
and samplers based on the Schreier Figure of Merit (FoM)
is shown in Fig. 1 [1]. Currently, ADCs are predominantly
designed in CMOS, due to their high fT and on-chip
calibration capabilities that can enable low-power and high
performing designs. Bipolar designs continue to show some
of the fastest performance at moderate resolutions [2], [3], but
they can be power hungry. Advanced BiCMOS technologies
now offer the synthesis of low-power designs from CMOS
architectures (Switched-Capacitor (SC) circuits) with the low
distortion capabilities of bipolar amplifiers and fT sufficient
to compete with emerging scaled CMOS designs [4].
The bottleneck for high-speed and high-resolution ADC
design is typically the front-end Sample and Hold Amplifier
(SHA). For these applications, several architectures for
Manuscript received March 2, 2018. This work is an expanded version of
the one accepted to the International Symposium of Circuits and Systems,
Florence, Italy, May 27-30, 2018.
D. Lal and D.S. Ricketts are with the Department of Electrical and
Computer Engineering, North Carolina State University, Raleigh, NC 27695
USA (e-mail: deeksh@ncsu.edu).
A.M.A. Ali is with Analog Devices Inc., Greensboro, NC 27409 USA.
FOMS,hf [dB]
Schreier Figure-of-Merit (FoM)
⎛
FoM= 10 log ⎜ 2ENOB
P ⎞
150 ⎟
⎝2 ERBW ⎠
⎛ ERBW ⎞
= SNDR +10 log ⎜
140 ⎟
⎝ P ⎠
130
Target Space
120
1.E+02 1.E+04 1.E+06 1.E+08 1.E+10 1.E+12
fsnyq [Hz]
Fig. 1. A state-of-the-art comparison using the Schreier FoM described with
data on ADCs and samplers published since 2000 [1].
samplers have demonstrated good performance, including
switched Emitter Followers (SEFs) in SiGe HBT processes
[2] and InP processes [5], Switched Source Followers (SSFs)
in CMOS [6], base-collector diodes in InP HBT processes [7],
and SC SHAs [8] or THAs [9] in CMOS. SEFs utilizing HBTs
in SiGe and InP processes can be very high performance, but
at the cost of high power consumption. InP processes face
challenges of digital integration as compared to Si processes.
SSFs and SC designs implemented in scaled CMOS can be
lower power, but require additional linearization techniques to
overcome low intrinsic gains in input buffers. An integrated
solution may be to design SC SHAs in BiCMOS processes.
This work compares two SC SHA designs in 28nm CMOS
and 90nm BiCMOS processes.
A SC SHA, as shown in Fig. 2(iv), consists of an
input buffer, sampling/holding implemented through charge
storage on a capacitor (CS ) and its redistribution across an
operational transconductance amplifier (OTA), and an output
buffer. The input buffer and the sampling switches are the
core components of the sampler. The sampler, together with
the OTA, represents the core of the ADC (the Multiplying
DAC, MDAC). A buffer is used at the output to simulate
a real, low-impedance output stage for 50Ω measurement in
case the sampler circuits are fabricated on chip. The SHA
reduces the design specifications of slew rate, bandwidth and
timing mismatches for the following stages of the ADC, at
the possible cost of distortion, noise and power deterioration
[10]. The input buffer is necessary to provide a low impedance
output node that drives CS (which can be large depending
on the noise/linearity specifications), and minimize kickback
distortion from the sampling process. The primary sources
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(i) Case 1: (ii) Case 2a: (v) Key: (vi) Timing Diagram
a. Sample/Hold 100ps(5GHz)
1 CS
1 CS 1 switching using op-amp: Φ
2 Φ1S
CS CS
Real IB Ideal IB Real OB 2ns(250MHz)
Φ1S Φ1A Φ1A
Real Sample/Hold Switching CS
Φ1B 4ns
(iii) Case 2b: (iv) Case 3: Φ1B
b. Behavioral model
1 of op-amp: Φ2 Φ2
CS 1 1
Ideal IB
CS + +
Real IB Real OB gM rload cload
- IB: Input Buffer
Real always-on -
Φ2 OB: Output Buffer
sampling switches Real Sample/Hold Switching

Fig. 2. Block diagrams for the four test-benches simulated to analyze the performance of SHAs in BiCMOS and CMOS. (i) Case A simulates buffers driving
450fF of CS . (ii) Case 2a simulates the switching distortion, (iii) Case 2b simulates tracking distortion for always-on switches for analyzing results from (ii)
and (iv) Case 3 shows the complete SHA. (v) shows the (a) sample/hold switching circuitry and (b) the behavioral model of the OTA used to simulate SHAs
in Cases 2a and 3. Timing diagram for switching is shown in (vi). All circuits are simulated differentially and are shown single-ended for simplicity.

of distortion in an ADC include the third-order non-linearity II. T HEORETICAL CONSIDERATIONS FOR HD3 AND SNR
(HD3) from the input buffer driving the CS , distortion from The sampling distortion in SHAs originates from the
the sampling process, and spurs from the quantization process. input buffer, the input switches, and their mutual interaction.
The front-end SHA contributes largely to the first two. The Switching non-linearity has two primary causes. Firstly, the
second-order non-linearity can be reduced through differential switches have finite and often variable on-resistance (Rsw )
circuit implementations. and capacitance, which affects the 3-dB tracking bandwidth
Fig. 1 shows few moderate to high resolution ADCs in (Bin ) as shown in (1) [10].
the multi-GS/s range [11]–[13], however research on GS/s
1
SHAs has been pushing state-of-the-art [2], [3], [5]–[7]. There Bin = (1)
are fewer BiCMOS ADCs - this is partly due to the move 2πRsw CS
to highly scaled CMOS processes for GHz ADCs. There Secondly, input-dependent charge is expelled from the
are many high-speed Time-Interleaved (TI) pipelined ADCs switch during the transition from on to off (also known as
pushing the FOM envelope. An example is the 8-bit 20GS/s kickback distortion).
80x interleaved pipelined ADC in 0.18um CMOS [11]. More Buffer non-linearity occurs due to the current drawn to
recently, the performance has improved to 12-bit 10GS/s charge CS , and the combined finite output impedance from
8x interleaved pipelined ADC in 28nm CMOS [12]. The the follower device and the current source. For an Emitter
performance of interleaved ADCs is limited by mismatches Follower (EF) driving CS , the Gain Bandwidth (GBW)
of offset, gain, and timing bandwidth, and nonlinearity, response is determined as shown in (2). This reduces to a
particularly from the front-end SHA [14]. The sampling relationship between the collector current, IC , the thermal
distortion is lowered in scaled MOS processes due to faster voltage VT and CS .
switches, but is traded off with buffer distortion due to
gM IC 1
dwindling RF performance from lower device intrinsic gains GBW =
= . (2)
in very short channel devices. Complex digital calibration CS VT CS
techniques, leveraging superior CMOS switches, have been For this buffer, the magnitude of HD3 can be derived as
developed to linearize or reduce ADC errors, but the issue of in (3), where ZE is the impedance at the emitter and Vin is
high fabrication expense due to increasing mask costs remains. the input amplitude [15]. ZE is defined to be the impedance
This work compares SHAs, designed in advanced BiCMOS of the current source in parallel with the output impedance of
and CMOS processes, that can be used as front-ends of GS/s the follower device (4). For high frequency applications, and
interleaved or non-interleaved ADCs. The target space for if the output resistance RE is very high, ZE reduces to just a
this is outlined in Fig. 1, for SHAs with sampling frequency CS dependence.
>1GS/s, where the availability of low buffer distortion due to 2
1 Vin 1
high intrinsic gain Heterojunction Bipolar Transistors (HBTs) HD3 = . 2. (3)
12 VT (gM ZE )3
in BiCMOS, along with the digital benefits of integrated
CMOS, may be advantageous. Previously this space has been 1 1
where ZE = RE || ≈ (4)
difficult to exploit, since older BiCMOS processes integrated jωCS jωCS
CMOS that was much slower than its bipolar counterpart, Substituting the value of ZE from (4) in (3) and re-writing
however GlobalFoundries’ 90nm BiCMOS process has made CS in terms of the GBW from (2), we get
both CMOS and HBTs available at 90nm. This technology
2  3
and TSMC’s 28nm CMOS process are used to design SHAs

1 Vin 2πfin
in this work, and compare their performances. HD3 = k ∗ . . (5)
12 VT GBW

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2.9V
VG3 R2
VB2 2.5V N3
R1 R2=150! VG2 R2
50! N2
VIN+ Q1 VG1
VOUT+ R2
IC VIN+ N1
CR VOUT+
Q2 CS I IC
345fF VB1 L
CR VG4 N4 CS I
200fF L
(a) VG1 N1 IBIAS
12mA VG5 N5
IBIAS
12mA
VG6 N6
CS = 450fF

(b)
Fig. 3. (a) Plot showing (i) variation of HD3 over frequency based on
(5), (ii) simulated HD3 of an EF in 90nm BiCMOS that compares well
with (ii), and (iii) for every 100fF increase in CS , HD3 drops by 5dB,
demonstrating the trade-off with kT/C. (b) Variation of quantization noise
and kT/C components of SNR where (i) at higher resolutions, kT/C dominates
SNR and (ii) decreasing it by increasing CS degrades HD3 in Fig. 3(a).
where k is a correction factor. HD3 in (5) is decided
by Vin , which is determined by the system specifications,
and the GBW, which is limited by CS . A similar analysis
has been shown in [16]. The simulated results for an
EF designed in 90nm BiCMOS (without any distortion
linearization techniques applied) and k =1.17 agree well
with (5) (Fig. 3(a)), except at 1GHz, where the SFDR is
predicted to be 110dB-123dB. This is because the ideal model
addresses only the major distortion contributor(s) and trends,
and neglects secondary factors like non-linear parasitics and
kickback, that put an upper limit on the achievable SFDR.
High fT processes have lower HD3, since GBW is a
function of the former. To lower HD3 through design for
higher GBW, low CS and larger gM would be necessary.
EF of Bipolar processes are superior in gM as compared
to Source Followers (SFs) designed in CMOS, which makes
BiCMOS processes better candidates for low distortion design.
On the other hand, lowering CS degrades SNR due to
increase in thermal noise, kT/C. For high resolution ADCs,
the overall SNR is generally limited by kT/C noise, and
not by quantization noise, since reducing the latter by 6dB
through each additional bit is less expensive, as demonstrated
in Fig. 3(b). This results in a high value of CS for converters
that require greater than 10 bits of resolution, and thus presents
a significant challenge for high-speed designs.
III. SHA COMPARISON FOR B I CMOS AND CMOS
A. System Design
To compare the performance for SHAs in 90nm BiCMOS
and 28nm CMOS, a SHA circuit as shown in Fig. 2(iv) is
designed in each process. For this SC sampler architecture,
typically the sampling (Φ1S , Φ1A , Φ1B ) and holding functions
(Φ2 ), as shown in Fig. 2(v)(a), would be clocked at the same
frequency. However, to reduce the complexity of the test
(a) (b)
Fig. 4. Circuit schematic for (a) an Emitter Follower in 90nm BiCMOS and
(b) a Source Follower in 28nm CMOS.
platform while retaining the performance and functionality of
a high speed SHA, the holding function is implemented at a
much slower speed (250 MS/s for Φ1A , Φ1B and Φ2 ) than
the sampling function (5GS/s for Φ1S ) (Fig. 2(vi). This is
typically true for first-rank samplers in TI systems, where the
input samples acquired at the ADC sampling frequency fS are
processed by the following n-interleaved stages at a slower
frequency, fS /n. The sampling switch clock, Φ1S , has a width
of 100 ps, which is the equivalent of a 5GS/s sample clock
with a 50% duty cycle, while the holding clocks have a width
of 2 ns.
Since the OTA in feedback implements the hold
functionality at a slower frequency, its contribution to the
overall distortion is minimized, allowing for a more accurate
evaluation of the 5GS/s sampler. A behavioral model of an
OTA is used as shown in Fig. 2(v)(b), where specifications
such as GBW and slew rate can be set using the resistor
rload and capacitor cload , and a gM cell. In this behavioral
model, ideal switches are needed to disconnect and connect the
OTA in sample and hold modes respectively. An ideal balun is
used to convert to differential output. Based on the SFDR and
SNR analysis in the previous section, a CS value of 450fF is
chosen, for a resolution of 12-14 bits while ensuring that the
quantization noise is at least 10dB below thermal noise. The
estimated SNR is 70dB. All simulations are carried out for an
input signal amplitude of 1Vppd .
B. Circuit Design
The input buffers are designed to be an EF in BiCMOS
(Fig. 4(a)) and a SF in CMOS (Fig. 4(b)). They drive CS ,
which charges through a non-linear current IL , which is a
major source of HD3. Linearization for this is performed by
supporting IL partly through IC , via a replica capacitive load,
CR , connected between the input and the emitter/source of the
current load [8]. The base/gate of the buffers are matched to
50Ω of the source through resistors.
The BiCMOS input buffer in Fig. 4(a) uses an HBT-NFET
cascode circuit for the current biasing, such that output
resistance RE is maximized (as in (4)) by exploiting the high
gM of the HBT and the high ro of the NFET [17]. For the
SF (Fig. 4(b)), a three-tier cascode is used for high output
impedance. The primary source of HD3 in a SF is channel

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(a)
(b)
(c)
Fig. 5. Simulation results showing (a) comparison of SFDR for buffer
circuits driving capacitance CS (no switches) (b) SFDR using bootstrapped
switches driven by ideal buffers (c) SFDR for overall SHA performance using
real circuit buffers and switches.
length modulation, which is especially prominent for short
channel devices. To reduce this effect, the drain of N1 can
be buffered from its gate using two SF buffers, N2 and N3 ,
capacitively coupled to the input signal at the gate [8][18].
When sampling is implemented (Fig. 2(v) (a)), the switch
clocked at Φ1S is bootstrapped to reduce tracking distortion
through constant VGS , and reduce kickback distortion. Bottom
plate sampling is used by turning off switches clocked at Φ1A
and Φ1B before Φ1S , thus reducing the input-dependence of the
stored charge. The circuits designed in both technologies have
been optimized for the best achievable SFDR performance. All
circuits are fully differential. The output buffer is designed as
an EF or SF with high bias current.
C. Simulation Methodology
To compare and contrast methodically the distortion
introduced by the input buffer and the sampling switches
through the sampler, simulations for four cases are performed
(Fig. 2(i)-(iv)). First, HD3 of the input buffers driving CS
is simulated (Case 1) to determine the upper limit for SFDR,
since the resolution cannot be higher than the performance
of the first stage. In Case 2a, to analyze distortion due to
sampling switches, all the switches along with an ‘ideal’ input
buffer and a real output buffer are simulated. The input buffer
is an ideal voltage controlled voltage source that includes the
expected buffer output loss and a series resistor to emulate
its output impedance, 1/gM . To further investigate the results
from Case 2a, Case 2b is created to delineate the effect of Bin
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4
(a)
(b)
(c)
Fig. 6. Simulation results for Case 2b, where the buffer is driving CS using
switches that are always-on. (a) Tracking BW versus input switch width, (b)
SFDR versus input switch width, (c) SFDR versus input frequency for the
optimum switch width. This is SFDR during tracking with no switching. The
actual overall SFDR is shown in Fig. 5(c).
and kickback distortion on switch distortion, where the input
buffer drives CS with sampling switches φ1S and φ1A that
are always-on. Case 3 simulates the entire SHA, with the real
input buffer, sample/hold switches, and the real output buffer.
D. Simulation Results and Discussion
Fig. 5(a) shows the SFDR simulated for Case 1. The solid
lines plot the SFDR when CR (see Fig. 4) is used, and the
BiCMOS design outperforms the CMOS buffer over all input
frequencies up-to 10GHz. This matches the prediction from
(5), since the gM , output impedance, and linearity of the HBT
surpass that of the NFET. The dotted lines show the SFDR
where CR has been disconnected. Even though the SFDR is
higher at 1-2GHz, it falls rapidly, and is 30dB (BiCMOS)
to 12dB (CMOS) lower at its minimum. This demonstrates
that CR linearizes the natural distortion of the input buffer,
especially at higher frequencies. This effect is more prominent
for BiCMOS due to its ability to sustain a larger CR of 345fF,
as shown by the very flat SFDR response. The addition of CR
directly degrades the input bandwidth of the buffer - however,
since the input bandwidth of the EF without CR (32GHz) is
much larger than that of the SF (25GHz), the EF can use a
larger CR , and thus benefit from greater SFDR, than the SF.
The distortion for Case 2a, as shown in Fig. 5(b), shows
CMOS switches (W/L = 57um/30nm) performing better than
the BiCMOS switches (W/L = 130um/100nm) over almost
all frequencies, except at 1-2GHz. This is likely due to the
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TCSII.2018.2822785, IEEE
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high Bin of 28nm switches (see later text) and reduced
charge-injection and parasitic coupling as a result of the
smaller absolute device size of the switches in 28nm CMOS.
The SFDR for Case 3, the overall SHA performance,
is shown in Fig. 5(c). The CMOS SHA shows better
performance, however, the BiCMOS SFDR is within 8dB of
the CMOS at 3-6 Ghz and within 3 dB from 7-10 GHz. It is
seen that at 1GHz, the CMOS performance is better than both
Fig. 5(a) and Fig. 5(b), which might be due to some distortion
cancellation. The poor performance of the BiCMOS design at
1 GHz is due to the frequency-dependent loading effect of the
switch on the buffer, that causes significantly worse distortion
at this particular frequency.
Case 2b is used to further investigate the relative
contribution of kickback distortion and finite Bin on the
sampling switch distortion as in Fig. 5(b). Fig. 6(a) plots the
simulated Bin for Case 2b versus unit width of always-on
switches (unit width for CMOS is 97µm, for BiCMOS is
130µm). Fig. 6(b) plots SFDR for Cases 2a and 3 at 4GHz over
switch width, i.e., SFDR is compared when the switch sizing
is swept for two SHAs, one each with an ideal and real input
buffer respectively. The bandwidth saturates to 12.8GHz and
18.5GHz for BiCMOS and CMOS processes respectively after
unit width is reached. After unit width, it is seen that SFDR
reduces, which indicates that the best tracking performance is
achieved for maximum Bin and unit width switch sizing, and
that another distortion factor must be dominating the sampling
switch performance seen in Fig. 5(b). This factor may be
charge injection and parasitic coupling as the absolute size
of the devices becomes larger. In Fig. 6(c) the sizing for peak
tracking SFDR in Fig. 6(b) is used to simulate tracking SFDR
for Case 2b over frequency. Surprisingly, 28nm switches show
worse tracking SFDR with increasing frequency than 90nm
switches - contrary to the results of Fig. 5(b). This indicates
that even though 90nm switches have better tracking SFDR,
they have worse kickback distortion, since they are 6x larger
in area.
A comparison of the input buffers (Fig. 4) shows that the
power consumption of the CMOS buffer is very similar to
that of the BiCMOS buffer (34.8mW and 34mW respectively).
This is because both high bias current and a three-tier cascode
structure with drain buffering (that entails a higher VDD) are
necessary for the SF to compensate for its low gM , and achieve
optimum SFDR performance. This performance is still lower
than the linearity of the EF, which benefits from larger intrinsic
gain, and this reinforces the inference from (5) that higher gM
devices have lower HD3. Secondly, even though the 28nm
switches are smaller in area and size than the 90nm switches,
the CMOS input buffer would likely consume larger area due
to the six FETs, their corresponding biasing circuitry, and
interconnects. For sampler circuits, since a behavioral model
of an OTA is used, a direct comparison of area and power is
out of the scope of this paper.
IV. C ONCLUSION
SHAs in 90nm BiCMOS and 28nm CMOS have been
designed, simulated and compared. It is demonstrated that
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5
although BiCMOS buffers are superior to CMOS buffer
designs, 90nm switches are worse in switching distortion,
since they must be significantly larger to achieve comparable
performance. Overall, the CMOS SHA is shown to have
better performance, but the BiCMOS performance is relatively
close. These results show the potential of advanced BiCMOS
processes in competing with highly scaled CMOS technologies
in the design of high-speed, high-resolution ADCs. In order to
take full advantage of the benefits of the low distortion buffers
possible in BiCMOS, the switch properties of the CMOS
devices in BiCMOS need to be further improved.
ACKNOWLEDGMENT
The authors would like to thank Analog Devices Inc. for
collaboration opportunities and training.
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