ANAND INSTITUTE OF HIGHER TECHNOLOGY

Kazhipattur-603 103
28/11/07
Department of ECE

UNIVERSITY QUESTUON BANK &ANSWERS

Subject: Microprocessors & Microcontrollers Code: CS 1304

Staff Name: A.vinodh Kumar Branch: IT
Designation: Lecturer Semester: III
UNIT 1

PART A
1. How address and data lines are demultiplexed in 8085? (May/ June 2007 CSE)

Address and data bus are demultiplexed using latches.(8282/8283)

2. .What is the function performed by SIM instruction in 8085? (May/ June 2007 CSE)

SIM is used to mask the hardware interrupts RST 7.5, 6.5, 5.5.It also used to

Send data through SOD line.

3. How the multiplexed address/data bus (AD7-AD0) IN 8085 is splitted into

address bus(A7-AO) and (D7-D0) ? (MAY/JUNE 2007 –IT)

4. List the different flags affected by the arithmetic and logic operations (NOV/DEC-2007,
CSE, regulation 2004)
Sign flag, zero flag, and auxiliary flag, and parity flag, carry flag

5. List the register set available in 8085? (NOV/DEC-2007,MCA-R 2005)

Temporary register, flag register, stack pointer (sp), program counter (pc)
, Z, A, B, C, D, E, H, L registers

6. How are the instructions of 8085 classified? (NOV/DEC-2007, MCA-R 2005)

Data transfer operations
Arithmetic operations

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 Logical operations
Branch operations
Stack, input/output and machine control operations.

7. Compare 8085 and 8086 flag registers. (NOV/DEC-2007, MCA-regulation 2005)

8085 flag register

It is an 8-bit register, in which five of the bits carry significant information in the form of
flags: s(sign flag),z(zero flag),AC(auxiliary carry flag),P(parity flag) and CY(carry flag)

8086 flag register in 8086 flag register contain nine active flags. Carry flag, parity flag.
Auxiliary carry flag for BCD, zero flag, sign flag, single step trap, interrupt enable,
string direction, overflow.

8. Write Briefly on data bus ,control bus ,of 8085 processor (MAY /JUNE 2007,CSE)

Data bus is used to transfer data between the CPU, Memory and I/O devices. The
Control Bus is used to carry necessary control signals.

9. what are the instructions that affect the sequence flow of an 8085 assembly language
Program. (MAY 2007 ECE)
1. All jump instructions
2. call instructions

10. What is interrupt vectoring? (MAY 2007 ECE)

Each interrupt is having a unique address for their function. If the particular
interrupt is called program control will go to the specific address and it will execute that
code.

11. What are the different memory mapping schemes? Give any one advantage and
disadvantage for each?
Memory Mapped 1/0
1. 16-bit address is allotted to
an I/O device
2. The devices are accessed by
I/O read or I/O writes cycle.
3. All instructions related to
memory can be used for
(Nov 2005 ECE)
Standard 1/0 mapped 1/0
1. 8 -bit address is allotted to an I/O
device.
2. The devices are accessed by
Memory read or memory writes
cycle.
3. Only IN and OUT instructions
can be used for data transfer.

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 data transfer.
4. A large number of I/O ports 4. Only 256 ports can be interfaced.
Can be interfaced.

12. Write an 8085 assembly language program, which checks to see if the number is even or
odd and if it is odd returns a 0 in B register else returns a 1. (Nov 2005 ECE)

PUSH PSW
POP B
MOV A, C
STA 2000H.
HLT

13. When the READY signal of 8085 processor is sampled by the processor?
(Apr 2005 ECE)

The READY is an input signal that is can be used by slow peripherals to get extra time
in order to communicate with 8085. The 8085 will work only when READY is tied to
logic high. Whenever READY is tied to logic low, the8085 will enter wait state. When
the system has slow peripheral devices, addition hardware is provided in the system to
make the READY input low during the required extra time while executing a machine
cycle, so the processor will remain in the wait state during this extra time.

14. What is DAD and what are the flags, affected by the instruction? (Apr 2005 ECE)

DAD refers to double addition. This instruction is used to perform addition of 16 bit
data. Syntax: DAD rp
The content of register pair is added to the contents of HL pair. After addition the result
will be in HL pair. On execution of this instruction only carry flag is affected.

Give the significance of SIM and RIM instruction in 8085 microprocessor.

(NOV2006 CSE, APRIL 2004 ECE)
SIM is used to mask the hardware interrupts RST 7.5, 6.5, 5.5.It also used to
send data through SOD line. RIM is used to check whether an interrupt is masked or
not. It is also used to read data from SID line.
15. Give the format of flag register in 8085. (MAY 2006 IT,NOV2006 CSE)

D7 D6 D5 D4 D3 D2 D1 D0
Sign Zero Auxiliary Parity Carry
Flag Flag Carry Flag Flag
flag

16. List the interrupts available in 8085 microprocessor. (NOV 2006 ECE)
INT, INTR, TRAP, RST5.5, RST6.5, RST7.5

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17. What are the instructions used for data transfer? (NOV 2006 ECE)
1. LDA, LHLD, LXIH,
2. MOV SOURCE, DESTINATION
3. MVI REGISTER, 8 BIT DATA

18. Name the different machine cycles in 8085. (NOV/DEC 2006, IT)

Opcode fetch
Memory read
Memory write
I/O read
I/O write
Wait

19. List the interrupts available in 8085 microprocessor. (NOV 2006 ECE)
INT, INTR, TRAP, RST5.5, RST6.5, RST7.5

20. What are the instructions used for data transfer? (NOV 2006 ECE)
1. LDA, LHLD, LXIH,
2. MOV SOURCE, DESTINATION
3. MVI REGISTER, 8 BIT DATA

21. hat are the types of instruction for 8085 microprocessor? (Nov 2005 CSE)

The 8085 can be classified into following five categories

Data transfer, Arithmetic, logical, branching and machine control instruction

22. What are the addressing modes for 8085 microprocessor? (Nov 2005 CSE)

The 8085 has the following five different modes of addressing.

1. Immediate addressing
2. Direct addressing
3. Register addressing
4. Register indirect addressing
5. Implied addressing

24. Give the clock out frequency and state T of 8085 when the crystal frequencies are (a) 5
MHz (b) 6.144 MHz. (Apr 2005 CSE)

The clock frequencies are 5/2 =2.5 MHz and 6.144/2 = 3.07 MHz If 6 MHZ crystal is
connected with 8085 how much is the time taken by 8085 to complete opcode fetch

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 cycle and memory read cycle.external clock frequency = 6MHZ internal clock
frequency = external clock/2 = 6/2= 3 MHZ time period of one T states=1/3 MHZ=
0.333µs time taken to complete opcode fetch and memory read cycle=
7T*0.333µs=2.31µs
25. Specify how a program counter is useful in program execution. (Nov 2004 CSE)

The program counter keeps track of program execution. To execute a program the
starting address of the program is loaded in program counter. The PC sends out address
to fetch a byte of instruction from memory and increment its content automatically

26. How the data and address lines are demultiplexed? (Nov 2004 CSE)

The lower order address and data lines of 8085 are demultiplexed using an external 8-
bit D- latch (74LS373) and the ALE signal of 8085,as shown in figure
At the beginning of every machine cycle, ALE is asserted high and then low. Also the
low byte of address is given out through AD0 – AD7 lines. Since the ALE is connected
to enable of latch, whenever ALE is asserted high and then low the address are
latched into the output lines of the latch the lines AD0 – AD7 are free for data transfer.

D0 –D7

8085(CPU) 8-bit D- latch A0 – A7

AD0 – AD7 (74LS373)
EN
ALE

27. What is meant by PLAs and PALs? (Apr 2004 CSE)

Now days modern computers system uses programmable logic devices such as PALs ,
PROM or PALs to implement the “glue” logic between LSI devices.
In programmable logic array both the AND matrix and the OR matrix are
programmable by leaving in fuses or blowing them out. The two programmable matrix
make PLA very flexible, but difficult to program. In programmable array logic the
connection in the OR matrix are fixed and the AND matrix connection are
programmable .PAL are often used to implement combinational logic and address
decoder in multi computer system.

28. Why do ROM and RAM have tri-state bus outputs? (Apr 2004 CSE)

In a computer system, the data signals of many memory devices (the data bus) may be
connected together – and also to the CPU. Tristate logic allows these devices to be

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 connected together without causing contention or clash on the data bus. The figure
below shows a non-inverting tristate buffer, with an active low enable.
Tristate buffer devices (the simplest example) have an input, an output and a second
input, called the enable signal, which may be active high or low depending on the
device in question. When the enable signal is active (low in the example above) the
output follows the state of the input signal (after a short delay tpd, called the
propagation delay of the device). When the enable is inactive (high in our case) the
output of the buffer is effectively disconnected from the input. This is often referred to
as being in the high impedance state, the high-Z state or in tristate. A typical tristate
buffer is a 74HC244, and a typical bi-directional tristate buffer or transceiver is a
74HC245. Bi-directional buffers are often used in data buses to increase the drive
characteristics of the memory devices. Note that al most all CPUs, RAMs and ROMs
have tristate buffers on their data bus pins. When the output enable or the chip enable of
the RAM, for example, is inactive, the data bus of the RAM is in the high-
impedance state and is effectively disconnected from the bus. Therefore another
memory device or buffer will be free to drive the bus undisturbed.

29. What are the two compare instructions in 8085? (Nov 2004 ECE)

CMP reg, CMP M

30. Write an ALP for time delay using a register pair available in 8085. (Nov 2004 ECE)

LXI h 4500
Loop: DCX h
MOV A,C
ORA B
JNZ Loop

31. What are the difference between 8085 and 8086? (Nov 2004 ECE)

8085 8086
1.It has 16 bit address for memory and 1.It has 20 bit address for memory
8 bit address for input output mapped. So physical address space is 1 MB.

2.The flag registers are five flags. 2.All internal registers are 16 bit
wide

32. What is the function performed by SIM instruction? (Apr 2004 ECE)

This is a multipurpose instruction and used to implement the 8085 interupts (RST
7.5,6.5 and 5.5) and serial data outputs. The instruction interprets the accumulator
content.

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33. What is meant by processor cycle? (Apr 2004 ECE)
The processor cycle or machine cycle is the basic operation performed by the
processor. To execute an instruction, the processor will run one or more machine cycles
in a particular order.

34. Identify the opcodes, operands and find the number of bytes of the following instruction.
MVI H, 47 H, ADI F 5 H, SUB C. (Nov 2003 CSE)

MVIH,47  26, 47 2 bytes

ADI F5H  C6,F5 2 bytes
SUB C  91 1 bytes

35. Explain the execution of the instruction CMA M in 8085. (Nov 2003 ECE)

The content of memory address by HL pair is compared with ACC. The comparison is
performed by subtracting the content of memory from A register. The subtraction is
performed in ALU and the result is used to modify flags and then discarded. After
execution of the instruction the content of the Acc and the memory are not altered. All
flags are affected by this instruction.

36. Distinguish I/O mapped I/O and memory mapped I/O. (Nov 2003 ECE, MAY/JUNE
2007 –IT)

Memory Mapped 1/0 Standard 1/0 mapped 1/0

1. 16-bit address is alloted to
an I/O device
2. The devices are accessed by
I/O read or I/O write cycle.
3. All instructions related to
memory can be used for
data transfer.
4 . A large number of I/O ports
can be interfaced.
1. 8 -bit address is alloted to an I/O
device.
2. The devices are accessed by
memory read or memory write
cycle.
3. Only IN and OUT instructions
can be used for data transfer.
4. Only 256 ports can be interfaced.

37. State the function of ALE and TRAP pins in 8085. (Nov 2004 IT/ MAY2006 IT,)
ALE: The ALE (Address Latch Enable) is signal used to demultiplex the
address and data lines using the external latch. It is used as enable signal for external
latch. TRAP: The interrupt TRAP is non maskable and it cannot be disabled by DI
instruction. Also the Trap is not disabled by the system reset or after recognition of
another interrupt. The only signal, which can override TRAP, is HOLD.

38. If the frequency of the crystal connected to 8085 is 6 MHz, Calculate the time to

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 Fetch and execute NOP instruction. (Nov 2004 IT)
This instruction performs no operation, just provide delay Time taken to fetch
and execute nop is 4T*0.33µs= 1.32µs

39. State the function of HOLD pin in INTEL 8085 processor. (Apr 2004 IT)

The HOLD and HLDA signals are used for the DMA type of data transfer. This
type of data transfer is achieved by employing a DMA controller in the system. When
DMA is required the DMA controller will place a high signal on the HOLD pin of
8085. When HOLD input is asserted high, the processor will enter a wait state and
drive all its tristate pins to high impedance state and send an acknowledge signal to
DMA controller through HLDA pin. Upon receiving the acknowledge signal, the
DMA controller will take control of the bus and perform DMA transfer and AT the end
it asserts HOLD signal low.

40. State the function of ALE and TRAP pins in 8085. (Nov 2004 IT)

ALE: The ALE (Address Latch Enable) is signal used to demultiplex the address and
data lines using the external latch. It is used as enable signal for external latch.
TRAP: The interrupt TRAP is non maskable and it cannot be disabled by DI
instruction. Also the Trap is not disabled by the system reset or after recognition of
another interrupt. The only signal, which can override TRAP, is HOLD.

41. If the frequency of the crystal connected to 8085 is 6 MHz, Calculate the time to fetch
and execute NOP instruction. (Nov 2004 IT)

This instruction performs no operation ,just provide delay

42. State the function of HOLD pin in INTEL 8085 processor. (Apr 2004 IT)

The HOLD and HLDA signals are used for the DMA type of data transfer. This type of
data transfer is achieved by employing a DMA controller in the system. When DMA is
required the DMA controller will place a high signal on the HOLD pin of 8085. When
HOLD input is asserted high, the processor will enter a wait state and drive all its
tristate pins to high impedance state and send an acknowledge signal to DMA controller
through HLDA pin. Upon receiving the acknowledge signal, the DMA controller will
take control of the bus and perform DMA transfer and AT the end it asserts HOLD
signal low.

43. Define flag and list out the flags in 8085.

Flag is a flip-flop used to store the information about the status of the processor and the
status of the instruction executed most recently.

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 There are five flags in 8085. They are sign flag, zero flag, Auxiliary carry flag, parity
flag and carry flag.

44. Which interrupt has the highest priority in 8085?what is the priority of other interrupts?

The TRAP has the highest priority, followed by RST7.5,RST 6.5, RST5.5 and INTR.

45. How clock signals are generated in 8085 and what is the frequency of the internal
clock?

The 8085 have the clock generation circuit on the chip but external quartz crystal or LC
circuit or RC circuit should be connected to x1 and x2 in order to generate a clock
signal. The 8085 clock generation circuit, generate a clock whose frequency is double
that of internal clock. The generated clock is divided by two and then used as internal
clock. The maximum internal clock frequency of 8085A is 3.03 MHz.

46. What is the physical memory size of 8085 and how many address lines are required?

The size of the binary number used to address the memory decides the physical
memory space. If the microprocessor has n- address lines then can directly address 2n
memory location. The 8085 uses 16-bit address lines, so 216 = 64K memory location

47. Write an 8085 program to generate a time delay of 0.4sec

given crystal frequency 5MHZ.

Operating frequency = 5/2 = 2.5MHZ.

Time for one T-state = 1/ 2.5MHZ = 0.4µ sec.
Number of T-states required = Required Time/Time for 1T-state
= 0.4sec/ 0.4µ sec
= 1 x 106
Delay program:
LXI B,COUNT
Loop : DCX B
MOV A,C
ORA B
JNZ Loop
6
1 x 10 = 10 + (count – 1) x24 +21
count = 4166610
= A2C2H.

48. Write 8085 assembly language instructions to store the contents of the flag register in
memory location 2000H.

PUSH PSW
POP B

9
 MOV A,C
STA 2000H.
HLT

49. What is an Interrupt? Haw the interrupt are classified ?

Interrupt is a signal send by an external device to the processor so as to request the
processor to perform a particular task or work.
They are three methods of classifying interrupts
Method I :The interrupts are classified into Hardware and
Software interrupts

Method II:The interrupts are classified into vectored and Non-

Vectored interrupt

50. What is the need for timing diagram? What is T -state?

The timing diagram provides information regarding the status of various signals, when
a machine cycle is executed. The knowledge of timing diagram is essential for system
designer to select matched peripheral devices like memories, latches, ports, etc., to
form a microprocessor system.
The T-state is the time period of the internal clock signal of the processor. The time
taken by the processor to execute the machine cycle is expressed in T-state.

UNIT 2

PART-A
1. .What is the function of trap flag and direction flag in 8086? (MAY/JUNE 2007 –IT)

After execution of every instruction the status of the register, as well memory is
Verified if DF=0 automatic increment of SI and DI and DI=1 means decrement of
of SI and DI register takes place.

2. Write the operations carried out when the instructions IN AL, OOH and IN AL, DX
are executed by 8086. (MAY/JUNE 2007 –IT)

IN AL, OOH instruction will move 00 data given in the instruction to 8-bit AL
Register.
IN AL, DX - in this instruction 8-bit data addressed by DX will move into AL.

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3. Draw the contents of the stack and the registers after a PUSH instruction. (NOV/DEC-
2007, CSE, regulation 2004)

PUSH rp

Steps involved in push operation.

a) Initial position of sp.

b) Decrements sp and stores higher byte.
c) Decrement sp and stores lower byte

Push Dsp=2000h DE=1050H

4. What is the function of TLB? (NOV/DEC 2006, IT)

TLBs(translation look aside buffers) that automatically translate the upper 20
bits of the virtual address into the upper 20 physical memory address bits.TLB can
translate rtual address and access the cache with in a single clock cycle.

5. What do these 8086 instructions do? : STD, IRET.

(NOV/DEC-2007, CSE, R 2004)

SID instruction:

This instruction is used to set the direction flag to one s0 that SI and/or DI can be
decremented automatically after execution of string instructions STD does not affect any
other flag.

IRET instruction:

The IRET instruction is used at the end of the interrupt service routine to return
execution to the interrupted program. the 8086 copies return address from stack into IP and
CS registers and the stored value of flags back to the flag register.

6. What is macro? (NOV/DEC-2007, CSE- R 2004)

7. What are the two modes of operation supported by 8086 architecture? How do you
Choose the mode of operation? (NOV/DEC-2007, CSE-R 2005)

Two modes of operation are maximum mode and minimum mode.

The mode is selected by MN/MX pin present in the 8086 chip.

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 When MN/MX=1(minimum mode)
When MN/MX=0(minimum mode)

8. Give the function of the following pins in 8086 a) ready b) ALE. (NOV/DEC-2007,
MCA- R2005)

READY:
If this signal is low the 8086 enters into WAIT state. The READY signal from
memory/IO is synchronized by the 8284A clock generator to form READY .This signal
is active HIGH.

ALE:
The 8086 has multiplexed address/data signals and address/status signals. Latches are
used for demultiplexing and these latches are enabled by using the ALE signal. Three
numbers of latches (Intel 8282/8283) are used as address latches.

9. How the interrupts can be masked / unmasked in 8086? (May/ June 2007 CSE)

By using NMI pin the interrupt can be masked and unmasked in 8086.

10. What are the signals involved in memory bank selection in 8086?

(May/ June 2007 CSE)

BHE (Bus High Enable) and Ao (Address line) .

11. Write briefly on LOCK and WAIT of 8086 . (May/ June 2007 – R 2001,CSE)
The LOCK prefix allows 8086 to make sure that another processor does not take
control of the system bus while it is in the middle of a critical instruction which uses
the system bus.

The WAIT instruction causes the 8086 to enter the wait state while its test line is not
active.

12. State the function of the MIN/MAX pin of 8086 . (May/ June 2007 – R 2001,CSE)
MN/MAX mode is use to change the mode of operation. MN/MAX is connected to 5v
if 8086 work in minimum mode and MN/MAX is connected to ground in maximum
mode

13. Explain the function of execution unit of 8086 . (May/ June 2007 – R 2001,CSE)

It will get the data from BIU and process the data in execution unit and result is
again given to bus interface unit .

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14. What are the differences between fetching 2 byte data starting at even address and
Odd address in 8086 system. (MAY2007 ECE)
BANK 0 is connected to the lower half of the 16 bit data (D0-D7) and contain even
address bytes i.e,when A0 is low the even bank is selected .Bank 1 is connected to
the uppr half of the data bus(D8-D15) and contains odd address bytes i.e, when A0
bit is high and BHE is low odd bank is selected.

15. When is a machine cycle initiated? How many States does each machine cycle contain in
8086? (NOV/DEC-2007, CSE-regulation 2005)

Fetch, decoding and execution of a single instruction constitute an instruction cycle. each
memory (or) operation requires a particular time period, called machine cycle.
In other words, to move byte of data in or out of the microprocessor, a machine cycle is
required. Each machine cycle consists of 3 to 6 clock periods/cycles referred to as T-
states.

16. .Write a control word to set 8255 Port A as Input and Port B as output and Port C
as Input port in model configuration. (MAY 2007 ECE)

17. list the different modes of 8255 for I/O operation. (MAY IT 2006)
1. mode 0
2. mode 1
3. mode2
18. .State the function of DSR and DTR pins in 8251. (MAY IT
2006)
DSR---Data set ready.it is used to test the modem condition.
DTE---- data terminal ready. It is used to check whether receiver is ready or not.

list the features of 8259. (MAY IT 2006)

a. It manages 8 interrupts.
b. Interrupts can be masked or unmasked individually.
c. It provides the status of pending interrupts.
d. it can be cascaded.
19. How many address lines and data lines in 8086? (NOV 2006 ECE)

There are 16 data lines and 20 address lines present in 8086

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 20. Why ADC and DAC is used in the microprocessor based system?
(NOV 2006
ECE)
21. What do you mean by pipelining in 8086 processor (Apr’2005, NOV 2006
CSE)
When fetching and execution takes place simultaneously then it is known as
pipelining. in 8086 it is achieved by instruction queue.
22. What are the advantages of segment and offset method of addressing memory?
(NOV/DEC 2006, IT)
Segmented memory is utilized by protected mode to allow tasks to have their own
Separate memory space.

What are the different types of interrupts in 8086 (MAY IT 2006)

*predefined interrupts
*user defined software interrupts
*user defined hardware interrupts.
23. State the interrupt priorities of 8086. (MAY IT 2006)

divide error ,intN,int o -------- highest priority.

Nmi
Intr ↓
Single step ------------- lowest priority.

24. Why is an interrupt driven I/O more efficient than programmed I/O for 8086
microprocessor? (Nov 2005 CSE)

In 8086 the interrupts initiated by executing “INT n” instruction is called as software

interrupts. The interrupts initiated by applying appropriate signals to INTR and NMI
pins of 8086 are called as hardware interrupts. So I/O interrupts are more efficient
because it is a non-maskable interrupts.

Name the software operation possible with the 8086 compared with 8085
microprocessor? (Nov 2005 CSE)

In 8086 it is possible to do modular programming such as Linking and relocation,

procedures, Macros, Byte and string manipulation etc. Whereas it is not possible to do
modular programming in 8085

26. Define the following instruction cycle, Machine cycle & T state. (Apr 2005 CSE)

Instruction cycle: The sequence of operation that a processor has to carryout while
executing an instruction is called instruction cycle.

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 Machine cycle: Each instruction cycle of a processor in turn consists of a number of
machine cycles.
T-State: the T-State is the time period of the internal clock signal of the processor time
taken by the processor to execute a machine cycle is expressed in T-State.

27. Mention the function of SI register and DI registers. (Apr 2005 CSE)

Source index is used to hold the index value of source operand for string instruction
Destination index is used to hold the index value of destination operand for string
instruction
28. What is the function of TEST pin in 8086 processor? (Apr 2005 ECE)

When the processor reads from memory or an I/O location it asserts RD low. The TEST
input is tested by WAIT instruction. The 8086 will enter a wait state after execution of
the WAIT instruction and it will resume execution when TEST is made low by an
external hardware.

29. How does the 8086 processor access a word at on odd address? (Apr 2005 ECE)

In 8086 based system the lower lines of data bus are connected to even bank memory
Ics and the upper eight data lines are connected to Odd bank memory Ics. The address
line A0 selects the even bank and odd bank is selected by the control signal BHE.

30. What is the function of T and D flags in 8086? (Apr 2005 IT)

TF(Trap flag)-if set, a trap is executed after reach instruction

IF(Interrupt enable flag)-If set ,a certain type of interrupt (a maskable interrupt)can be
recognized by the CPU; otherwise these interrupts are ignored

31. What is the operation is carried out when 8086 executes the instruction MOVSW? (Apr
2005 IT)

It move the content from B register to the accumulator without altering the value.

32. State the functional units available in 8086. (Nov 2004 CSE)

The Bus Interface Unit(BIU) and Execution Unit(EU) are the two functional units
available in 8086 instruction

32. Give the difference between segment registers and general purpose registers. (Nov 2004
CSE)

The segment registers are used to store 16 bit segment base address of the four memory
segments. The general purpose registers are used as the source or destination register
during data transfer and computation, as pointers to memory and as counters.

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33. What is the difference between the following 8086 instruction: MOV AX,
TABLE_ADDR and LEA AX, TABLE_ADDR? (Apr 2004 CSE)

The Mov instruction move the contents and duplicate the contents from the source to
destination
The LEA instruction loads the effective address computed by adding the contents of
BX or BP register contents, SI or DI register contents and a displacement.

34. What is the function of the following signal pins in 8086 based systems- BHE, TEST,
RESET. (Apr 2004 CSE)

BHE  Bus high enable used to enable the bus.

TEST  Used to wait on list control.
RESET  System reset

35. What is a segment override prefix? Give an example. (Nov 2004

ECE)

An assembly program in .EXE format consists of one or more segments. The start of
these segments are defined by SEGMENT and the end of the segment is indicated by
ENDS directive. Format Name SEGMENT

Name ENDS

36. Write a program segment that will carry out the following binary operation using 8086
instruction W<=X+Y+24-Z. (Nov 2004 ECE)

MOV AX, X
ADD AX, Y
ADD AX, 24
SUB AX, Z
MOV W, AX

37. What are segment register in 8086 ? (Nov 2003 ECE)

The segment register are used to store 16 bit segment base address of four memory
segments.

38. Explain the Min/Max mode of 8086 microprocessor. (Nov 2003 IT)

The minimum mode is used for a small system with a signal processor, a system which
the 8086/8088 generates all the necessary bus ctrl signals directly.
The maximum mode is for medium size to large systems which often include two or
more processor.

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39. List the flags of 8086.

The 8086 has nine flags and they are

1. Carry Flag (CF) 6. Overflow Flag (OF)
2. Parity Flag (PF) 7. Trace Flag (TF)
3. Auxiliary carry Flag (AF) 8. Interrupt Flag (IF)
4. Zero Flag (ZF) 9. Direction Flag (DF)
5. Sign Flag (SF)

40. List the different addressing modes of 8086.

Register Addressing Mode, Immediate Addressing Mode, Direct Memory Addressing

Mode, Indirect Addressing Mode.

41. How to exit from the HALT state.

There are three ways to exit a halt by an interrupt, by ahard ware reset, or during the
DMA operation.

42. Write the special functions carried by the general purpose registers of 8086.

The special functions carried by the registers of 8086 are the following.
Register Speical function
AX 16-bit Accumulator
AL 8-bit Accumulator
BX Base Register
CX Count Register
DX .Data Register

43. In 8086 processor the code segment contains 4000H and instruction pointer contains
9F20H. Find the memory location addressed by the processor.

Segment address 4000 0100 0000 0000 0000

Shifted to left by 0100 0000 0000 0000 0000

four bits +
Offset address 1001 1111 0010 0000

0100 1001 1111 0010 0000

Physical address 49F20H

44. How clock signal is generated in 8086? What is the maximum internal clock frequency of
8086?

17
 The 8086 does not have on-chip clock generation circuit. Hence the clock generator
chip, 8284 is connected to the CLK pin of8086. The clock signal supplied by 8284 is
divided by three for internal use. The maximum internal clock frequency of8086 is
5MHz.

UNIT-3

PART A

1. How clock signal is generated in 8086? What is the maximum internal clock

frequency of 8086? (May/ June 2007 CSE)

clock signal is generated by using external crystal clock generator .range of clock rates :

5MHZ for 8086,8 MHZ for 8086-2, 10MHZ for 8086-1.

2. What are the 3 modes of operations of a keyboard interface chip 8279? (May/ June
2007 – R 2001,CSE)
1. scanned keyboard mode
2.scanned sensor matrix mode
3.strobed input mode.
3. What is the need for virtual mode bit of 80386? (May/ June 2007 – R 2001,CSE)
In virtual mode 80386 can execute 8086 instructions. From virtual mode processor can
switch to protected mode in which it can execute 80386 instructions.

4. What is the use MN/MX signal in 8086? (MAY2007 ECE)

MN/MX pin is used to change the mode of operation in 8086. if this pin is
connected to +5 volt then 8086 is working in minimum volt and vice versa.

5. What is a coprocessor? (NOV/DEC-2007, CSE, R 2004)

18
 In coprocessor configuration both the CPU (8086) and external processor(math co-
processor 8087)share entire memory and i/o sub system. they also share same bus control
logic and clock generator,
Coprocessors add instructions to the instruction set. an instruction to be executed by the
coprocessor is indicated by an escape(ESC) prefix or instruction.

6. . Mention any two coprocessors and their use. (NOV/DEC-2007, MCA-R 2005)

Coprocessor

In coprocessor configuration both the CPU (8086) and external processor(math co-
processor 8087)share entire memory and i/o sub system. they also share same bus control
logic and clock generator,

Ex: 8087(MATH coprocessor)

Many microcomputer program, such as those used for specific

research,engineering,businees,and graphics, need to make mathematical calculations such
as computing the square root of a number, log of a number. Another common need is to do
arithmetic operations an very large and very small numbers.

7. What is meant by time multiplexed LED display? (NOV/DEC 2006, IT)

8. An interrupt device based on 8086 microprocessor sends 03h onto AD0 thru AD7 data
bus when INTA is low. Where should the interrupt jump address located in the vector
table? (Nov 2005 CSE)

An 8086 interrupt can come from any of the following three sources
• External signals
• Special instructions in the program
• Condition produced by instruction
Then it will jump into the any one-vector address table of 256.

9. Name the signals used by 8086 to demultiplex the address/data bus and to control the
data bus buffer? (Nov 2005 CSE)

The signal MI/O is used to differentiate memory address and I/O address. When the
processor is accessing memory location I/O is asserted high and when it is accessing
I/O mapped devices it is asserted low.

10. Define pipeline operation in 8086. (Apr 2005 CSE)

19
 Conventionally instruction fetch and execution operation are performed sequentially;
one after another in separate time slots .to speed up the program simultaneously. While
decoding and execution of an instruction is progressing. A new instruction can be
fetched, provided the execution of the current instruction does not require memory
access. The concept of performing more than one operation in as overlapping manner is
known as pipelining.

11. Name the four-processor control instruction (8086). (Apr 2005 CSE)

Some of the process control instructions are

CLC, CMC, STC, CLD, STD etc.

12. State the modes in which 8086 operate. (Nov 2004 CSE)

The 8086 can operate in two modes and these are minimum mode and the maximum
mode.

13. What is macro? Give example. (Nov 2004 CSE)

Conventionally instruction fetch and execution operation are performed sequentially;

one after another in separate time slots .to speed up the program simultaneously. While
decoding and execution of an instruction is progressing. A new instruction can be
fetched, provided the execution of the current instruction does not require memory
access. The concept of performing more than one operation in as overlapping manner is
known as pipelining.

14. In how many ways can the EA calculate by the addressing modes in 8086? List them.
(Apr 2004 CSE)

The effective address is thecombination of theBX or BP register content, SI or DI

register content and a displacement. The effective address may also be placed directly
in the instruction (e.g) (DS)*10+2536+(BX)+(SI)

15. What are the schemes for establishing priority in order to resolve bus arbitration
problems? (Apr 2004 CSE)

Daisy Chaining
Polling
Independent requesting
16. What is the role of TF and IF flags in the flag register of 8086? (Nov 2004 IT)

TF(Trap flag)-if set, a trap is executed after reach instruction

IF(Interrupt enable flag)-If set ,a certain type of interrupt (a maskable interrupt)can be
recognized by the CPU; otherwise these interrupts are ignored.

20
17. What are the advantages of a loosely coupled configuration (Apr 2004 CSE)

High system throughput can be achieved by having more than one CPU The system can
be expanded in a modular form. Each bus master is an independent unit and normally
resides on a separate pc board. Therefore a bus master module can be added or removed
without affecting the other modules in the system’s failure in one module normally
does not cause a breakdown of the entire system and faulty module can be easily
detected and replaced

18. What are the three basic multiprocessor configuration that the8086 can support? (Nov
2003 CSE)

Coprocessor configuration
Closely coupled configuration
Loosely coupled configuration

19. State the need for stack (Nov 2003 CSE)

Stack is apart of RAM used for storing intermediate results, address of memory or
register contents temporarily. The user must define the area of RAM to be used as
stack. Stack pointer keeps the starting address of the stack. It follows LIFO mechanism.

20. What are the three groups of signals in 8086?

Common signal
Maximum mode signal
Minimum mode signal

21. What are signals involved in memory bank selection in 8086?

In 8086 based system the even bank is selected by address line Ao and the odd bank is
selected by control signal BHE.

22. What do you mean by timing diagram?

The timing diagram provides information the status of various signal, when a machine
is executed. The knowledge of timing is essential for system designer to select matched
peripherals devices like memories, latches, ports etc. to form a microprocessors system.

23. What is queue? How queue is implemented in 8086?

A data structure which can be accessed on the basics of first in first out is called queue.
The 8086 has six number of 8 bit FIFO register which are used as instruction queue.

24. How 20-bit physical address is generated from 16 bits internal registers in 8086?

21
 First the effective address is calculated which is of 16 bits, on the other hand address
put on the address bus called the physical address must contain 20 bits the extra 4 bits
are obtained by adding the EA to the contents of one of the segment registers. The
address is carried out by appending four 0 bits to the right of the number in the segment
register before the addition is made, thus 20 bit result is produced.

25. What is a recursive procedure?

A recursive procedure is a procedure which calls itself. Recursive procedures are used
to work with complex data structures called trees. If the procedure is called with N=3,
then the N is decremented by 1 after each procedure CALL and the procedure is called
until N=0.

26. Explain about passing parameters using registers with example?

Procedures process some data or address variable from the main program, for
processing it is necessary to pass the address variables or data. This is called passing
parameters to procedures. In passing parameters using registers the data to be passed is
stored in registers & these registers are accessed in the procedure to process the data.
CODE SEGMENT
MOV AL, DATA

CALL PRO1

PRO1 PROC NEAR

MOV INPUT, AL

RET
PRO1 ENDP
CODE ENDS

27. Explain the linking process.

A linker is a program used to join together several object files into one large object
file. The linker produces a link file which contains the binary codes for all the
combined modules. It also produces a link map which contains the address information
about the link files. The linker does not assign absolute addresses but only relative
address starting from zero, so the programs are relocatable & can be put anywhere in
memory to be run.

28. What are assembler and Linker?

The assembler translates the assembly language program text which is given as input to
the assembler to their binary equivalents known as object code. The time required to

22
 translate the assembly code to object code is called access time. The assembler checks
for syntax errors & displays them before giving the object code.
A linker is a program used to join together several object files into one large object file.
For large programs it is more efficient to divide the large program modules into smaller
modules. Each module is individually written, tested & debugged. When all the
modules work they are linked together to form a large functioning program.

29. Write the format BSR control word in 8255? (Nov 2004 IT, Nov 2003 IT)

B7 B6 B5 B4 B3 B2 B1 B0

If B7= 0 it is BSR MODE.

B6,B5,B4 are don’t care
B3,B2, B1 are used to select port C pin TO set or reset depending on the bit B0
B0=0 RESET
B0=1 SET

UNIT 4

PART A
1. . List the uses of USART. (NOV/DEC-2007, CSE, regulation 2004)
.i ) Intel 8251A USART (universal synchronous / asynchronous receiver transmitter)
is used for serial I/O transfer with microprocessor.

ii) it supports standard asynchronous protocol with

a) 5 to 8 bit character format

b) Add, even or no parity generation and detection
c) Automatic break detect and handling.
iii)it allows full duplex transmission.

3. Write the I/O control word format of 8255. (MAY/JUNE 2007 –IT)

23
4. How high power devices are interfaced with microprocessor ports? (MAY/JUNE
2007 –IT)

5. What is the function of EOI command in 8259 (programmable interrupt controller)

(MAY/JUNE 2007 –IT)
In the AEOI mode the ISR bit is reset at the end of third INTA pulse. Otherwise the
ISR bit remains set until an appropriate EOI command is issued at the end of interrupt
request

6. Calculate how many devices can be addressed by 8086. (NOV/DEC-2007, MCA,

regulation 2004)
7. Give the format of program clock word of 8279 and mention its purpose. (NOV/DEC-
2007, CSE-regulation 2005)

Program clock command

All timing and multiplexing signals for the 8279 are generated by an internal prescaler.this
prescaler divides the external clock by a programmable integer value given in the program
clock command word, to generate internal frequency.

B7 B6 B5 B4 B3 B2 B1 B0
0 0 1 p p p p p

Bits ppppp determine the value of this integer which ranges from 2 to 31.

8. What is the function of gate signal in 8254 timer? (May/ June 2007 CSE)

Gate: In Time mode control register (TMOD), when TRX (In TCON) is set and Gate =1

TIMER / COUNDTER x will run only while TRX=1 (Software Control)

9. Write the format of KW1 in 8259. (May/ June 2007 CSE)

10. What is pipelined architecture? (May/ June 2007 CSE)

Using pipeline architecture processor can execute more then one instruction in a single

Clock cycle. The stages in pipeline architecture are fetch, decode execute and store.

24
 11. Write a control word to set 8255 Port A as Input and Port B as output and Port C as
Input port in model configuration. (MAY 2007 ECE)

12. when DSR signal will be activated (MAY2007 ECE)

Before data transmission takes place between two devices (ex. transmission takes place
between memory and processor) DSR will be activated.

13. What are the 3 modes of operations of a keyboard interface chip 8279?
(May/ June 2007 – R 2001, CSE)
Scanned keyboard mode
Scanned sensor matrix mode
strobed input mode

14. Write the different modes of operation of 8255. (NOV/DEC 2006, IT)
BSR mode and I/O mode

I/O mode is further divided into

Mode 0-basic I/O mode
Mode-1 strobed I/O mode
Mode-2 bidirectional data transfer mode

15. What is meant by resolution of an ADC? (NOV/DEC 2006, IT)

16. Name any two important methods available for error correction during serial
communication? (Nov 2005 CSE)

The status word can be read by the CPU to check the readiness of the transmitter or
receiver and to check the character synchronization in synchronous reception .It also
provides information regarding various errors in the data received. The various error
conditions that can be checked from the status word are parity error overrun error and
framing error.

17. What is meant by “baud-rates” and how is it achieved? (Nov 2005 CSE)

The baud rate is the. rate at which the serial data are transmitted. Baud
Rate is defined as l/(The time for a bit cell). In some systems one bit cell has one data
bit, then the baud rate and bits/sec are same.

25
18. Draw the command word format for 8251. (Apr 2005 CSE)

DIAGRAM

19. What is cycle stealing in DMA? (Apr 2005 ECE)

In cycle stealing DMA the DMA controller will perform one DMA transfer in between
instruction cycles

20. List the functions performed by 8279. (Apr 2005 ECE)

The functions performed by 8279

Keyboard Scanning, Key Deboncing, Key code Generation, Informing the key entry to
CPU, Storing display codes, output display codes to LEDs and Display refreshing

21. Specify the bit of controller word for 8255.Which differentiates between I/O mode and
the BSR mode? (Nov 2004 ECE)

DIAGRAM

22. Give the bit format used for sending a synchronous serial data. (Nov 2004 CSE)

DIAGRAM

23. Write the format BSR control word in 8255? (Nov 2004 IT)

DIAGRAM

24. State the functions of the control register in INTEL 8255? (Apr 2004 IT)

The content of this register called control word specify an input/output function for
each port.

25. Mention any two functions performed by INTEL 8251. (Nov 2004 CSE)

It is used for converting parallel data to serial or vice versa. The data transmission or
reception can be either asynchronous or synchronous. It is also used to interface
MODEM and established serial communication through MODEM over telephone lines

26
26. How DMA is initiated? (Nov 2004 CSE)

When the input output device needs a DMA transfer, it will send a DMA request signal
to DMA controller. The DMA controller in turn sends a HOLD requests to the
processor. When the processor receives a HOLD request it will drive its tri-stated pins
to high impedance state at the end of current instruction execution and send an
acknowledge signal to DMA controller. Now DMA controller will perform DMA
transfer.

27. Specify the two types of serial communication. (Nov 2003 CSE)

The two types are:

i) Synchronous and ii) asynchronous communication

28. List the four possible modes of operation of 8237 DMA controllers. (Nov 2003 CSE)

The possible modes are:

i) Demand mode (00) ii) Single mode (01) iii) Block mode (10) iv) cascade
mode (11)

29. What is 8259? What are its functions? (Nov 2003 ECE)

8259 is a programmable interrupt controller. It major functions are can manage eight
interrupt according to the instruction Vector an interrupt request anywhere in the
memory map. Mask each interrupt request individually.

30. What is the difference between two key lockout and N-key rollover modes in 8279?

In keyboard interface there are two methods of handling keys. If one key is pressed and
generates its code that is called as two key lockout and on the other hand it detects all
the keys pressed in the order of entry and generates corresponding keycode.

31. What do you mean by BSR mode of 8255 PPI? (Nov 2003 IT)

The BSR mode is concerned only with the eight bits of port C, which can set or reset by
using an appropriate control word in the control register with D7 =0 is recognized as a
BSR control word and it does not alter any previously transmitted control word bit D7
=0

32. What are the operating modes of 8255 PPI?

The port-A of 8255 can be programmed to work in anyone of the

following operating modes as input or output port.
Mode-0 : Simple 1/0 port.

27
 Mode-l: Handshake 1/0 port
Mode-2 : Bidirectional 1/0 port

33. What is the need for 8254 programmable interval timers and mention its applications?

It is used basically as counter and timers

Application:
Real time clock
Event counter
Digital one shot
Square wave generator
Complex waveform generator
34. What are the different modes of operation of 8254?

The different modes are

Mode 0 – Interrupt on terminal count
Mode 1 – Hardware retriggerable one shot
Mode 2 – Rate generator
Mode 3 – Square wave generator
Mode 4 – Software triggered strobe
Mode 5 – Hardware triggered strobe
35. What are the different modes of 8279?

The different scan modes of8279 are decoded scan and encoded scan. In decoded scan
mode, the output of scan lines will be similar to a 2-to-4 decoder. In encoded scan
mode, the output of scan lines will be binary count, and so an external decoder should
be used to convert the binary count to decoded output.

36. What is USART? What are the functions performed by INTEL 8251A?

The device which can be programmed to perform Synchronous or Asynchronous serial

communication is called USART (Universal Synchronous Asynchronous Receiver
Transmitter). The INTEL 8251A is an example of USART.
The INTEL 825lA is used for converting parallel data to serial or vice versa. The data
transmission or reception can be either asynchronously or synchronously. The 8251A
can be used to interface MODEM and establish serial communication through
MODEM over telephone lines.

37. What are the control words of 8251A and what are its functions?

The control words of 8251A are Mode word and Command word. The mode word
informs 8251 about the baud rate, character length, parity and stop bits. The command
word can be send to enable the data transmission and reception.

28
38. What is deboucing ?

When a key is, pressed it bounces for a short time. If a key code is generated
immediately after sensing a key actuation, then the processor will generate the same
key code a number of times.(A key typically bounces for 10 to 20 msec). Hence the
processor has to wait for the key bounces to settle before reading the key code. This
process is called keyboard debouncing.

39. What is the difference in programming the 8279 for encoded scan and decoded scan?

If the 8279 is programmed for decoded scan then the output of scan lines will be
decoded output and if it is programmed for, encoded scan then the output of scan lines
will be binary count. In encoded mode, an external decoder should be used to decode
the scan lines.
40.What are the different types of ADC?
The different types of ADC are successive approximation ADC, counter type ADC
flash type ADC, integrator converters and voltage-to-frequency converters.

UNIT-5

PART-A

1. Which port of 8051 requires external pull up resistances when configured as output?
Port? Why? (MAY/JUNE 2007 –IT)

2. Write the expression of baud rate in model operation of 8051 serial port.
(MAY/JUNE 2007 –IT)
The rate at which bits are transmitted is called baud rate. Measured in bits/second.
baud rate is in the range of 50,75,100,150,300,600,1200,2400,4800,9600,19200.
3. List the interrupts of 8051 microcontroller. (May/ June 2007 CSE)

Five interrupts are provided in the 8051.Three of these are generated by internal
operations. Timer flag 1 and the serial port interrupt (R0 and T1) .Two interrupts are
triggered by external signals provided by circuitry that is connected to pins INTO and
INT1

29
4. What are register banks in 8051 microcontroller? (May/ June 2007 CSE)

BANK0.BANK1, BANK2, BQNK3

5. What is the need for virtual mode bit of 80386? (May/ June 2007 – R 2001,CSE)
In virtual mode processor can execute 8086 instructions. From virtual mode processor
can switch to protected mode to execute 80386 programs.

6. Write briefly on pipeline architecture of Pentium processor (May/ June 2007 – R

2001, CSE)
The main purpose of pipeline is at same time processor can able to process
move than one instruction. The process of pipeline architecture is Fetch, Decode,
Execute and Store. When one Instruction is decoded then next Instruction is fetched in
the fetching Unit.

7. Draw the format of PSW of 8051. (NOV/DEC-2007, CSE, regulation 2004)

8. List the addressing modes supported by 8051. (NOV/DEC-2007, CSE, regulation 2004)
Register addressing mode
Direct byte addressing
Register indirect addressing
Immediate addressing
Register specific
Index.

9. What is the maximum capacity of memory that can be interfaced with 8051?
(NOV/DEC 2006, IT)
Maximum capacity of memory that can be interfaced with 8051 is 64 KB.
10. What is the function of GATE bit in the TMOD register of 8051?
(NOV/DEC 2006, IT)
8051 has two 16 bit timers/counters. T0 and T1 capable of working in different
modes. each consists of a ‘HIGH’ byte and a ‘LOW’ byte which can access under
software .There is a mode control register (TMOD) and a control register (TCON)
to configure these timers/counters in number of ways.

11. ich control signal of 8051 are used to access external data memory and external
program memory?

12. Which control signal of 8051 are used to access external data memory and external
Program memory? (NOV/DEC 2006, IT)

30
 The PSEN (program store enable) is a active low output signal that acts as a strobe to
read the external program memory. This goes low during external program memory
accesses.

13. What are alternate functions of port 3 in 8051 microcontroller? (Nov 2006 ECE)

The alternate functions of port 3 are

RD – Read data control output.
WR – Write data control output.
T1 – Timer / Counter1 external input or test pin.
T0 – Timer / Counter0 external input or test pin.
INT1- Interrupt 1 input pin.
INT 0 – Interrupt 0 input pin.
TXD – Transmit data pin for serial port in UART mode.
RXD - Receive data pin for serial port in UART mode.

14. Compare the 8051, 8031 and 8751 microcontroller? (Nov 2005 ECE)

In 8031 there is no ROM

In 8051there is internal 128bytes EPROM
In 8751 there is internal 128bytes Flash ROM

15. What is function of DPTR register? (Apr 2005 ECE)

DPTR stands for data pointer. DPTR consists of a high byte (DPH) and a low byte
(DPL). Its function is to hold a 16-bit address. It may be manipulated as a 16-bit data
register or as two independent 8-bit registers. It serves as a base register in indirect
jumps, lookup table instructions and external data transfer.

16. Name the interrupt of 8051 micro controllers. (Apr 2005 ECE)

The interrupts are:

Vector address
• External interrupt 0 : IE0 : 0003H
• Timer interrupt 0 : TF0 : 000BH
• External interrupt 1 : IE1 : 0013H
• Timer Interrupt 1 : TF1 : 001BH
• Serial Interrupt
Receive interrupt : RI : 0023H
Transmit interrupt : TI : 0023H

17. What is the special function registers available in 8051 micro controller? (Nov 2004
ECE)

a. Accumulator

31
 b. B Register
c. Program Status Word.
d. Stack Pointer.
e. Data Pointer.
f. Port 0
g. Port 1
h. Port 2
i. Port 3
j. Interrupt priority control register.
k. Interrupt enable control register.

18. What is job of TMOD register? (Nov 2004 ECE , MAY 2007 ECE)

The TMOD register is used to select the operating mode and timer/counter operation of
the timers

19. What is the interrupt priority control register in 8051 micro controller? (Apr 2004 ECE)

• External interrupt 0
• Timer interrupt 0
• External interrupt 1
• Timer Interrupt 1
• Serial Interrupt

20. List the merits of Memory Segmentation. (Apr 2004 ECE)

It is easier to access the memory 256 bytes has been separated into two parts one is
RAM and other one is SFR .Due to memory segmentation we can program the SFR by
mentioning its address and moreover we can do bit wise as well as byte programming

21. Distinguish between Microprocessor and Micro controller. (Nov 2003 ECE)

Sl. Microprocessor Microcontroller

No
1 Microprocessor contains
ALU,general purpose registers,
stack pointer, program counter,
clock timing circuit and interrupt
circuit.
2 It has many instructions to move
data between memory and CPU.
3 It has one or two bit handling
instructions.
4 Access times for memory and I/O
devices are more.
Microcontroller contains the circuitry of
microprocessor and in addition it has
built- in ROM, RAM, I/O devices, timers
and counters.
It has one or two instructions to move
data between memory and CPU.
It has many bit handling instructions.
Less access times for built-in memory
and I/O devices.

32
 5 Microprocessor based system Microcontroller based system requires
requires more hardware. less hardware reducing PCB size and
increasing the reliability.

22. List any two application of micro controller. (Nov2003 ECE)

Standalone devices
Automotive applications

23. State the function of RS1 and RS0 bits in the flag register of Intel 8031/8051. (Apr 2004
IT)

RS1 , RS0 – Register bank select bits

RS1 RS0 Bank Selection

0 0 Bank 0
0 1 Bank 1
1 0 Bank 2
1 1 Bank 3

24. Write a short note on bit wise instruction of 8051 micro controllers. (Nov 2003 IT)

Some of the SFR are both bit wise as well as byte wise programming some of them are
B register, ACC, IP, P0-P3, SCON, TCON, IE, PSW

25. Explain the function of the pins PSEN and EA of 8051.

PSEN stands for program store enable. In 8051 based system in which an external
ROM holds the program code, this pin is connected to the OE pin of the ROM.
EA stands for external access. When the EA pin is connected to Vcc, program fetched
to addresses 0000H through 0FFFH are directed to the internal ROM and program
fetches to addresses 1000H through FFFFH are directed to external ROM/EPROM.
When the EA pin is grounded, all addresses fetched by program are directed to the
external ROM/EPROM.

33
26. Write down the different operating modes for serial communication of 8051.

Serial communication of 8051 operate under four modes. They are

mode 0 , mode 1, mode 2 and mode3 .SM0 and SM1 bits of SCON register
specifies the mode.
SM0 SM1 Mode
0 0 0 Baud rate fixed.
0 1 1 8-bit data, 1 stop bit, 1 start bit. Baud rate
Variable.
1 0 2 8-bit data, 9th programmable bit,1 stop bit, 1
1 1 3 8-bit data, 9th programmable bit,1 stop bit, 1
Start bit, Baud rate fixed.

27. Explain the register IE format of 8051.

EA - ET2 ES ET1 EX1 ET0 EX0

EA- Enable all control bit.

ET2- Timer 2 interrupt enable bit.
ES – Enable serial port control bit.
ET1 – Enable Timer1 control bit.
EX1- Enable external interrupt1 control bit.
ET0 – Enable Timer0 control bit.
EX0- Enable external interrupt0 control bit.

28. What is the use of timing and control unit?

Timing and control unit is used to deliver all the necessary timing and control signals
required for the internal operation of the circuit. It also derives control signals that are
required for controlling external system bus

29. List the features of 8051 microcontroller?

The features are

Single supply +5 volt operation using HMOS technology.
4096 bytes program memory on chip (not on 8031)
128 data memory on chip.
Four register banks.
Two multiple mode, 16-bit timer/counter.
Extensive Boolean processing capabilities.
64 KB external RAM size
32 bidirectional individually addressable I/O lines.
8 bit CPU optimized for control applications.

30. What is the use of timing and control unit?

34
 Timing and control unit is used to deliver all the necessary timing and control
signals required for the internal operation of the circuit. It also derives control signals
that are required for controlling external system bus

31. What are the usage of TIMER and COUNTER? (MAY 2007 ECE)
Timers are used to measure time intervals, determine pulse width (or) initiate events
With one microsecond resolution up to a maximum 65 ms. We use software to get
Longer delay.

32. What are the features of ROM and RAM in 8051 micro controller? (NOV 2006 ECE)

ROM is 4 K and RAM is 128 bytes in 8051

33. What is interrupt latency? (MAY 2007 ECE) (MAY 2007 ECE)

34. What is the function of program counter in 8051? (NOV 2006 ECE)
When program is executed address of the instruction which has to be executed
will be present in PC.

35. Name any four conditional jump instructions of 8051 (NOV 2006 ECE)
1. JZ 2.JNZ, 3.JC 4.JNC
36. What is the use of DA instruction in 8051? (NOV 2006 ECE)

DA instruction in 8051 is used to convert hexadecimal number into BCD number

35