ZXG10 IBSC (V6.20.62) Hardware Description

ZXG10 iBSC
Base Station Controller

Hardware Description
Version: V6.20.62
ZTE CORPORATION
NO. 55, Hi-tech Road South, ShenZhen, P.R.China
Postcode: 518057
Tel: +86-755-26771900
Fax: +86-755-26770801
URL: http://ensupport.zte.com.cn
E-mail: support@zte.com.cn
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The ultimate right to interpret this product resides in ZTE CORPORATION.
Revision History
Revision No. Revision Date Revision Reason
R1.0 2011-09-29 First edition
Serial Number: SJ-20110909163609-003
Publishing Date: 2011-09-29(R1.0)

Contents
About This Manual ......................................................................................... I
Chapter 1 Overview .................................................................................... 1-1
1.1 Product Description ............................................................................................ 1-1
1.2 Hardware Architecture ........................................................................................ 1-1
Chapter 2 Cabinet....................................................................................... 2-1

2.1 Cabinet Appearance........................................................................................... 2-1
2.2 Cabinet Structure ............................................................................................... 2-2
2.2.1 Cabinet Top ............................................................................................. 2-2
2.2.2 Front/Rear Door ....................................................................................... 2-7
2.2.3 Rack........................................................................................................ 2-8
2.2.4 Busbar..................................................................................................... 2-9
2.3 Cabinet Assembly ............................................................................................ 2-10
2.4 External Connections ........................................................................................2-11
2.5 Cabinet Cabling ............................................................................................... 2-15
2.6 Cabinet Processing Features ............................................................................ 2-16
Chapter 3 Subrack...................................................................................... 3-1

3.1 Power Distribution Subrack ................................................................................. 3-1
3.1.1 Functions................................................................................................. 3-1
3.1.2 Structure.................................................................................................. 3-1
3.1.3 Panel....................................................................................................... 3-2
3.2 Fan Subrack ...................................................................................................... 3-4
3.2.1 Functions................................................................................................. 3-4
3.2.2 Structure.................................................................................................. 3-4
3.2.3 Panel....................................................................................................... 3-4
3.3 Dust-proof Subrack ............................................................................................ 3-5
Chapter 4 Shelf ........................................................................................... 4-1

4.1 Shelf Overview................................................................................................... 4-1
4.1.1 Shelf Functions ........................................................................................ 4-1
4.1.2 Shelf Classification ................................................................................... 4-1
4.1.3 Shelf Position........................................................................................... 4-2
4.1.4 Backplane................................................................................................ 4-3
4.2 Shelf Description (for Resource Shelf) ................................................................. 4-3
4.2.1 Control Shelf (BCTC)................................................................................ 4-3
I
4.2.2 Packet Switching Shelf (BPSN) ................................................................4-11
4.2.3 Resource Shelf (BUSN) .......................................................................... 4-15
4.3 Shelf Description (for GB Resource Shelf) ......................................................... 4-19
4.3.1 Control Shelf (BCTC).............................................................................. 4-19
4.3.2 Switching Shelf (BPSN) .......................................................................... 4-25
4.3.3 Gigabit Resource Shelf (BGSN) .............................................................. 4-29
4.4 Inter-Shelf Connection ...................................................................................... 4-33
4.4.1 Internal Connections (Using BUSN)......................................................... 4-33
4.4.2 Internal Connections (Using BGSN)......................................................... 4-40
Chapter 5 Board.......................................................................................... 5-1

5.1 Board Description............................................................................................... 5-1
5.2 BSC IP Interface Board (BIPI) ............................................................................. 5-2
5.2.1 BIPI Functions ......................................................................................... 5-2
5.2.2 BIPI Principle ........................................................................................... 5-2
5.2.3 BIPI Panel ............................................................................................... 5-3
5.2.4 BIPI Interfaces ......................................................................................... 5-4
5.2.5 BIPI Buttons............................................................................................. 5-5
5.2.6 BIPI Indicators ......................................................................................... 5-5
5.3 Control Plane HUB (CHUB) ................................................................................ 5-6
5.3.1 CHUB Functions ...................................................................................... 5-6
5.3.2 CHUB Principle ........................................................................................ 5-6
5.3.3 CHUB Panel ............................................................................................ 5-7
5.3.4 CHUB Interfaces ...................................................................................... 5-8
5.3.5 CHUM Buttons ......................................................................................... 5-9
5.3.6 CHUB Indicators .................................................................................... 5-10
5.4 Clock Generator Board CLKG (CLKG)................................................................5-11
5.4.1 CLKG (CLKG) Functions .........................................................................5-11
5.4.2 CLKG (CLKG) Principle ...........................................................................5-11
5.4.3 CLKG (CLKG) Panel .............................................................................. 5-12
5.4.4 CLKG (CLKG) Interfaces ........................................................................ 5-13
5.4.5 CLKG (CLKG) Buttons............................................................................ 5-15
5.4.6 CLKG (CLKG) Indicators ........................................................................ 5-16
5.4.7 CLKG (CLKG) Jumpers .......................................................................... 5-18
5.5 Clock Generator Board CLKG (ICM).................................................................. 5-19
5.5.1 CLKG (ICM) Functions ........................................................................... 5-19
5.5.2 CLKG (ICM) Principle ............................................................................. 5-19
5.5.3 CLKG (ICM) Panel ................................................................................. 5-21
II
5.5.4 CLKG (ICM) Interfaces ........................................................................... 5-21
5.5.5 CLKG (ICM) Buttons............................................................................... 5-24
5.5.6 CLKG (ICM) Indicators ........................................................................... 5-24
5.5.7 CLKG (ICM) DIP Switches ...................................................................... 5-27
5.6 Control Main Processing (CMP) Board .............................................................. 5-27
5.6.1 CMP Functions ...................................................................................... 5-27
5.6.2 CMP Principle ........................................................................................ 5-27
5.6.3 CMP Panel ............................................................................................ 5-28
5.6.4 CMP Interfaces ...................................................................................... 5-29
5.6.5 CMP Buttons ......................................................................................... 5-29
5.6.6 CMP Indicators ...................................................................................... 5-30
5.7 Digital Trunk Board (DTB) ................................................................................. 5-31
5.7.1 DTB Functions ....................................................................................... 5-31
5.7.2 DTB Principle......................................................................................... 5-31
5.7.3 DTB Panel ............................................................................................. 5-32
5.7.4 DTB Interfaces ....................................................................................... 5-34
5.7.5 DTB Buttons .......................................................................................... 5-34
5.7.6 DTB Indicators ....................................................................................... 5-34
5.7.7 DTB DIP Switches and Jumpers.............................................................. 5-35
5.8 E1 IP Interface Board (EIPI).............................................................................. 5-37
5.8.1 EIPI Functions ....................................................................................... 5-37
5.8.2 EIPI Principle ......................................................................................... 5-38
5.8.3 EIPI Panel ............................................................................................. 5-38
5.8.4 EIPI Interfaces ....................................................................................... 5-39
5.8.5 EIPI Buttons........................................................................................... 5-39
5.8.6 EIPI Indicators ....................................................................................... 5-40
5.9 GB Line Interface (GLI) Board ........................................................................... 5-40
5.9.1 GLI Functions ........................................................................................ 5-40
5.9.2 GLI Principle .......................................................................................... 5-40
5.9.3 GLI Panel .............................................................................................. 5-41
5.9.4 GLI Interfaces ........................................................................................ 5-42
5.9.5 GLI Buttons............................................................................................ 5-43
5.9.6 GLI Indicators ........................................................................................ 5-43
5.10 GB Line Interface (GLI4) Board ....................................................................... 5-44
5.10.1 GLI4 Functions..................................................................................... 5-44
5.10.2 GLI4 Principle ...................................................................................... 5-44
5.10.3 GLI4 Panel........................................................................................... 5-44
III
5.10.4 GLI4 Interfaces .................................................................................... 5-45
5.10.5 GLI4 Buttons........................................................................................ 5-46
5.10.6 GLI4 Indicators..................................................................................... 5-46
5.11 Gigabit Ethernet Network Interface (GIPI) Board............................................... 5-47
5.11.1 GIPI Functions ..................................................................................... 5-47
5.11.2 GIPI Principle ....................................................................................... 5-47
5.11.3 GIPI Panel ........................................................................................... 5-48
5.11.4 GIPI Interfaces ..................................................................................... 5-49
5.11.5 GIPI Buttons......................................................................................... 5-50
5.11.6 GIPI Indicators ..................................................................................... 5-50
5.12 Gigabit Universal Interface Module (GUIM) ...................................................... 5-51
5.12.1 GUIM Functions ................................................................................... 5-51
5.12.2 GUIM Principle ..................................................................................... 5-52
5.12.3 GUIM Panel ......................................................................................... 5-53
5.12.4 GUIM Interfaces ................................................................................... 5-53
5.12.5 GUIM Buttons ...................................................................................... 5-54
5.12.6 GUIM Indicators ................................................................................... 5-55
5.13 Gigabit Universal Interface Module (GUIM2) .................................................... 5-56
5.13.1 GUIM2 Functions ................................................................................. 5-56
5.13.2 GUIM2 Principle ................................................................................... 5-57
5.13.3 GUIM2 Panel ....................................................................................... 5-57
5.13.4 GUIM2 Interfaces ................................................................................. 5-58
5.13.5 GUIM2 Buttons .................................................................................... 5-59
5.13.6 GUIM2 Indicators ................................................................................. 5-59
5.14 GSM Universal Processing (GUP) Board ......................................................... 5-60
5.14.1 GUP Functions..................................................................................... 5-60
5.14.2 GUP Principle ...................................................................................... 5-60
5.14.3 GUP Panel........................................................................................... 5-62
5.14.4 GUP Interfaces .................................................................................... 5-63
5.14.5 GUP Buttons........................................................................................ 5-63
5.14.6 GUP Indicators..................................................................................... 5-64
5.15 GSM Universal Processing (GUP2) Board 2..................................................... 5-64
5.15.1 GUP2 Functions................................................................................... 5-64
5.15.2 GUP2 Principle .................................................................................... 5-65
5.15.3 GUP2 Panel......................................................................................... 5-66
5.15.4 GUP2 Interfaces................................................................................... 5-67
5.15.5 GUP2 Buttons ...................................................................................... 5-67
IV
5.15.6 GUP2 Indicators................................................................................... 5-68
5.16 Integrated Clock Module (ICM) ........................................................................ 5-68
5.16.1 ICM Functions...................................................................................... 5-68
5.16.2 ICM Principle ....................................................................................... 5-69
5.16.3 ICM Panel............................................................................................ 5-70
5.16.4 ICM Interfaces...................................................................................... 5-70
5.16.5 ICM Buttons ......................................................................................... 5-73
5.16.6 ICM Indicators...................................................................................... 5-73
5.16.7 ICM DIP Switches ................................................................................ 5-76
5.17 Operation and Maintenance Processing (OMP) Board ...................................... 5-77
5.17.1 OMP Functions .................................................................................... 5-77
5.17.2 OMP Principle ...................................................................................... 5-77
5.17.3 OMP Panel .......................................................................................... 5-77
5.17.4 OMP Interfaces .................................................................................... 5-78
5.17.5 OMP Buttons ....................................................................................... 5-79
5.17.6 OMP Indicators .................................................................................... 5-79
5.18 Packet Switching Network (PSN) Board ........................................................... 5-80
5.18.1 PSN Functions ..................................................................................... 5-80
5.18.2 PSN Principle....................................................................................... 5-80
5.18.3 PSN Panel ........................................................................................... 5-81
5.18.4 PSN Interfaces ..................................................................................... 5-82
5.18.5 PSN Buttons ........................................................................................ 5-82
5.18.6 PSN Indicators ..................................................................................... 5-83
5.19 Power Distribution (PWRD) Board ................................................................... 5-83
5.19.1 PWRD Functions.................................................................................. 5-83
5.19.2 PWRD Principle ................................................................................... 5-84
5.19.3 PWRD Panel........................................................................................ 5-84
5.19.4 PWRD DIP Switches and Jumpers ........................................................ 5-85
5.20 Server Board (SBCX) ..................................................................................... 5-86
5.20.1 SBCX Functions................................................................................... 5-86
5.20.2 SBCX Principle .................................................................................... 5-86
5.20.3 SBCX Panel......................................................................................... 5-87
5.20.4 SBCX Interfaces................................................................................... 5-88
5.20.5 SBCX Buttons ...................................................................................... 5-89
5.20.6 SBCX Indicators................................................................................... 5-90
5.21 SONET Digital Trunk Board (SDTB) ................................................................ 5-91
5.21.1 SDTB Functions ................................................................................... 5-91
V
5.21.2 SDTB Principle..................................................................................... 5-91
5.21.3 SDTB Panel ......................................................................................... 5-92
5.21.4 SDTB Interfaces................................................................................... 5-94
5.21.5 SDTB Buttons ...................................................................................... 5-94
5.21.6 SDTB Indicators ................................................................................... 5-94
5.22 SONET Digital Trunk Board2 (SDTB2)............................................................. 5-95
5.22.1 SDTB2 Functions ................................................................................. 5-95
5.22.2 SDTB2 Principle................................................................................... 5-95
5.22.3 SDTB2 Panel ....................................................................................... 5-96
5.22.4 SDTB2 Interfaces ................................................................................. 5-98
5.22.5 SDTB2 Buttons .................................................................................... 5-98
5.22.6 SDTB2 Indicators ................................................................................. 5-98
5.23 Signaling Processing Board (SPB)................................................................... 5-99
5.23.1 SPB Functions ..................................................................................... 5-99
5.23.2 SPB Principle ......................................................................................5-100
5.23.3 SPB Panel ..........................................................................................5-100
5.23.4 SPB Interfaces ....................................................................................5-101
5.23.5 SPB Buttons .......................................................................................5-102
5.23.6 SPB Indicators ....................................................................................5-102
5.23.7 SPB DIP Switches and Jumpers...........................................................5-103
5.24 Signaling Processing Board 2 (SPB2) .............................................................5-105
5.24.1 SPB2 Functions ..................................................................................5-105
5.24.2 SPB2 Principle ....................................................................................5-105
5.24.3 SPB2 Panel ........................................................................................5-106
5.24.4 SPB2 Interfaces ..................................................................................5-107
5.24.5 SPB2 Buttons......................................................................................5-108
5.24.6 SPB2 Indicators ..................................................................................5-108
5.25 Universal Interface Module for Control Plane (UIMC) .......................................5-109
5.25.1 UIMC Functions ..................................................................................5-109
5.25.2 UIMC Principle ....................................................................................5-109
5.25.3 UIMC Panel ........................................................................................ 5-110
5.25.4 UIMC Interfaces .................................................................................. 5-111
5.25.5 UIMC Buttons...................................................................................... 5-112
5.25.6 UIMC Indicators .................................................................................. 5-112
5.26 Universal Interface Module for User Plane (UIMU)........................................... 5-113
5.26.1 UIMU Functions .................................................................................. 5-113
5.26.2 UIMU Principle .................................................................................... 5-113
VI
5.26.3 UIMU Panel ........................................................................................ 5-114
5.26.4 UIMU Interfaces .................................................................................. 5-115
5.26.5 UIMU Buttons...................................................................................... 5-116
5.26.6 UIMU Indicators .................................................................................. 5-116
5.27 User Plane Processing Board (UPPB) ............................................................ 5-118
5.27.1 UPPB Functions.................................................................................. 5-118
5.27.2 UPPB Principle ................................................................................... 5-118
5.27.3 UPPB Panel........................................................................................ 5-119
5.27.4 UPPB Interfaces..................................................................................5-120
5.27.5 UPPB Buttons .....................................................................................5-120
5.27.6 UPPB Indicators..................................................................................5-121
Chapter 6 Auxiliary Equipment ................................................................. 6-1

6.1 Alarm Box (ALB) ................................................................................................ 6-1
6.1.1 ALB Functions ......................................................................................... 6-1
6.1.2 Principle .................................................................................................. 6-2
6.1.3 Panel....................................................................................................... 6-4
6.1.4 Interfaces ................................................................................................ 6-5
6.1.5 Buttons.................................................................................................... 6-7
6.1.6 Indicators................................................................................................. 6-7
6.1.7 Connection Mode ..................................................................................... 6-8
6.2 Relevant GPS Devices ....................................................................................... 6-9
6.2.1 GPS Active Antenna and Lightning Protector/Frequency Divider ................. 6-9
6.2.2 GPS L1 Signal Transponder and GPS Antenna Feeder Lightning
Protector .............................................................................................. 6-12
Chapter 7 System Configuration............................................................... 7-1

7.1 Overview ........................................................................................................... 7-1
7.2 Resource Shelf .................................................................................................. 7-1
7.2.1 E1 at Abis and A Interfaces....................................................................... 7-1
7.2.2 IP+E1 at Abis and E1 at A-Interface .......................................................... 7-2
7.2.3 IP+E1 at Abis and STM-1 at A-Interface .................................................... 7-3
7.2.4 IPoE at Abis and E1 at A-Interface ............................................................ 7-4
7.2.5 E1 at Abis and STM-1 at A Interface.......................................................... 7-5
7.2.6 E1 at Abis and E1 (Outer TC) at Ater......................................................... 7-6
7.2.7 E1 at Abis and STM-1 (Outer TC) at Ater ................................................... 7-7
7.3 GB Resource Shelf............................................................................................. 7-8
7.3.1 E1 (T1) used at Abis and A Interfaces........................................................ 7-8
7.3.2 E1 at Abis and STM-1 at A Interface.......................................................... 7-9
VII
7.3.3 E1 at Abis and IP at A-Interface .............................................................. 7-10
7.3.4 IP at Abis and A Interfaces.......................................................................7-11
7.3.5 IP at Abis and E1 (T1) at A-Interface ....................................................... 7-12
7.3.6 IP at Abis and STM-1 at A-Interface......................................................... 7-13
7.3.7 IPoE at Abis and E1 (T1) at A-Interface ................................................... 7-14
7.3.8 IPoE at Abis and STM-1 at A-Interface .................................................... 7-15
7.3.9 IPoE at Abis and IP at A Interface ........................................................... 7-16
7.3.10 E1 (T1) at Abis and Ater Interfaces ........................................................ 7-17
7.3.11 IP at Abis and E1 (T1) at Ater ................................................................ 7-18
Appendix A Explanation of Combined Indicator States ........................ A-1

Figures............................................................................................................. I
Tables ...........................................................................................................VII
Glossary ........................................................................................................XI
VIII
About This Manual
Purpose
ZXG10 is a GSM mobile communication system independently developed by ZTE
Corporation. It consists of ZXG10 MSS and ZXG10 BSS. ZXG10 BSS provides and
manages radio transmission in GSM, composed of BSC and BTS.
ZXG10 iBSC is a third-generation BSC product of ZTE. It features large capacity,
high reliability, cost-effectiveness, comprehensive functionality, and powerful service
provisioning.
ZXG10 iBSC software system comprises NetNumen M31 and OMM. NetNumen M31 is
the universal wireless network element management system. It manages and maintains
the entire network. OMM implements local operation and maintenance for iBSC. Its
hardware platform uses SBCX board, which is set inside an iBSC rack. iBSC is connected
to NetNumen M31 through OMM.
This manual introduces the hardware system of ZXG10 iBSC, including cabinet, subracks,
boards, auxiliary device, and system configuration.
Intended Audience
l System engineer
l Maintenance engineer
l Installation engineer
What is in This Manual

This manual has the following chapters.
Chapter Description
Chapter 1, Overview Describes the hardware structure of ZXG10 iBSC.
Chapter 2, Cabinet Describes the structure of ZXG10 iBSC cabinet.
Chapter 3, Subrack Describes the function, structure and panel of ZXG10 iBSC subrack.
Chapter 4, Shelf Describes the type and description of ZXG10 iBSC shelf and its
connection.
Chapter 5, Board Describes the functions, panels, interfaces, indicators, DIP switches,
and jumpers on the ZXG10 iBSC board.
Chapter 6, Auxiliary Device Describes the functions and structures of the ZXG10 iBSC auxiliary
device.
I
Chapter Description
Chapter 7, System Describes the configuration under the different transmission modes in
Configuration the ZXG10 iBSC system
Appendix A, Description of Describes the meaning of combination of RUN and ALM indicators.
Combined Indicator States
II
Chapter 1
Overview
Table of Contents
Product Description ....................................................................................................1-1
Hardware Architecture................................................................................................1-1
1.1 Product Description

ZXG10 is a GSM mobile communication system independently developed by ZTE
Corporation. It comprises ZXG10 MSS and ZXG10 BSS. Composed of BSC and
BTSZXG10 BSS provides and manages radio transmission in GSM.
ZXG10 iBSC is a third-generation BSC product of ZTE. It features large capacity,
high reliability, cost-effectiveness, comprehensive functionality and powerful service
provisioning. ZXG10 iBSC system consists of NetNumen M31 and Operation and
Maintenance Module (OMM).
NetNumen M31 is the universal wireless network element management system. It
manages and maintains the entire network. OMM implements local operation and
maintenance for iBSC. Its hardware platform uses SBCX board, which is set inside an
iBSC rack. iBSC is connected to NetNumen M31 through OMM.
1.2 Hardware Architecture

The ZXG10 iBSC hardware consists of cabinet, subracks, shelves, boards, and other
hardware equipments. The hardware configuration varies depending on the actual
situation.
The hardware architecture of ZXG10 iBSC is shown in Table 1-1.
Table 1-1 Hardware Architecture Description
Component Description
Introduces the structure and composition of ZXG10 iBSC cabinet,

Cabinet including cabinet appearance, structure, assembly, and cabling.
Introduces the function, structure and panel of ZXG10 iBSC sub-

Subrack rack.
Explains the configuration and backplane descriptions of shelves

Shelves used in ZXG10 iBSC.
Introduces the function, indicator, button, jumper and DIP Switch

Board of ZXG10 iBSC board.
1-1
SJ-20110909163609-003|2011-09-29(R1.0) ZTE Proprietary and Confidential

ZXG10 iBSC Hardware Description
Component Description
Describes the functions, principle, and panels of the alarm box, its
connection mode with iBSC equipment, GPS antenna lightening
Other Hardware Equipments protector, GPS antenna, and forwarder.
1-2

Chapter 2
Cabinet
Table of Contents
Cabinet Appearance...................................................................................................2-1
Cabinet Structure .......................................................................................................2-2
Cabinet Assembly ....................................................................................................2-10
External Connections ...............................................................................................2-11
Cabinet Cabling........................................................................................................2-15
Cabinet Processing Features ...................................................................................2-16
2.1 Cabinet Appearance

Figure 2-1 shows the ZXG10 iBSC cabinet appearance.
Figure 2-1 ZXG10 iBSC Cabinet Appearance
ZXG10 iBSC cabinet is compliant with the CompactPCI standard. The cabinet body and
its front door are navy blue, the latter with the compact vents.
2-1

2.2 Cabinet Structure

Figure 2-2 shows the ZXG10 iBSC cabinet composition.
Figure 2-2 Cabinet Components
1. Cover 5. Service subrack 9. Side door

2. Filter 6. Installing base 10. Rack
3. Fiber wrap tTray 7. Rear door
4. Front door 8. Busbar
The ZXG10 iBSC cabinet comprises of cabinet top, front door, rear door, rack, subrack,
and busbar.
2.2.1 Cabinet Top

The ZXG10 iBSC power input port, cable outlet module, top fan, and additional fiber
processing modules are placed at the cabinet top.
Figure 2-3 shows the appearance of cabinet top appearance.
2-2

Chapter 2 Cabinet
Figure 2-3 Appearance of Cabinet Top
The cabinet top consists of top frame component, cable outlet module, top fan, top filter
and fiber wrap tray. Figure 2-4 shows the structure of cabinet top.
Figure 2-4 Structure of Cabinet Top
1. Fiber wrap tray 4. Filter cover 7. Top frame component

2. Top fan cover 5. Cable oulet module
3. Top fan 6. Top filter
2-3

Top Frame Component

It is the base of different function units at the cabinet top. The grounding bolts in the top
frame component are the general grounding parts with the grounding identifier nearby.
Its structure is shown in Figure 2-5.
Figure 2-5 Structure of Top Frame Component
1. Base plate for outlet module 3. Grounding label 5. Installation base of

2. Installation plate for top 4. Grounding bolt Cabinet-Top Fan
filter
Cable Oulet Module

The cable outlet module is the path from/to the cabinet for the signal cable, comprising of
outlet frames and bars (11 bars). Figure 2-6 shows the structure of outlet module.
2-4

Chapter 2 Cabinet
Figure 2-6 Structure of Outlet Module
1. Outlet frame 2. Outlet bar
Top Fan
The top fan is the important part for ventilation. The top fan comprises of base plate, (6)
fans, and monitoring circuit board.
Figure 2-7 shows the structure of the top fan.
Figure 2-7 Structure of Top Fan
1. Monitor circuit board 2. Fan 3. Installation base
2-5

Top Filter
It is the power input interface. The -48 V power cable from the equipment room is mounted
at its input terminal and the output terminal connects the power subrack in the cabinet.
Figure 2-8 shows the structure of the top filter.
Figure 2-8 Top Filter
1. Power input 2. Power output
Fiber Wrap Tray

It is the device to wrap the additional fibers, which comprises of base plate, fiber post, and
cover.
Figure 2-9 shows the structure of the fiber wrap tray.
2-6

Chapter 2 Cabinet
Figure 2-9 Structure of Fiber Wrap Tray
1. Cover 2. Fiber wrap post 3. Base plate
2.2.2 Front/Rear Door

The structure of front and rear door are similar to each other. Tiny ventilation holes on the
doors help to cool the cabinet.
Office information label and serial No. label are affixed on the top right corner of front door.
Figure 2-10 shows the label information (If only one label is required, its distance from the
edge shall be 120 mm).
Figure 2-10 Office Information Label and Serial No. Label
1. Office information label 2. Serial No. label
l Office information label
2-7

Office information label contains the cabinet consignment information for unpacking
check, such as product name, consignment number and recipients address.
l Serial No. lLabel
Serial No. label contains the cabinet serial number.
2.2.3 Rack
Rack consists of top frame, bottom frame, column, adjustment rail, and side door, as shown
in Figure 2-11.
Figure 2-11 Rack Structure
1. Top frame 2. Polar 3. Adjustment track
2-8

Chapter 2 Cabinet
4. Side door 5. Bottom frame
Note:
For multiple cabinets in a single row, only the leftmost and rightmost door at the two ends
of the row need be installed.
2.2.4 Busbar
Busbar is used for providing power supply and grounding of ZXG10 iBSC system. Figure
2-12 show the busbar appearance.
Figure 2-12 Busbar
Bus bars are located at the right side of rear cabinet. There are six groups of terminals.
1. From top to bottom, there are four terminals in group 1 and 6, listed as follows:
l -48 V
l -48 V GND
l PE
l PE
2-9

2. Group 1 connects the power distribution subrack and provides power supply input for
busbar.
3. Group 6 provides power supply for the third fan subrack.
4. Group 2 ~ 5 provide power supply for different fan subracks and shelves.
There are six connection terminals for these groups:
l -48 V
l -48 V GND
l -48 V
l -48 V GND
l PE
l PE
2.3 Cabinet Assembly

ZXG10 iBSC cabinet can assemble:
l Four layers of 9 U shelves;
l A layer of 2 U power distribution subrack;
l Three layers of 1 U fan subrack;
l A layer of 1 U dummy panel.
Figure 2-13 shows the structure of ZXG10 iBSC cabinet.
2-10

Chapter 2 Cabinet
Figure 2-13 Cabinet Layout
1. Power distribution subrack 3. 1 U dummy panel 5. Dust-proof subrack

2. Fan subrack 4. Shelves
2.4 External Connections

External equipments connected with iBSC include BTS, MSC/MGW, SGSN, NetNumen
M31, and iTC.
The external connection may vary while resource shelf (BUSN) or GB resource shelf
(BGSN) is used.
2-11

External Connections (Using BGSN)

The external connections for BGSN is shown in Figure 2-14.
Figure 2-14 Connection of iBSC and Peripheral Device for GB Resource Shelf
In Figure 2-14, the blue line represents the E1 connection, the red line represents the fiber
connection, and the azury broken line represents the Ethernet connection.
1. A-Interface
There are three physical bearing modes at the A-interface between iBSC and
MSC/MGW.
a. STM-1 mode
It is implemented by the optical port on the front panel of SDTB2.
b. E1 mode
It is implemented by the E1 port on rear board RDTB of DTB and rear board RSPB
of SPB2.
c. Ethernet mode
It is implemented by the GE optical port on the front panel of GIPI or the GE electric
port on rear board RGER.
2. Gb interface
There are two physical bearing modes at the Gb interface between iBSC and SGSN.
a. E1 mode
It is implemented by the E1 port on the rear board SPB2.
b. Ethernet mode
It is implemented by the GE optical port on the front panel of GIPI or the GE electric
3. Abis interface
There are three physical bearing modes at the Abis interface between iBSC and BTS.
2-12

Chapter 2 Cabinet
a. STM-1 mode
b. E1 mode
It is implemented by the E1 port on rear board RDTB of DTB and rear board RSPB
of SPB2.
c. Ethernet mode
It is implemented by the GE optical port on front panel of GIPI or the GE electric
4. Ater Interface
There are two physical bearing modes at the interface Ater between iBSC and iTC.
a. STM-1 mode
b. E1 mode
It is implemented by the E1 port on rear board RSPB of SPB2 and rear board
RDTB of DTB.
5. Connection with OMM
It is implemented by the FE interface of rear board RMPB for OMP and the FE interface
of rear board SBCX for RSVB. OMM interacts with NetNumen M31 mobile element
management system.
6. Connection with OMCB (SDR OMC)
It is implemented by the FE interface on the rear board of GIPI.
7. Connection with MR server
It is implemented by the FE interface on the rear board of GIPI.
External Connections (Using BUSN)

The external connections for BUSN is shown in Figure 2-15.
Figure 2-15 Connection of iBSC and Peripheral Device for Resource Shelf
2-13

In Figure 2-15, the blue line represents the E1 connection, the red line represents the fiber
connection, and the azury broken line represents the FE connection.
1. A-Interface
There are two physical bearing modes at the A-interface between iBSC and
MSC/MGW.
a. STM-1 mode
It is implemented by the optical port on the front panel of SDTB.
b. E1 mode
It is implemented by the E1 port on the rear board RDTB of DTB.
2. Gb interface
There are two physical bearing modes at the Gb interface between iBSC and SGSN.
a. E1 mode
It is implemented by the E1 port on the rear board RSPB of SPB.
b. FE mode
It is implemented by the FE interface on the rear board RMNIC of BIPI.
3. Abis interface
There are three physical bearing modes at the Abis interface between iBSC and BTS.
a. E1 mode
It is implemented by the E1 port on the rear board RDTB of DTB.
b. FE mode
c. STM-1 mode
4. Ater Interface
There are two physical bearing modes at the Ater interface between iBSC and iTC.
a. STM-1 mode
b. E1 mode
It is implemented by the E1 port on rear board RSPB of SPB or rear board RDTB
of DTB.
5. Connection with OMM
It is implemented by the FE interface of rear board RMPB of OMP and the FE
interface of rear board SBCX of RSVB. OMM interacts NetNumen M31 mobile
element management system.
6. Connection with OMCB (SDR OMC)
2-14

Chapter 2 Cabinet

7. Connection with MR server
2.5 Cabinet Cabling

Figure 2-16 shows the ZXG10 iBSC cabinet cabling.
Figure 2-16 Cabinet Cabling (Left View)
1. Leading out cables from 2. Leading out cables from 4. Vertical cable trough
cabinet rear board 5. Leading out optical fibers
3. Rear transverse cable rack from front
In ZXG10 iBSC cabinet, the optical fiber is led out from the front board panel, while other
cables are led out from the rear board panel.
2-15

2.6 Cabinet Processing Features

ZXG10 iBSC has excellent processing designs in terms of power supply, grounding,
dustproof, heat dissipation, and electromagnetic compatibility (EMC).
Power Supply
1. The system working voltage is -48 V DC, with a fluctuation ranging from -40 V DC to
-57 V DC.
2. An entirely distributed power supply mode is used. The power supply module on the
board implements conversion of the -48 V power supply into that needed by the board
(such as +5/+3.3/+2.5/1.8 V DC) and isolation between them.
3. The ingress of the cabinet power is power distribution subrack. The power distribution
subrack has two power inputs. Use the switch to select one channel to supply power
for all shelves and the fan subrack. The two inputs are mutually backed up. The -48
V power is piped downwards from the power distribution subrack through busbar. The
powers for each shelf and the fan subrack come from the same -48 V busbar.
Grounding
There are two types of grounding:
1. -48 V GND: -48 V ground.
2. GNDP: system protection ground.
For each shelf, board GND and static GNDE connect with GNDP via shelf filter, and the
rack busbar PE; they also connect rack GNDP with the grounding busbar in equipment
room via right PE post at the top of rack.
Note:
Judgement method of left & right PE post: viewed from the rear of the cabinet to the
front of the cabinet, the left one is left PE post and the right one is right PE post.
-48 V GND is led out from power subrack, and connects -48 VGND of different
subsystems via a busbar.
-48 V GND firmly connects with the GNDP in equipment room.

The rack provides top grounding and bottom grounding. If conditions permit, the
protection ground wire can be grounded through an independent grounding post.
Rack bonding resistance is 0.1 ~ 0.3 Ω, and the grounding resistance shall be less
than 1 Ω in equipment room.
2-16

Chapter 2 Cabinet
Dustproof Measures
1. A dustproof net is installed at the air inlet at the bottom of the cabinet. It uses ABS
plastic as the frame, which joins nylon net. The flexibility provides convenience for
installation and uninstallation.
2. The door air filter uses metal as the frame, with polyurethane second foaming plastic
inside.
Both types of air filters can be reused after being cleaned, and are easy for installation and
disassembling.
Heat Dissipation
Figure 2-17 shows the heat dissipation duct of ZXG10 iBSC.
2-17

Figure 2-17 Heat Dissipation Duct of ZXG10 iBSC
EMC
The EMC design is manifested in the shielding and grounding processing of the rack and
subrack.
The shielding design is adopted at subrack level. When the frequency is within the range
30 MHz to 1 GHz, the minimum shielding characteristic is 40 dB.
The subracks support EMC shielding functions. The surfaces are totally electroplated to
ensure the excellent conductivity.
2-18

Chapter 2 Cabinet
The joints between subrack and plug-in unit and between plug-in units are conducted by
conductive springs.
To ensure grounding, anti-static grounding devices are reserved on the subrack for the
connection of subrack and rack.
2-19

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2-20

Chapter 3
Subrack
Table of Contents
Power Distribution Subrack ........................................................................................3-1
Fan Subrack...............................................................................................................3-4
Dust-proof Subrack ....................................................................................................3-5
3.1 Power Distribution Subrack

3.1.1 Functions
The power distribution subrack is located above the cabinet and used to supply power for
the whole cabinet.
Functions of the power distribution subrack are as follows:
1. Provides power to all shelves and fan subracks within a cabinet.
2. Implements power backup by automatically switching over two external power
supplies.
3. With the Power Distribution Board (PWRD) and the Power Distributor Backplane
(PWRDB) installed inside, implements power indication, environment monitoring, and
internal fan subrack monitoring.
3.1.2 Structure
Figure 3-1 shows the structure of power distribution subrack.
Figure 3-1 Structure of Power Distribution Subrack
1. Terminal 4. Shelf 7. PWRD

2. Lightning protector 5. Heat sink for isolating diode 8. Switch
3. PWRDB 6. Isolating diode
3-1

The line connection terminal of power distribution subrack is installed on the rear frame.
The energy safety cover is added at the rear cover. The front panel of the subrack is fixed
with Power Distribution Board (PWRD). The front panel can be turned 90º outward, which
facilitates maintenance.
When the equipment is running, captive fastener can be used to fix the front panel in the
subrack.
3.1.3 Panel
The front plate of the power distribution box is shown in Figure 3-2.
Figure 3-2 Front Panel of Power Subrack
The rear panel of the power distribution subrack is shown in Figure 3-3.
Figure 3-3 Rear Panel of Power Subrack
1. Indicator Description
There are eight indicators on the front panel of the power distribution subrack. Table
3-1 explains the panel indicators.
Table 3-1 Indicators on Panel of Power Distribution Subrack
Name Color Meaning Description
Flashes at 1 Hz: normal running

RUN green Running indicator OFF: abnormal
ON: the first -48 V power supply has

The first -48 V under-voltage or over-voltage alarm
-48 V (I) Red alarm indicator OFF: no alarm
ON: the second -48 V power supply has

The second -48 V under-voltage or over-voltage alarm
-48 V (II) Red alarm indicator OFF: no alarm
ON: the fan has abnormal alarm

FAN Red Fan alarm indicator OFF: no alarm
3-2

Chapter 3 Subrack
ON: the environment temperature has

Temperature alarm abnormal alarm
HOT Red indicator OFF: no alarm
Smoke alarm indi- ON: abnormal smoke alarm

SMOKE Red cator OFF: no alarm
Access control ON: abnormal access control alarm

DOOR Red alarm indicator OFF: no alarm
ON: the lightning protector has abnormal

Lightning protector alarm
ARRESTER Red alarm indicator OFF: no alarm
2. Switches
There are two switches on the front panel. Table 3-2 shows the description of the
switches.
Table 3-2 Switches on Panel of Power Distribution Subrack
Switch Name Description
Down: Disconnect -48 V input

-48 V (I) power input switch Up: Connect -48 V input
Down: Disconnect -48 V input

-48 V (II) power input switch Up: Connect -48 V input
3. Interface Description
Input/Output cables of power distribution and monitoring are connected to the power
distribution subrack through the interfaces. Table 3-3 explains the interfaces of the
power distribution subrack.
Table 3-3 Interfaces of Power Distribution Subrack
Interface Description
RS485 (Up) Connects PD485 of the OMP rear board
RS485 (Down) Connects the RS485 (up) of the adjacent rack
SENSORS Connects sensor cable
DOOR Connects door access cable
FANBO X1 Connects the top fan group
FANBO X2 Connects the fan subrack at layer 1
ARRESTER Connects the lightning arrester.
3-3

INPUT (I) Power input
INPUT (II) Power input
OUTPUT Power output
3.2 Fan Subrack

3.2.1 Functions
The fan subrack monitors and performs automatic rate adjustment, forming a closed wind
channel through which wind comes in from the bottom and goes out from the top in the
cabinet. The fan subrack cools the equipment with wind flow.
3.2.2 Structure
Figure 3-4 shows the structure of fan subrack.
Figure 3-4 Structure of Fan Subrack
Each fan subrack consists of three units. Each unit contains two fans. This structure
facilitates the operations such as onsite maintenance and hot swapping.
3.2.3 Panel
The front panel of the fan subrack is shown in Figure 3-5.
Figure 3-5 Front Panel of Fan Subrack
The rear board of the fan subrack is shown in Figure 3-6.
3-4

Chapter 3 Subrack
Figure 3-6 Rear Panel of Fan Subrack
1. Monitor socket 2. Power socket
1. Indicator Description
A fan subrack consists of three fan units. Each fan unit has two indicators. Totally,
there are six indicators on the front panel of fan subrack.
Table 3-4 explains the panel indicators.
Table 3-4 Indicators on the Panel of Fan Subrack
Running ON: The fan module is running properly.

RUN Green indicator OFF: The fan module is running improperly.
ON: There is exceptional alarm in the fan

Alarm module.
ALM Red indicator OFF: There is no alarm in the fan module.
2. Buttons
Each of the three fan units in the fan subrack has one button on the front panel. Press
the button to pull out the fan unit.
The fan subrack interfaces are located at the rear board. Table 3-5 describes the
interfaces.
Table 3-5 Interfaces of Fan Subrack
Connected to FANBOX2 ~ FANBOX4 in power

Monitor distribution subrack
POWER Power socket
3.3 Dust-proof Subrack

The dust-proof subrack is fixed on the bottom of the cabinet.
Air filters are available in the dust-proof subrack, easy to be removed for cleaning and
maintenance.
3-5

3-6

Chapter 4
Shelf
Table of Contents
Shelf Overview ...........................................................................................................4-1
Shelf Description (for Resource Shelf)........................................................................4-3
Shelf Description (for GB Resource Shelf)................................................................4-19
Inter-Shelf Connection..............................................................................................4-33
4.1 Shelf Overview

4.1.1 Shelf Functions
The shelf combines different boards into different function units and provides a good
running environment for the boards. Each shelf contains 17 standard board slots.
4.1.2 Shelf Classification

ZXG10 iBSC system includes four kinds of shelves: control shelf (BCTC), resource shelf
(BUSN), GB resource shelf (BGSN), and packet switching shelf (BPSN).
Table 4-1 shows the shelf classification and function description.
Table 4-1 Shelf Description
Shelf Type Functions
Control shelf is the control core of ZXG10 iBSC system, which

manages and controls the whole system, processes control
plane signaling, performs operation and maintenance, and
Control shelf (BCTC) provides a global clock and external synchronization function.
Resource shelf holds different types of service processing

boards and forms various general service processing
subsystems (the data at user plane is switched by MB mode
Resource shelf (BUSN) in the shelf).
Resource shelf holds different types of service processing

boards and forms various general service processing
subsystems (the data at user plane is switched by GB mode
Gigabit resource shelf (BGSN) in the shelf).
Packet switching shelf provides the IP switching platform with

Packet switching shelf (BPSN) a large capacity.
4-1

4.1.3 Shelf Position

Figure 4-1 shows the positions of different shelves in ZXG10 iBSC when the GB resource
shelf is used.
Figure 4-1 Positions of Different Shelves for the GB Resource Shelf
Figure 4-2 shows the positions of different shelves in ZXG10 iBSC when the resource shelf
is used.
Figure 4-2 Positions of Different Shelves for the Resource Shelf
If you use the ZXG10 iBSC system of resource shelf for expansion, you can add the GB
resource shelf for the whole shelf. You shall note that the boards for resource shelf and
GB resource shelf can not be inserted in mixed mode.
If the ZXG10 iBSC uses BUSN or BGSN, the configuration, principle, and backplane may
be varied for different shelves. The section below describes the different shelves for BUSN
and BGSN.
4-2

Chapter 4 Shelf
4.1.4 Backplane
Backplane is an important component of a shelf. Circuit boards in a shelf connect through
printed lines on the backplane. This reduces the cable routing on the backplane and
improves reliability of the entire system.
Figure 4-3 shows the backplane structure.
Figure 4-3 Backplane Structure
1. Fixing screw 3. Positioning hole

2. Connector 4. Connector
The shelf corresponds to the backplane. The corresponding relation is shown in Table 4-2.
Table 4-2 Relationship Between Shelf and Backplane
Shelf Backplane
Packet switching shelf Backplane of packet switching network (BPSN)
Control shelf Backplane of control center (BCTC)
Resource shelf Backplane of universal service network (BUSN)
Gigabit resource shelf Backplane of gigabit service network (BGSN)
4.2 Shelf Description (for Resource Shelf)

4.2.1 Control Shelf (BCTC)
Control shelf is the control core of ZXG10 iBSC. It manages and controls the whole system,
handles the control plane signal, operation and maintenance of the iBSC system, and
provides the clock supply and clock synchronization for the distributed processing platform.
4-3

Each iBSC should be equipped with a control shelf. The control shelf should be located in
shelf 2 cabinet 1.
Configuration
Table 4-3 shows the boards that can be configured by the control shelf.
Table 4-3 The boards that can be configured by the control shelf
Front board Rear board Backplane
Operation and Maintenance

Processing Board (OMP) Rear board of OMP (RMPB)
Control Main Processing Board

(CMP ) -
Universal Interface Module for Rear Board 2 of UIM (RUIM2)

Control Plane (UIMC) Rear Board 3 of UIM (RUIM3)
Rear board 1 of CHUB (RCHB1)

Control Plane HUB (CHUB) Rear board 2 of CHUB (RCHB2)
Clock Generator Board CLKG Rear Board 1 of CLKG (RCKG1)

(CLKG) Rear Board 2 of CLKG (RCKG2)
Backplane of control center
Server board (SBCX) Rear board of server (RSVB) (BCTC)
The configuration of control shelf is shown in Figure 4-4.
Figure 4-4 Configuration of Control Shelf
The board configuration in the control shelf is described as follows.

1. There are two OMP boards for active and standby configuration. They are inserted
into slots 11 and 12 and are mandatory.
2. There are 2 ~ 4 CMP boards inserted in slot 5 ~ 8. The number of CMP boards
depends on the required capacity.
4-4

Chapter 4 Shelf
Note:
If the processing capacity should be expanded, CMP also can be inserted into other
shelves. The BPSN shelf is suggested.
3. There are two CLKG boards for active and standby configuration. They are inserted
into slot 13 & 14 and are mandatory.
Note:
CLKG in Figure 4-4 is one of CLKG (CLKG) and CLKG (ICM). You can use a pair of
boards for same type and can not use the different boards in mixed insertion mode.
4. There are two CHUB boards for active and standby configuration. They are inserted
5. There are two UIMC boards for active and standby configuration. They are inserted
6. A SBCX board should be configured. The SBCX board is inserted in slot 1 and rear
board RSVB is inserted in slot 1.
Principles
Figure 4-5 shows the working principle of control shelf.
4-5

Figure 4-5 Principle of Control Shelf
1. Inter-shelf Communication Functions

a. In the iBSC system, you can set a pair of CLKGs. In normal case, CLKG is set
in the control shelf and distributes the system clock for packet switching shelf and
different resource shelves through the cable.
b. OMC2 network port for the OMP rear board and OMP1 network port for the SBCX
rear board are connected through HUB. The OMC1 network port for the SBCX rear
board connects to the external network through another HUB and implements the
isolation between inner and outer network segments. OMM is installed on the
SBCX board.
c. The CHUB board is used as the hub of control flow to centrally connect packet
switching shelf, resource shelf, and control flow from control shelf.
2. Intra-shelf Communication Functions

a. The BCTC backplane is used to carry signal processing board and different
master modules to connect and handle the control plane and form the distributed
processing platform in the multi-shelves equipment.
4-6

Chapter 4 Shelf
b. The UIMC board is the signal switching center of control shelf, used to finish the
information exchange among different modules.
c. The OMP board implements the control of operation and maintenance in the whole
system (including operation and maintenance agent).
The OMP board is the core of ZXG10 iBSC operation and maintenance,
directly and indirectly monitors and manages the boards in the system, provides
the Ethernet and RS485 interfaces for the system boards for configuration
management.
d. SBCX can be used as the OMM server and also can save some files required by
OMP. Also, you can organize these files according to the format required by OMM.
e. The CMP board connects on the switching unit at control plane and handles the
protocols at all control planes.
Backplane
The backplane for the control shelf is the BCTC backplane, with two versions, such as
040203 and 060201.
Figure 4-6 shows the rear view of BCTC with version 040203.
Figure 4-6 Rear Viw of BCTC Backplane with Version 040203
Figure 4-7 shows the rear view of BCTC with version 060201.
4-7

Figure 4-7 Rear Viw of BCTC Backplane with Version 060201
060201 version of the BCTC backplane uses the RBID rear board and collects the DIP
switches on RBID, as shown in Figure 4-8.
4-8

Chapter 4 Shelf
Figure 4-8 Layout of DIP Switch on RBID
1. Power supply interface

Table 4-4 describes the power interfaces for control shelf.
Table 4-4 Description of Power Interfaces for Control Shelf
Interface ID Purpose Connection Relation
Through the power filter of subrack, X1 and X2

are connected to -48 V, -48 VGND, and PE sig-
X1, X2 Power socket nal post for the rack busbar in parallel.
2. DIP Switches on Backplane
Table 4-5 shows the description of DIP switches for the backplane.
4-9

Table 4-5 Description of DIP Switches for the Backplane
DIP Purpose Example
4-position switch
S1 only uses the left 3 positions and X2 only uses
the bottom 3 positions.
S2/X3 uses all 4 positions.
The office information for
S1/X2 the target shelf
The rack information for All S1/X2 switches are ON: the value is binary
S2/X3 the target shelf "000";
All S2/X3 switches are ON: the value is binary
"0000";
Two positions for the S3/X4 switch are OFF and
other positions are ON: the value is binary "11".
From above description: 0, 0, and 3 are set for
S1/X2, S2/X3, and S3/X4. The actual rack id
and shelf id should be added by 1, so the setting
indicates that the BCTC shelf is located at: office
S3/X4 Shelf information 0, rack 1, and shelf 4.
Note:
There are DIP switches for BPSN, BCTC, and BUSN. Its ON/OFF setting method is
same.
OFF: Set to the lower position, represented by 1.

ON: Set to the upper position, represented by 0.
You also can use the jumpers to set the shelf information on the field. At this time,
a jumper indicates a number. There are 3 4-way jumpers, corresponding to the
information of office, rack, and shelf. For the specific information, refer to Table 4-5.
OFF: Unplug the short-circuit block, represented by 1.
ON: Plug the short-circuit block, represented by 0.
Note:
The DIP switches on RBID and backplane can not be effective at the same time. If
you use RBID, all DIP switches on the backplane should be set to OFF, that is, all
represented by 1111.
4-10

Chapter 4 Shelf
4.2.2 Packet Switching Shelf (BPSN)

BPSN provides the IP switching function for the data at user plane for different function
entities in the iBSC system and can provide the proper QoS function for the different users.
Each iBSC system shall be equipped with a packet switching shelf, configured at layer 4
in the primary cabinet.
Configuration
Table 4-6 shows the boards that can be configured in the packet switching shelf.
Table 4-6 Boards That can be Configured in Packet Switching Shelf
Packet Switching Network

(PSN) Board -
Gigabit Line Interface (GLI)

Board -

(CMP ) -
Rear Board 2 of UIM (RUIM2)

Universal Interface Module for Backplane of packet switching
Control Plane (UIMC) Rear Board 3 of UIM (RUIM3) network (BPSN)
Figure 4-9 shows the configuration of the packet switching shelf.
Figure 4-9 Configuration of Packet Switching Shelf
1. The packet switching shelf provides the level I IP switching platform for the system,
used by the user plane with multiple resource shelves. The packet switching shelf also
can directly provide the high-speed external interface.
2. Intra-Shelf Board Configuration
4-11

a. There are two UIMC boards to implement the switching function at control plane
for the packet switching shelf. The boards are inserted into slots 15 and 16 and
are mandatory.
b. There are two PSN boards to implement the data switching function between line
cards. The boards are inserted into slots 7 and 8 and are mandatory.
c. There are 2 ~ 4 GLI boards to implement the function of GE line card. The boards
can be inserted in slots 1 ~ 4. The number of boards depends on the configuration
capacity. You shall follow the direction from left to right.
d. There are 0 ~ 2 CMP boards for active and standby configuration. A pair of boards
are set per 1024 carriers and can be inserted in slot 11 ~ 14.
e. There is a RUIM2 board inserted in slot 15 and is mandatory.
f. There is a RUIM3 board inserted in slot 16 and is mandatory.
Principle
Figure 4-10 shows the principle of the packet switching shelf.
Figure 4-10 Principle of Packet Switching Shelf
1. Inter-Shelf Communication Functions
a. The different resource shelves are connected to the GLI of switching shelf through
the optical port on front panel of the UIMU board.
b. The control shelf connects the UIMC for switching shelf through the rear boards
RCHB1 and RCHB2 for the CHUB board.
c. The clock signal connects the UIMC for switching shelf through the rear boards
RCKG1 and RCKG2 for CLKG, to implement the clock transmission.
2. Intra-Shelf Communication Functions
4-12

Chapter 4 Shelf
a. Data at user plane

l The packet switching shelf accesses to the data at user plane through GLI.
l Then, the data is sent to the packet switching network (PSN) board through
the high-speed signal cable on the backplane.
l Finally, GLI receives the switched data from PSN, finishes the proper
handling, and sends the data to destination port.
b. Data at control plane
UIMC switching takes the Ethernet bus as the inner control bus in the subsystem,
connects the different subsystem modules, implements the distribution and
collection of route information and the configuration maintenance management.
Meanwhile, it implements the delivery of high-layer protocol and signaling data.
Backplane
The backplane for the packet switching shelf is BPSN. It has two versions, 040203 and
070200.
Figure 4-11 shows the rear view of BPSN with version 040203.
Figure 4-11 Rear Viw of BPSN Backplane with Version 040203
Figure 4-12 shows the rear view of BPSN with version 070200.
4-13

Figure 4-12 Rear Viw of BPSN Backplane with Version 070200

Table 4-7 shows the description of power interfaces for packet switching shelf.
Table 4-7 Description of Power Interfaces for Packet Switching Shelf
Through the secondary power filter of subrack, X1,

X2, and X3 are connected to -48 V, -48 VGND, and
X1, X2, X3 Power socket PE signal post for the rack busbar in parallel.

The DIP switches on the BPSN backplane (S1/X2, S2/X3, and S3/X4) are similar to
those on the BCTC backplane. The DIP switches are used to set the information of
office, rack, and shelf. For the specific setting methods, refer to "Description of DIP
Switches on Backplane".
Note:
On the field, you can use the RBID backplane and collect the DIP switches on RBID.
For RBID, refer to "Layout of DIP Switches on RBID". X2 corresponds to S1, X3
corresponds to S2, and X4 corresponds to S3. The DIP switches on RBID and
backplane can not be effective at the same time. If you use RBID, all DIP switches on
the backplane shall be set to OFF, that is, all represented by 1111.
4-14

Chapter 4 Shelf
4.2.3 Resource Shelf (BUSN)

The resource shelf is used as the universal service shelf and can hold different service
processing boards, to form the different universal service processing subsystem. The
resource shelf can set Abis interface unit, A interface unit, PCU unit, TC unit, and Ater
interface unit.
There is no special limit on the position of resource shelf that is set at layer 1 & 3 in cabinet
1 and can be set at any layer in cabinet 2.
Configuration
Table 4-8 shows the boards that can be configured by the resource shelf.
Table 4-8 The boards that can be configured by the resource shelf
Rear Digital Trunk Board

Digital Trunk Board (DTB) (RDTB)
SONET Digital Trunk Board General Rear Interface Module

(SDTB) 1 (RGIM1)
Universal Interface Module for

User Plane (UIMU) Rear Board 1 of UIMU (RUIM1)
GSM Universal Processing

Board (GUP) -
BSC IP Interface Board (BIPI) Rear board of MNIC (RMNIC)
Signaling Processing Board

(SPB) Rear Board of SPB (RSPB)
User Plane Processing Board

(UPPB) -


(CMP ) -
Backplane Of Universal Service
E1 IP interface board (EIPI) - Network (BUSN)
There are multiple configurations for resource shelf. Here takes FE+E1 at Abis and E1 at
A interface as the example. The configuration of resource shelf is shown in Figure 4-13.
4-15

Figure 4-13 Configuration of Resource Shelf
The board configuration in the resource shelf is described as follows.

1. There are two UIMU boards inserted into slot 9 & 10 and are mandatory.
2. DTB can be set in any slot other than 9, 10, 15, and 16. The number of consecutive
DTB boards can not be more than 3; it is difficult for routing at slot 1/17 and DTB is not
recommended; 6 DTBs are suggested for each shelf, up to 8.
3. SDTB can be set in any slot other than 9 and 10. If it is not the active/standy
configuration, slot 17 is preferred. If you insert into other slot, the adjacent slot for
active/standby slot can not be set to use the boards for HW line resource, such as
DTB and GUP.
4. If GUP is used as BIPB/TIPB, slots 5~8 and 11~14 are preferred. If it is inserted into
slots 1~4 and 15~16, the board that does not use the network port at media plane can
be set in the adjacent slots for active/standby GUP board, such as DTB and SDTB. If
GUP is used as DRTBk, it can be inserted into any slot other than 9 & 10.
5. SPB can be inserted in any slot other than 9 & 10. However, only one can be inserted
in slot 15 or 16.
6. UPPB is recommended to be inserted in slots 5~8 and 11~14. If it is inserted into slots
1~4 and 15~16, the board that does not use the network port at inner media plane can
be set in the adjacent slots for active/standby UPPB board, such as DTB and SDTB.
7. BIPI shall be first inserted in slots 5~8 and 11~14.
8. The EIPI board shall be first inserted in slot 5~8 and 11~14. If the EIPI board is set
in the slot for active/standby board, the board that uses HW line resource can not be
set in adjacent slots, such as DTB, SPB, and SDTB. If it is inserted into slots 1~4 and
15~16, the board can not be set in adjacent EIPI slots.
9. If an office only contains a shelf, you shall set the OMP board inserted in slot 11 & 12.
Set the CMP on demands and insert it in slot 13 & 14.
Principles
Figure 4-14 shows the working principle of resource shelf.
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Chapter 4 Shelf
Figure 4-14 Principle of Resource Shelf

a. The UIMU board provides the control Ethernet channel for external resource shelf
and connects the CHUB board in control hub for control shelf.
The UIMU board connects the GLI board for the packet switching shelf to
implement the level I switching between different resource boards.
b. The DTB and SPB boards provide the E1 line interface.
c. The SDTB board provides the STM-1 access.
d. BIPI provides the FE access.
e. The CLKG board in control shelf distributes the system clock to different resource
shelves through the cable.
a. BUSN, as the backplane of resource shelf, can hold the different service
processing modules to form the universal service processing subsystem.
b. UIMU is the connection and switching center for different data in the resource
shelf, to finish the information switching among the different modules.
c. UPPB handles the relevant radio protocols at user plane.
d. GUP implements the TC transcoder conversion, rate adaption, and handover from
TDM to IP packet.
Backplane
The backplane for the resource shelf is BUSN. There are two versions: 040202 and
040203.
4-17

Figure 4-15 shows the BUSN rear view with version 040202.
Figure 4-15 Rear Viw of BUSN Backplane with Version 040202
Figure 4-16 shows the BUSN rear view with version 040203.
Figure 4-16 Rear View of BUSN Backplane with Version 040203
Table 4-9 shows the description of power interfaces for resource shelf.
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Chapter 4 Shelf
Table 4-9 Description of Power Interfaces for Resource Shelf
Through the power filter of subrack, X1 and

X2 are connected to -48 V, -48 VGND, and
X1, X2 Power Socket PE signal post for the rack busbar in parallel.
The DIP switches on the BUSN backplane (S1/X2, S2/X3, and S3/X4) are similar to
those on the BCTC backplane. The DIP switches are used to set the information of
office, rack, and shelf. For the specific setting methods, refer to "Description of DIP
Switches on Backplane".
Note:
On the field, you can use the RBID backplane and collect the DIP switches on RBID.
For RBID, refer to "Layout of DIP Switches on RBID". X2 corresponds to S1, X3
corresponds to S2, and X4 corresponds to S3. The DIP switches on RBID and
backplane can not be effective at the same time. If you use RBID, all DIP switches on
the backplane shall be set to OFF, that is, all represented by 1111.
4.3 Shelf Description (for GB Resource Shelf)

4.3.1 Control Shelf (BCTC)
Control shelf is the control core of ZXG10 iBSC. It manages and controls the whole system,
handles the control plane signal, operation and maintenance of the iBSC system, and
provides the clock supply and clock synchronization for the distributed processing platform.
Each iBSC shall be equipped with a control shelf. The control shelf shall be located in
shelf 2 cabinet 1.
Configuration
Table 4-10 shows the boards that can be configured by the control shelf.
4-19

Table 4-10 The boards that can be configured by the control shelf


(CMP ) -
Universal Interface Module for Rear Board 2 of UIM (RUIM2)

Control Plane (UIMC) Rear Board 3 of UIM (RUIM3)
Rear board 1 of CHUB (RCHB1)

Control Plane HUB (CHUB) Rear board 2 of CHUB (RCHB2)
Clock Generator Board CLKG Rear Board 1 of CLKG (RCKG1)

(CLKG) Rear Board 2 of CLKG (RCKG2)
Rear Board 1 of CLKG (RCKG1)

Integrated Clock Module (ICM) Rear Board 2 of CLKG (RCKG2)
Backplane of control center
Server board (SBCX) Rear board of server (RSVB) (BCTC)
The configuration of control shelf is shown in Figure 4-17.
Figure 4-17 Configuration of Control Shelf
The board configuration in the control shelf is described as follows.
1. There are two OMP boards for active and standby configuration. They are inserted
2. There are 2~4 OMP boards for active and standby configuration. They can be inserted
into slot 1 & 4. The number of OMP boards depend on the required capacity.
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Chapter 4 Shelf
Note:
If the processing capacity shall be expanded, CMP also can be inserted into other
shelves. The BPSN shelf is suggested.
3. There are two SBCX boards for active and standby configuration. The boards can be
inserted into slot 5 & 7.
4. There are two CLKG/ICM boards for active and standby configuration. They are
inserted into slot 13 & 14 and are mandatory.
Note:
You shall use one of CLKG (ICM) and ICM. You can use a pair of boards for same type
and can not use the different boards in mixed insertion mode.
5. There are two CHUB boards for active and standby configuration. They are inserted
6. There are two UIMC boards for active and standby configuration. They are inserted
7. There is a RUIM2 board inserted into slot 9 and is mandatory.
8. There is a RUIM3 board inserted into slot 10 and is mandatory.
9. There are two RMPB boards inserted into slot 11 & 12 and are mandatory.
10. There is a RCKG1 board inserted in slot 13.
11. There is a RCKG2 board inserted in slot 14.
12. There is a RCHB1 board inserted in slot 15.
13. There is a RCHB2 board inserted in slot 16.
14. There are two RSVB boards inserted in slot 5 & 7.
15. There is a RBID board configured on the BCTC shelf.
Principles
Figure 4-18 shows the working principle of control shelf.
4-21

Figure 4-18 Principle of Control Shelf
1. Inter-shelf Communication Functions

a. In the iBSC system, you can set a pair of CLKG/ICMs. In normal case, CLKG/ICM
is set in the control shelf and distributes the system clock for packet switching shelf
and different GB resource shelves through the cable.
b. OMC2 network port for the OMP rear board and OMP1 network port for the SBCX
rear board are connected through HUB. The OMC1 network port for the SBCX rear
board connects to the external network through another HUB and implements the
isolation between inner and outer network segments. OMM is installed on the
SBCX board.
c. The CHUB board is used as the hub of control flow to centrally connect packet
switching shelf, GB resource shelf, and control flow from control shelf.
2. Intra-shelf Communication Functions

a. The BCTC backplane is used to carry signal processing board and different
master modules to connect and handle the control plane and form the distributed
processing platform in the multi-shelves equipment.
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Chapter 4 Shelf
b. The UIMC board is the signal switching center of control shelf, used to finish the
information exchange among different modules.
c. The OMP board implements the control of operation and maintenance in the whole
system (including operation and maintenance agent).
The OMP board is the core of ZXG10 iBSC operation and maintenance,
directly and indirectly monitors and manages the boards in the system, provides
the Ethernet and RS485 interfaces for the system boards for configuration
management.
d. SBCX can be used as the OMM server and also can save some files required
by OMP. Also, you can organize these files according to the formats required by
OMM.
e. The CMP board connects on the switching unit at control plane and handles the
protocols at all control planes.
Backplane
The backplane for the control shelf is the BCTC backplane, with version 060201. Figure
4-19 shows the rear view.
Figure 4-19 Rear View of BCTC Backplane
1. Power Interfaces
Table 4-11 shows the description of power interfaces for control shelf.
4-23

Table 4-11 Description of Power Interfaces for Control Shelf
Through the power filter of subrack, X1 and X2

are connected to -48 V, -48 VGND, and PE sig-
X1, X2 Power socket nal post for the rack busbar in parallel.
The DIP switches for the backplane are located on RBID, as shown in Figure 4-20.
Figure 4-20 Layout of DIP Switch on RBID
Table 4-12 shows the description of DIP switches for the backplane.
4-24

Chapter 4 Shelf
Table 4-12 Description of DIP Switches for the Backplane
Name of DIP
Switch Purpose Example
4-position switch
S2/X3 uses all 4 positions.
The office information
S1/X2 for the target shelf
The rack information All S1/X2 switches are ON: the value is binary
S2/X3 for the target shelf "000";
All S2/X3 switches are ON: the value is binary
"0000";
Two positions for the S3/X4 switch are OFF and
other positions are ON: the value is binary "11".
From above description: 0, 0, and 3 are set for
S1/X2, S2/X3, and S3/X4. The actual rack id and
shelf id shall be added by 1, so the setting indicates
that the BCTC shelf is located at: office 0, rack 1,
S3/X4 Shelf information and shelf 4.
Note:
There are DIP switches for BPSN, BCTC, and BGSN. Its ON/OFF setting method is
same.
OFF: Set to the lower position, represented by 1.
ON: Set to the upper position, represented by 0.
You also can use the jumpers to set the shelf information on the field. At this time,
a jumper indicates a number. There are 3 4-way jumpers, corresponding to the
information on office, rack, and shelf. For the specific meaning, refer to Table 4-12.
OFF: Unplug the short-circuit block, represented by 1.
ON: Plug the short-circuit block, represented by 0.
4.3.2 Switching Shelf (BPSN)

BPSN provides the IP switching function for the data at user plane for different function
entities in the iBSC system and can provide the proper QoS function for the different users.
Each iBSC system shall be equipped with a packet switching shelf, configured at layer 4
in the primary cabinet.
4-25

Configuration
Table 4-13 shows the boards that can be configured by the packet switching shelf.
Table 4-13 The Boards That can be Configured by Packet Switching Shelf
Packet Switching Network

(PSN) Board -
Gigabit Line Interface (GLI)

Board -

(CMP ) -
Universal Interface Module for Rear Board 2 of UIM (RUIM2) Backplane of packet switching
Control Plane (UIMC) Rear Board 3 of UIM (RUIM3) network (BPSN)
Figure 4-21 shows the configuration of packet switching shelf.
Figure 4-21 Configuration of Packet Switching Shelf
1. The packet switching shelf provides the level I IP switching platform for the system,
used by the user plane with multiple resource shelves. The packet switching shelf
also can directly provide the high-speed external interface. Each pair of GLIs provide 8
pair of optical ports for active/standby configuration. 3 pairs of GLI exactly introduce 24
pairs of optical ports, connected to 24 pairs of active/standby optical ports for resource
shelf GUIM at layer 6. Each GUIM board uses two pairs of optical ports.
2. Intra-shelf Board Configuration
a. There are two UIMC boards to implement the switching function at control plane
for the packet switching shelf. It is active/standby configuration, inserted in slots
15 and 16 and mandatory.
b. There are two PSN boards to implement the data switching function between line
cards. Load balancing, inserted in slots 7 ~ 8 and mandatory.
4-26

Chapter 4 Shelf
c. There are 2 ~ 6 GLI boards to implement the function of GE line card. The boards
can be inserted in slots 1 ~ 6. The number of boards depends on the configuration
capacity. You shall follow the direction from left to right for load balancing.
d. There are 0 ~ 2 CMP boards for active and standby configuration. A pair of boards
are set per 1024 carriers and can be inserted in slot 11~14.
e. There is a RUIM2 board inserted in slot 15 and is mandatory.
f. There is a RUIM3 board inserted in slot 16 and is mandatory.
g. There is a RBID board configured on the BPSN shelf.
Principles
Figure 4-22 shows the principle of packet switching shelf when the GB resource shelf is
used.
Figure 4-22 Principle of Packet Switching Shelf

a. The different resource shelves are connected to the GLI of switching shelf through
the optical port on front panel of the GUIM board.
b. The control shelf connects the UIMC for switching shelf through the rear boards
RCHB1 and RCHB2 for the CHUB board.
c. The clock signal connects the UIMC for switching shelf through the rear boards
RCKG1 and RCKG2 for CLKG/ICM, to implement the clock transmission.
a. Data at user plane
l The packet switching shelf accesses to the data at user plane through GLI.
l Then, the data is sent to the packet switching network (PSN) board through
the high-speed signal cable on the backplane.
4-27

l Finally, GLI receives the switched data from PSN, finishes the proper
handling, and sends the data to destination port.
b. Data at control plane
UIMC switching takes the Ethernet bus as the inner control bus in the subsystem,
connects the different subsystem modules, implements the distribution and
collection of route information and the configuration maintenance management.
Meanwhile, it implements the delivery of high-layer protocol and signaling data.
Backplane
The backplane for the packet switching shelf is the BPSN, with version 070200. Figure
4-23 shows the rear view.
Figure 4-23 Rear View of BPSN Backplane
1. Backplane Interface
Table 4-14 shows the description of power interfaces for packet switching shelf.
Table 4-14 Description of Power Interfaces for Packet Switching Shelf
Through the secondary power filter of subrack, X1, X2,

and X3 are connected to -48 V, -48 VGND, and PE sig-
X1, X2, X3 Power socket nal post for the rack busbar in parallel.

The DIP switches on the BPSN backplane (X2, X3, and X4) are located on RBID,
similar to those on the BCTC backplane. The DIP switches are used to set the
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Chapter 4 Shelf
information of office, rack, and shelf. For the specific setting methods, refer to
"Description of DIP Switches on Backplane".
4.3.3 Gigabit Resource Shelf (BGSN)

The GB resource shelf is used as the universal service shelf and can hold the different
service processing boards, to form the different universal service processing subsystem.
The GB resource shelf can set Abis interface unit, A-interface unit, PCU unit (that is, GIU
unit), TC unit, and Ater interface unit.
There is no special limit on the position of GB resource shelf that is set at layer 1 & 3 in
cabinet 1 and can be set at any layer in cabinet 2.
Configuration
Table 4-15 shows the boards that can be configured by the GB resource shelf.
Table 4-15 The boards that can be configured by the GB resource shelf
Digital Trunk Board (DTB) Rear Digital Trunk Board (RDTB)
SONET Digital Trunk Board General Rear Interface Module 1

(SDTB2) (RGIM1)
Rear board 1 for GUIM (RGUM1)

Gigabit Universal Interface and rear board 2 for GUIM
Module (GUIM) (RGUM2)
GSM Universal Processing

board (GUP2) -
Rear Card of GE for BUSN and

Gigabit Ethernet Network In- BGSN (RGER)
terface Card (GIPI) Rear board of MNIC (RMNIC)
Signaling Processing Board

(SPB2) Rear Board of SPB2 (RSPB)
E1 IP interface board (EIPI) -

Control Main Processing Backplane of gigabit service net-

Board (CMP ) - work (BGSN)
There are multiple configurations for GB resource shelf. Here takes E1 or IPOE at Abis,
E1 at A interface, E1 at Gb as the example. The configuration of GB resource shelf is
shown in Figure 4-24.
4-29

Figure 4-24 Configuration of GB Resource Shelf
The board configuration in the GB resource shelf is described as follows.

1. There are two GUIM boards for active and standby configuration. They are inserted
in slots 9 & 10 and are mandatory. There is a multi-mode fiber to connect the level I
switching.
2. DTB can be set in any slot other than 9, 10, 15, and 16. The number of consecutive
DTB boards can not be more than 3; it is difficult for routing at slot 1/17 and DTB is not
recommended; 6 DTBs are suggested for each shelf, up to 8.
3. SDTB2 can be set in any slot other than 9, 10, and 17 as active/standby configuration.
The SDTB2 panel has two pairs of single-mode fiber. If STDB2 is not the
active/standby configuration and the board is set in the slot for active/standby
board, you can not use the board that uses the HW line resource in the adjacent
active/standby slot, such as DTB, GUP2, SPB2, and EIPI.
4. GUP2 can be inserted in any slot other than 9, 10, 1, and 17.
5. SPB2 can be inserted in any slot other than 9 & 10. However, only one can be inserted
in slot 15 or 16.
6. GIPI can be inserted in any slot other than slots 9 & 10. However, only a board can
be inserted in slot 15/16. The panel has a GB optical port. Or, you can set the RGER
rear card to have an external GB electric port. Or, set the RMNIC rear card to have 4
MB electric port for active/standby configuration.
The GIPI board is used to provide the OMCB channel or can be inserted in slots 5~8,
13, and 14 for active/standby configuration while connecting the MR server. At this
time, the GIPI board provides four FE externally and internally, The used rear card is
RMNIC.
7. EIPI can be inserted in any slot other than slots 9 & 10. However, only a board can be
inserted in slot 15 or 16.
8. If an office contain one or two shelves, you shall set the OMP board inserted in slot 11
& 12. Set the CMP on demands and insert it in slots 11~14.
9. If SDTB2, SPB2, GIPI, EIPI, and GUP2 are set in slot 15/16, TDM trunk board can not
extract line 8K clock reference and you can not use the serial port in slot 16.
4-30

Chapter 4 Shelf
10. There are RGUM1 and RGUM2 inserted in slots 9 & 10 and are mandatory.
11. RDTB, RSPB, and RGER/RMNIC are set properly with the front board.
12. The rear card RGIM1 for the SDTB2 board is used to extract 8K clock from STM-1 line.
If the line clock is not required to extract, the configuration is not required. In normal
case, if the number of configured SDTB2 is more than 1, you shall set two RGIM1. Set
two cables for clock extraction.
13. There is a RBID board configured on the BGSN shelf.
Principles
Figure 4-25 shows the working principle of GB resource shelf.
Figure 4-25 Principle of GB Resource Shelf

a. The GUIM board provides the control Ethernet channel for external GB resource
shelf and connects the CHUB board in control hub for control shelf.
The GUIM board connects the GLI board for the packet switching shelf to
implement the level I switching between different resource boards.
b. The DTB and SPB2 boards provide the E1 line interface.
c. The SDTB2 board provides the STM-1 access.
d. GIPI provides the GE access.
e. EIPI provides the E1/T1-based IP access, in combination with DTB or SDTB2.
f. The CLKG/ICM board in control shelf distributes the system clock to different GB
resource shelves through the cable.
4-31

a. BGSN, as the backplane of GB resource shelf, can hold the different service
processing modules to form the universal service processing subsystem.
b. GUIM is the connection and switching center for different data in the GB resource
shelf, to finish the information switching among the different modules.
c. GUP2 handles the relevant radio protocol at user plane, TC transcoder conversion,
and handover from TDM to IP packet.
d. GIPI provides a GB electric port or four MB interfaces through the backplane at
media plane.
Backplane
The backplane for GB resource shelf is BGSN. Figure 4-26 shows its rear view.
Figure 4-26 Rear View of BGSN Backplane
1. Backplane Interface
Table 4-16 shows the description of power interfaces for GB resource shelf.
Table 4-16 Description of Power Interfaces for GB Resource Shelf
Through the power filter of subrack, X1, X2, and

X3 are connected to -48 V, -48 VGND, and PE
X1, X2, X3 Power Socket signal post for the rack busbar in parallel.

The DIP switches on the BGSN backplane (X2, X3, and X4) are located on RBID,
similar to those on the BCTC backplane. The DIP switches are used to set the
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Chapter 4 Shelf
information of office, rack, and shelf. For the specific setting methods, refer to
"Description of DIP Switches on Backplane".
4.4 Inter-Shelf Connection

The inner wiring for the ZXG10 iBSC system is used to connect the signal among the inner
boards in the system.
The inner connection may be varied while resource shelf (BUSN) or GB resource shelf
(BGSN) is used. The section below explains it in two cases.
4.4.1 Internal Connections (Using BUSN)

Single Cabinet
1. For single cabinet, the cables in the ZXG10 iBSC system contains:
a. Clock distribution cable and line clock extraction cable;
b. Ethernet cable at control plane;
c. Fiber at user plane;
d. Monitoring cable.
2. Wiring Instance Description

a. Clock extraction distribution
Figure 4-27 shows the wiring of clock extraction distribution in an iBSC cabinet.
4-33

Figure 4-27 Wiring of Clock Extraction Distribution In an iBSC Cabinet for

Resource Shelf
Note:
In Figure 4-27, CLKG refers to CLKG(CLKG) or CLKG(ICM). Both CLKG(CLKG)
and CLKG(ICM) can provide the clock. Other paragraphs in this section is same
as this, no more explanation later. DTB, STDB, SDTB2, and SPB can extract the
clock signal for CLKG. This figure only takes DTB as an example.
There are the following modes for clock extraction distribution.

l Clock extraction for reference clock base
Extracts the line clock from CN through the interface board and send it to the
CLKG board.
The CLKG board also can input the BITS clock base.
l Clock Distribution
Connect the UIMU/UIMC board in different shelves from rear boards RCKG1
& RCKG2 for the CLKG board through the clock cable and distribute to
different slots in local shelf by UIMU/UIMC.
b. Ethernet interconnection at control plane
Figure 4-28 shows the Ethernet interconnection at control plane.
4-34

Chapter 4 Shelf
Figure 4-28 Ethernet Connection at Control Plane in an iBSC Cabinet for

Resource Shelf
In Figure 4-28, real line represents the cable connection and dashed line
represents the printed connection on the backplane.
The Ethernet interconnection at control plane for the iBSC system can be
implemented by the CHUB board. The Ethernet interconnection mode at control
plane is described as follows.
l Connect CHUB to UIMC for resource shelf and packet switching shelf through
the cable.
l The UIMC board for the control shelf directly connects the CHUB board
through the printed lines on the backplane.
c. Interconnection at user plane

The connection at user plane for an iBSC cabinet is shown in Figure 4-29.
4-35

Figure 4-29 Wiring at User Plane in an iBSC Cabinet for Resource Shelf
The user plane interconnects in the iBSC system, the user plane in a resource
shelf interconnects through backplane, the user plane among different resource
shelves interconnect through the GLI and PSN boards in the packet switching
shelf. That is, connect the UIMU and GLI boards for all resource shelves through
the fibers.
d. Monitoring cable connection
Figure 4-30 shows the connection of monitoring cable in an iBSC cabinet.
4-36

Chapter 4 Shelf
Figure 4-30 Wiring of Monitoring Cables in an iBSC Cabinet for Resource Shelf
The fan subrack and power subrack are connected through the cables, to monitor
the fans.
The PWRD board connection between the OMP board and power subrack
implements the PWRD monitoring.
Different sensor and power subrack connections implement the monitoring of
external environment.
Dual Cabinet
1. For dual cabinet, the connections between ZXG10 iBSC cabinets contain:

a. Clock Distribution
4-37

Figure 4-31 shows the wiring of clock distribution & extraction in the iBSC
dual-cabinet.
Figure 4-31 Wiring of Clock Extraction Distribution In the iBSC Dual-Cabinet

for Resource Shelf
The shelf in the iBSC system requires the system clock. The clock extraction and
distribution modes are described as follows:
l Clock extraction for reference clock base
CLKG board.
The CLKG board also can input the BITS clock base.
Connect UIMU for different resource shelves or UIMC for packet switching
shelves from rear boards RCKG1 & RCKG2 for the CLKG board through the
clock cable and distribute to different slots in local shelf by UIMU/UIMC.
Figure 4-32 shows the Ethernet wiring at control plane in the iBSC dual-cabinet.
4-38

Chapter 4 Shelf
Figure 4-32 Ethernet Connection at Control Plane in the iBSC Dual-Cabinet

for Resource Shelf
The Ethernet interconnection at control plane in the iBSC dual-cabinet is described
as follows.
l Connect the UIMC or UIMU board for all shelves other than the control shelf
in cabinet 1 to the CHUB board through the cable.
l The UIMC board for the control shelf in cabinet 1 directly connects the CHUB
board through the printed lines on the backplane.

Figure 4-33 shows the interconnection at user plane for the iBSC dual-cabinet.
Figure 4-33 Wiring at User Plane in the iBSC Dual-Cabinet for Resource Shelf
The user plane interconnects in the iBSC system, the user plane in a resource
shelf interconnects through backplane, the different resource shelves interconnect
mutually through the GLI and PSN boards among the different resource shelves.
4-39

That is, connect the UIMU and GLI boards for all resource shelves through the
fibers.
Figure 4-34 shows the connection of monitoring cables in the iBSC dual cabinet.
Figure 4-34 Wiring of Monitoring Cables in the iBSC Dual-Cabinet for Resource
Shelf
the fan subrack.
The OMP board in cabinet 1 connects the PWRD board in this cabinet. The PWRD
board in cabinet 2 connects that in cabinet 1, to monitor the PWRD in cabinet 1 &
2.
Different sensor and power subrack connections in cabinet 1 implement the
monitoring of external environment.
4.4.2 Internal Connections (Using BGSN)

Single Cabinet
1. For single cabinet, the cables in the ZXG10 iBSC system contains:
a. Clock extraction distribution
4-40

Chapter 4 Shelf
Figure 4-35 shows the wiring of clock extraction distribution in an iBSC cabinet.

GB Resource Shelf
Note:
In Figure 4-35, CLKG (ICM) can be changed to ICM. CLKG (ICM) and ICM can
provide the clock. Other paragraphs in this section is same as this, no more
explanation later. DTB, STDB, SDTB2, and SPB2 can be CLKG (ICM)/ICM
extraction clock signal. This figure only takes DTB as an example.
There are the following modes for clock extraction distribution.
l Clock base for clock extraction reference
CLKG (ICM)/ICM board.
The CLKG (ICM)/ICM board also can input the BITS clock base or get the
clock base from the GPS module.
4-41

Connect the GUIM/UIMC board in different shelves from rear boards RCKG1
& RCKG2 for the CLKG(ICM)/ICM board through the clock cable and
distribute to different slots in local shelf by GUIM/UIMC.
Figure 4-36 shows the Ethernet interconnection at control plane.
Figure 4-36 Ethernet Connection at Control Plane in an iBSC Cabinet for GB

Resource Shelf
The Ethernet interconnection at control plane for the iBSC system can be
implemented by the CHUB board. The Ethernet interconnection mode at control
plane is described as follows.
l Connect CHUB to GUIM for GB resource shelf and UIMC for packet switching
shelf through the cables.
l The UIMC board for the control shelf directly connects the CHUB board
through the printed lines on the backplane.
The connection at user plane for an iBSC cabinet is shown in Figure 4-37.
4-42

Chapter 4 Shelf
Figure 4-37 Wiring at User Plane in an iBSC Cabinet for GB Resource Shelf
The user plane interconnects in the iBSC system, the user plane in a GB
resource shelf interconnects through backplane, the user plane among different
GB resource shelves interconnect through the GLI and PSN boards in the packet
switching shelf. That is, connect the GUIM and GLI boards for GB all resource
shelves through the fibers.
Figure 4-38 shows the connection of monitoring cable in an iBSC cabinet.
4-43

Figure 4-38 Wiring of Monitoring Cables in an iBSC Cabinet for GB Resource

Shelf
the fans.
The PWRD board connection between the OMP board and power subrack
implements the PWRD monitoring.
Different sensor and power subrack connections implement the monitoring of
external environment.
Dual Cabinet
1. For dual cabinet, the connections between ZXG10 iBSC cabinets contain:
a. Clock Distribution
4-44

Chapter 4 Shelf
Figure 4-39 shows the wiring of clock distribution and extraction in the iBSC
dual-cabinet.
Figure 4-39 Wiring of Clock Extraction Distribution In the iBSC Dual-Cabinet

for GB Resource Shelf
The shelf in the iBSC system requires the system clock. The clock extraction &
distribution modes are described as follows.
l Clock base for clock extraction reference
CLKG (ICM)/ICM board.
The CLKG (ICM)/ICM board also can input the BITS clock base or get the
clock base from the GPS module on the ICM board.
Connect GUIM for different GB resource shelves or UIMC for packet switching
shelves from rear boards RCKG1 & RCKG2 for the CLKG(ICM)/ICM board
through the clock cable and distribute to different slots in local shelf by
GUIM/UIMC.
Figure 4-40 shows the Ethernet wiring at control plane in the iBSC dual-cabinet.
4-45

Figure 4-40 Ethernet Connection at Control Plane in the iBSC Dual-Cabinet

for GB Resource Shelf
The Ethernet interconnection at control plane in the iBSC dual-cabinet is described
as follows:
l Connect the GUIM or UIMU board for all shelves other than the control shelf
in cabinet 1 to the CHUB board through the cables.
l The UIMC board for the control shelf in cabinet 1 directly connects the CHUB
board through the printed lines on the backplane.
Figure 4-41 shows the interconnection at user plane for the iBSC dual-cabinet.
Figure 4-41 Wiring at User Plane in the iBSC Dual-Cabinet for GB Resource
Shelf
The user plane interconnects in the iBSC system, the user plane in a GB resource
shelf interconnects through backplane, the different GB resource shelves
interconnect mutually through the GLI and PSN boards among the different GB
4-46

Chapter 4 Shelf
resource shelves. That is, connect the GUIM and GLI boards for all GB resource
shelves through the fibers.
Figure 4-42 shows the connection of monitoring cables in the iBSC dual cabinet.
Figure 4-42 Wiring of Monitoring Cables in the iBSC Dual-Cabinet for GB

Resource Shelf
the fan subrack.
The OMP board in cabinet 1 connects the PWRD board in this cabinet. The PWRD
board in cabinet 2 connects that in cabinet 1, to monitor the PWRD in cabinet 1
and 2.
Different sensor and power subrack connections in cabinet 1 implement the
monitoring of external environment.
4-47

4-48

Chapter 5
Board
Table of Contents
Board Description.......................................................................................................5-1
BSC IP Interface Board (BIPI) ....................................................................................5-2
Control Plane HUB (CHUB)........................................................................................5-6
Clock Generator Board CLKG (CLKG) .....................................................................5-11
Clock Generator Board CLKG (ICM) ........................................................................5-19
Control Main Processing (CMP) Board .....................................................................5-27
Digital Trunk Board (DTB) ........................................................................................5-31
E1 IP Interface Board (EIPI) .....................................................................................5-37
GB Line Interface (GLI) Board ..................................................................................5-40
GB Line Interface (GLI4) Board ................................................................................5-44
Gigabit Ethernet Network Interface (GIPI) Board ......................................................5-47
Gigabit Universal Interface Module (GUIM) ..............................................................5-51
Gigabit Universal Interface Module (GUIM2) ............................................................5-56
GSM Universal Processing (GUP) Board .................................................................5-60
GSM Universal Processing (GUP2) Board 2.............................................................5-64
Integrated Clock Module (ICM).................................................................................5-68
Operation and Maintenance Processing (OMP) Board .............................................5-77
Packet Switching Network (PSN) Board ...................................................................5-80
Power Distribution (PWRD) Board............................................................................5-83
Server Board (SBCX) ...............................................................................................5-86
SONET Digital Trunk Board (SDTB) .........................................................................5-91
SONET Digital Trunk Board2 (SDTB2) .....................................................................5-95
Signaling Processing Board (SPB) ...........................................................................5-99
Signaling Processing Board 2 (SPB2) ....................................................................5-105
Universal Interface Module for Control Plane (UIMC) .............................................5-109
Universal Interface Module for User Plane (UIMU) ................................................. 5-113
User Plane Processing Board (UPPB).................................................................... 5-118
5.1 Board Description

In the iBSC system, the board refers to the integrated circuit board that can implement a
specific function.
According to the hardware assembly relation, boards can be classified as front board and
rear board.
The front board is inserted in the shelf slot, with a front panel. Indicators on the front panel
indicate the board status. Rear board consists of the external interfaces and debugging
5-1

interfaces. These interfaces are used to interconnect shelves of same cabinet or different
cabinets. The rear board and the front board work together. For some active/standby front
board, it is necessary to configure two kinds of rear boards.
Front board and rear board form a complete metal shield inside the shelf, reducing the
external electromagnetic radiation of the system and enhancing the anti-interference
capability.
Figure 5-1 shows the board assembly relation.
Figure 5-1 Board Assembly
1. Panel of front board 3. Backplane 5. Rear board

2. Front board 4. Slot 6. Panel of rear board
5.2 BSC IP Interface Board (BIPI)

5.2.1 BIPI Functions
The IP interface between ZXG10 iBSC and BTS, SGSN, MSC/MGW is implemented by
BSC IP interface board (BIPI). Each BIPI provides four external interfaces.
According to functions, the BIPI board is divided into the following three types of functional
boards: Abis Interface IP Interface Board (IPBB), A-Interface IP Interface Board (IPAB),
and Gb Interface IP Interface Board (IPGB).
5.2.2 BIPI Principle

Figure 5-2 shows the working principle of the BIPI board.
5-2

Chapter 5 Board
Figure 5-2 Principle of BIPI Board
1. The BIPI board consists of the following three units:

a. Service processing unit
It processes related protocol and implements the isolation of user plane and control
plane.
b. Logic unit
It implements all logical processing function of the board.
c. Interface unit
It provides four FE interfaces and RS232 serial interface for debugging.
2. Board data flow direction
Data accesses the interface unit and is sent to service processing unit and separated
to be the data at user plane and control plane. The data at user plane is sent to GUP
or UPPB for processing via switching network at user plane and the data at control
plane is sent to CMP for processing via switching network at control plane.
5.2.3 BIPI Panel

RMNIC is the rear board of BIPI. Figure 5-3 shows the BIPI board.
5-3

Figure 5-3 BIPI Board
1. BIPI panel for front board 2. RMNIC panel for rear board
5.2.4 BIPI Interfaces

RMNIC provides four external 100 Mbps Ethernet interfaces.
Table 5-1 shows the relevant interfaces on the BIPI board.
5-4

Chapter 5 Board
Table 5-1 Relevant Interfaces on BIPI Board
Location Interface Direction Description
FE1 Bidirectional Connected to BTS,

SGSN, and MSC/MGW
FE2 Bidirectional
100baseT electric port,
FE3 Bidirectional
maximum transmission
FE4 Bidirectional distance: 100 m
Ethernet network in-

terface for debugging;
connected to the debug
DEBUG-FE Bidirectional machine (unused).
3 * 232 serial port, con-

nected to the external
PrPMC232 Bidirectional PC (unused).
RMNIC panel for rear
board 8KOUT/ARM232 Output/Bidirectional Debugging interface
5.2.5 BIPI Buttons

Table 5-2 shows the panel buttons of the BIPI board.
Table 5-2 BIPI Panel Buttons
Name Description
RST Reset switch
EXCH Active/standby switchover switch
5.2.6 BIPI Indicators

There are eight indicators on the panel of the BIPI board. Table 5-3 describes its specific
meanings.
Table 5-3 BIPI Panel Indicators
Refer to "Description of combined

RUN Green Running indicator indicator status"

ALM Red Alarm indicator indicator status"
5-5

ON: Indicates that the micro

switch is turned on; the board
is not inserted to the correct
position, software version is not
downloaded.
Flashing at 5 Hz: Indicates the
micro switch alarm; during the
boards running, the micro switch
is turned on and has alarm.
Flashing at 1 Hz: Indicates that
the board can be extracted;
during the boards running, the
micro switch is turned on, the
board, which is standby or
does not use resource, can be
extracted.
Board extraction Indica- OFF: Indicates that the micro
ENUM Yellow tor switch is proper.
ON: Indicates the board is active

OFF: Indicates the board is
ACT Green Active/standby indicator standby
ON: indicates the connection

of FE1~FE4 at 100M access
network port.
FE1~FE4 indicators at OFF: indicates the disconnection
100M access network of FE1~FE4 at 100M access
LINK1~4 Green port. network port.
5.3 Control Plane HUB (CHUB)

5.3.1 CHUB Functions
CHUB and UIMC/UIMU/GUIM are used to exchange and converge the data flow at internal
control plane.
5.3.2 CHUB Principle

Figure 5-4 shows the working principle of the CHUB board.
5-6

Chapter 5 Board
Figure 5-4 Principle of CHUB Board
1. The CHUB board consists of the following three units:

a. CPU unit
It connects the logic unit and Ethernet switching unit via the control bus, to
configure the switching chip set.
b. Logic unit
It implements all logical processing functions of the board.
c. Ethernet switching unit
It performs Ethernet switching, implementing the gathering on the control plane.
a. The data of the control plane from all shelves is sent to Ethernet switching unit on
CHUB.
b. The data is sent to UIMC on the control shelf via Interface GE, and then is
distributed to RCB for processing and vice versa.
5.3.3 CHUB Panel

RCHB1 and RCHB2 are the proper rear boards for CHUB board. Both RCHB1 and RCHB2
provide the external interface for CHUB board.
Figure 5-5 shows the the CHUB board.
5-7

Figure 5-5 CHUB Board
1. CHUB panel for front board 3. RCHB2 panel for rear 5. RCHB2 panel for rear
2. RCHB1 panel for rear board (version 040501) board (version 040502)
board (version 040501) 4. RCHB1 panel for rear
board (version 040502)
5.3.4 CHUB Interfaces

The CHUB board provides 46 external 100 Mbps Ethernet interfaces and one Gigabit
interface.
Table 5-4 shows the relevant interfaces on the CHUB board.
5-8

Chapter 5 Board
Table 5-4 Relevant Interfaces on CHUB Board
Location Interface Direct. Description
FE1-8 Bi.
FE9-16 Bi.
Connect the port at control plane
FE17-24 Bi. for UIM.
RCHB1 panel for rear Debugging interface/serial port in

board (version 040501) DEBUG-FE/232 Bi. CPU system
FE25-32 Bi. Connect the port at control plane

for UIM.
FE33-40 Bi.
FE43, FE44, FE45, and FE46 are
FE41-46 Bi. used for TRUNK (unused).

Odd FE1-15 Bi. Connect the port at control plane

for UIM.
Odd FE17-31 Bi.
Odd FE43 and Odd FE45 are
Odd FE33-45 Bi. used for TRUNK (unused).

Even FE2-16 Bi. Connect the port at control plane

for UIM.
Even FE18-32 Bi.
Even FE44 and Even FE46 are
Even FE34-46 Bi. used for TRUNK (unused).

Note:
The rear board RCHB1 (version 040501) works with the rear board RCHB2 (version
040501), while the rear board RCHB1 (version 040502) works with the rear board RCHB2
(version 040502).
The rear board (version 040501) cannot be used with the rear board (version 040502).
5.3.5 CHUM Buttons

Table 5-5 shows the relevant buttons on CHUB board.
5-9

Table 5-5 CHUB Panel Buttons
Name Description
RST Reset switch
5.3.6 CHUB Indicators

There are 50 indicators on the panel of the CHUB board, as shown in Table 5-6.
Table 5-6 CHUB Panel Indicators
Refer to "Description of combined indicator

RUN Green Running indicator status"

ALM Red Alarm indicator status"
Active/standby indi- ON: Indicates the board is active

ACT Green cator OFF: Indicates the board is standby
ON: Indicates that the micro switch is turned

on; the board is not inserted to the correct
position, software version is not downloaded.
Flashing at 5 Hz: Indicates the micro switch
alarm; during the boards running, the micro
switch is turned on and has alarm.
Flashing at 1 Hz: Indicates that the board
can be extracted; during the boards running,
the micro switch is turned on, the board,
which is standby or does not use resource,
can be extracted.
Board extraction In- OFF: Indicates that the micro switch is
ENUM Yellow dicator proper.
Status indicator for ON: indicates that related cascading 100M

46-channel cascad- interface is connected at control plane.
ing network interface OFF: Related cascading 100M interface is
L1-L46 Green at control plane. disconnected at control plane.
5-10

Chapter 5 Board
5.4 Clock Generator Board CLKG (CLKG)

5.4.1 CLKG (CLKG) Functions
For iBSC, there are three kinds of boards that can provide the clock for the system: CLKG
(CLKG), CLKG (ICM), and ICM.
CLKG (CLKG) provides the following functions:
l Provides system clock and external synchronization. It extracts clock reference
through A-interface and gives multiple timing reference signals to the interface units.
l Supports background or manual selection of reference sources, including BITS,
network (8 kHz), GPS, and local (level 2 or level 3). Manual switchover can be
screened by software.
l Uses loose-coupling phase-locked system, working in four modes: CATCH, TRACE,
HOLD, and FREE.
l Outputs level-3 clock.
l Performs clock loss alarm and deterioration judgment for input reference.
l Supports active/standby switchover.
5.4.2 CLKG (CLKG) Principle

Figure 5-6 shows the working principle of CLKG (CLKG) board.
Figure 5-6 Principle of CLKG (CLKG) board
1. The CLKG (CLKG) board consists of the following five units:
a. Main control unit

It manages the board, communicates with the system control unit, implements the
core clock control algorithm, outputs the clock signals, and selects the reference
according to the data that the phase detection and phase locking unit provides.
b. Reference selection unit

It selects the suitable reference clock from several input clock under the
control of the main control unit. The clock reference can be from 8 KHz frame
5-11

synchronization signal of DTB or SDTB clock reference, 2 MHz / 2 Mbits of

Building Integrated Timing System (BITS).
c. Voltage controlled oscillator unit
The constant temperature crystal oscillator that meets level-3 clock standard
provides the clock source with high precision.
d. Phase detection and phase lock unit
It compares the adjustment clock signal and input reference phase, and provides
the quantized data for the main control unit, to control the voltage controlled
oscillator unit. The phase lock system uses the loose coupler phase lock principle.
e. Active/Standby changeover unit
It implements the active/standby changeover (the impact of the switching on the
clock shall be within the allowed range). The active/standby CLKG (CLKG) is
locked in the same reference, for the smooth switchover.
a. Select one channel of input reference clock to lock the phase and output 16 M
and frame header signals that meets the requirements of scheduling. After being
balanced- driven, the data is distributed to UIMU.
b. Perform the pulse expansion on the received PP2S and 16 CHIP signal, and then
distribute the new PP2S to shelves.
5.4.3 CLKG (CLKG) Panel

The rear board of CLKG (CLKG) is RCKG1 and RCKG2. Figure 5-7 shows the CLKG
(CLKG) board.
Figure 5-7 CLKG (CLKG) Board
1. CLKG (CLKG) Panel for 2. Layout of CLKG (CLKG) for 3. RCKG1 panel for rear
front board front board board (version 040503)
5-12

Chapter 5 Board
4. RCKG2 panel for rear 5. RCKG1 panel for rear 6. RCKG2 panel for rear
board (version 040502) board (version 071200) board (version 071200)
5.4.4 CLKG (CLKG) Interfaces

Table 5-7 shows the relevant interfaces on CLKG (CLKG) board.
Table 5-7 Relevant interfaces on CLKG (CLKG) board
CLKOUT Output 6 * clock output, connected to different resource

shelves/GB resource shelves and control
shelves.
One CLKOUT outputs 1-to-6 cable. One shelf
has two UIM/GUIM boards, and uses a group of
active/standby clocks (a group of active/standby
clocks include two 16 M, two 8 K, and two
PP2S signals). Therefore, one CLKOUT can
connect three shelves, that is, three groups of
clock outputs. RCKG1 has two CLKOUTs and
provides six clock outputs, that is, connecting
CLKOUT Output six shelves.
2 x 8 K reference input. If SDTB/SDTB2 pro-

vides the clock reference, this port is connected
with 8KOUT/DEBUG-232 on RGIM1. If DTB
provides the clock reference, this port is con-
nected with 8KOUT/DEBUG-232 on RDTB. If
SPB/SPB2 provides the clock reference, this
port is connected with 8KOUT/CPU1-RS232 on
8 KIN1 Input RSPB.
2 x 8 K reference input, connecting GPS clock

reference source. To guarantee the reference
redundancy, 8KIN2 can input link 8 K clock ref-
8 KIN2 Input erence as the standby clock.
1 x 2 Mbps and 2 MHz input, connected to

RCKG1 panel for external BITS clock reference source.
rear board (version 75 ohms coaxial cable or 120 ohms twist pairs,
040503) 2 Mbps/2 MHz Input max transmission distance 250 m
5-13

CLKOUT Output Nine clock output interfaces connect different

resource shelves/GB resource shelves and
CLKOUT Output
control shelves.
RCKG2 has three CLKOUTs and provides nine
clock outputs, that is, connecting nine shelves.
RCKG1 and RCKG2 working together can
connect 15 shelves. It is the max number of
CLKOUT Output clock connections currently for iBSC.
RCKG2 panel for
rear board (version 1 x GPS reference input, connecting the external
040502) PP2S/16CHIP Input GPS clock reference source.
CLKOUT Output 6 clock output interfaces connect different

control shelves.
has two UIM/GUIM boards and uses two clock
sockets, so a CLKOUT can connect three
shelves, that is, three clock outputs. RCKG1
has two CLKOUTs and provides six clock
outputs, that is, connecting six shelves.
The output of RCKG1 and RCKG2 with the
same number is a group of active/standby
clock, connecting the rear board of UIM/GUIM
CLKOUT Output board in the active/standby slot.
8 K reference input. If SDTB/SDTB2 provides

the clock reference, this port is connected
8 KIN1 Input RSPB.
The system debugging serial port, connecting

RS232 Bidirectional the debugger.
1 x 2 Mbps and 2 MHz reference clock input,

connected to external BITS clock reference
RCKG1 panel for source.
071200) BITS REF Input max transmission distance 250 m
5-14

Chapter 5 Board
CLKOUT Output Six clock output interfaces connect different

control shelves.
has two UIM/GUIM boards and uses two clock
sockets, so a CLKOUT can connect three
shelves, that is, three clock outputs. RCKG1
outputs, that is, connecting six shelves.
clock, connecting the rear board of UIM/GUIM
CLKOUT Output board in the active/standby slot.
8 K reference input. If SDTB/SDTB2 provides

the clock reference, this port is connected
8 KIN2 Input RSPB.
The system debugging serial port, connecting

RS232 Bidirectional the debugger.
1 x 2 Mbps and 2 MHz reference clock input,

connected to external BITS clock reference
RCKG2 panel for source.
071200) BITS REF Input max transmission distance 250 m
Note:
The rear board RCKG1 (version 040503) is used with the rear board RCKG2 (version
040502). Two sets of 8K references are introduced from RCKG1. The rear board RCKG1
(version 071200) is used with the rear board RCKG2 (version 071200). Each rear board
connects a set of 8K clock reference and a set of BITS clock reference.
The rear board (version 0405xx) cannot be used with the rear board (version 071200).
5.4.5 CLKG (CLKG) Buttons

Table 5-8 shows the relevant buttons on CLKG (CLKG) panel.
5-15

Table 5-8 CLKG (CLKG) Panel Buttons
Name Description
RST Reset switch
Button for enabling manual reference selection

After MANEN is pressed, the manual clock reference selection is
MANEN enabled, the MANI indicator is ON.
Button for manually selecting the reference

Before selecting the clock reference, press MANEN.
After MANI is ON, press this button to select the clock reference
(corresponding indicators such as 8K1, 8K2, 8K3, or NULL will
MANSL be ON).
5.4.6 CLKG (CLKG) Indicators

There are 18 indicators on the CLKG (CLKG) panel. Table 5-9 describes its specific
meanings.
Table 5-9 CLKG (CLKG) Panel Indicators
Running indica-
RUN Green tor Refer to "Description of combined indicator status"
ALM Red Alarm indicator Refer to "Description of combined indicator status"
ON: Indicates that the micro switch is turned on;

the board is not inserted to the correct position,
software version is not downloaded.
Flashing at 1 Hz: Indicates that the board can be
extracted; during the boards running, the micro
switch is turned on, the board, which is standby
Board extraction or does not use resource, can be extracted.
ENUM Yellow Indicator OFF: Indicates that the micro switch is proper.
Active/standby ON: Indicates the board is active

ACT Green indicator OFF: Indicates the board is standby
ON: Indicates that the board is currently in catch

status, that is, a reference has been found but has
CATCH: Green Catch indicator not been locked onto
5-16

Chapter 5 Board
ON: Indicates that the board is currently in trace

status, that is, a reference has been found and
TRACE: Green Trace indicator locked onto
ON: Indicates that the reference has been lost af-

KEEP Green Hold indicator ter being locked onto
ON: Indicates that the board has no reference, and

FREE Green Free indicator is in free running status
Indicates the clock reference CLKG (ICM) board

selects
ON: Indicates CLKG (ICM) selects the first 2 Mbps
Reference indi- clock reference provided by BITS equipment,
2 Mbps1 Green cator which is transmitted in HDB3 coding form

selects
ON: Indicates CLKG (ICM) selects the second
2 Mbps clock reference provided by BITS
Reference indi- equipment, which is transmitted in HDB3 coding
2 Mbps2 Green cator form

selects
ON: Indicates CLKG (ICM) selects the first 2 MHz
Reference indi- clock reference provided by BITS equipment,
2 MHz1 Green cator which is transmitted in TTL differential form

selects
ON: Indicates that the selected reference is the
second 2 MHz clock reference transmitted in the
Reference indi- form of TTL difference, which is provided by BITS
2 MHz2 Green cator equipment.

selects
Reference indi- line 8K reference provided by board such as DTB
8 K1 Green cator and APBE.

selects
Reference indi- ON: Indicates that the selected reference is the
8 K2 Green cator 8K clock reference provided by GPS board.
5-17


selects
Reference indi- ON: Indicates that the selected reference is the
8 K3 Green cator 8K clock reference provided by UIMU or UIMC.

selects
Reference indi- ON: Indicates that no external reference is
NULL Green cator available and system is in free oscillating status
Reference deteri- ON: Indicates the selected reference has

QUTD Red oration indicator deteriorated
ON: Indicates that the reference can be selected

manually
Manual selection OFF: Indicates that the reference can not be
MANI Green indicator selected manually
5.4.7 CLKG (CLKG) Jumpers

Table 5-10 shows the description of CLKG (CLKG) jumpers.
Table 5-10 CLKG (CLKG) Jumpers
Name Purpose Jumper Description Default Position
It indicates that matching

impedance is 75 ohms when pins
X40 1 and 2 are connected.
X41 Selection of the first 2 It indicates that matching
X44 Mbps and 2 MHz matching impedance is 125 ohms when Pin 1 connects pin
X45 impedance of BITS pins 2 and 3 are connected. 2 in short circuit.
It indicates that matching

impedance is 75 ohms when pins
X42 1 and 2 are connected.
X43 Selection of the second 2 It indicates that matching
X46 Mbps and 2 MHz matching impedance is 125 ohms when Pin 1 connects pin
X47 impedance of BITS pins 2 and 3 are connected. 2 in short circuit.
used in debug mode;

X48 disconnected in normal
X50 operation mode. - Disconnected
Two protective grounding

jumpers for input coaxial The shell of coaxial cable connects
X53 cables of 2 Mbps and 2 the protective ground while 1 is in Pin 1 connects pin
X56 MHz clocks. short circuit with 2. 2 in short circuit.
5-18

Chapter 5 Board
Name Purpose Jumper Description Default Position
Pins 3-5 and 4-6 shall be

connected in short circuit
during debugging when data is
downloaded through serial port in
the computer.
In normal case, it communicates
with the background via 485 while Pin 1-3 and 2-4
Jumper of RS485 connec- pin 1-3 and 2-4 are connected in connect in short cir-
X60 tion relation short circuit. cuit.
5.5 Clock Generator Board CLKG (ICM)

5.5.1 CLKG (ICM) Functions
CLKG (ICM) provides the following functions:
HOLD, and FREE.
5.5.2 CLKG (ICM) Principle

Figure 5-8 shows the working principle of CLKG (ICM) board.
5-19

Figure 5-8 Principle of CLKG (ICM) Board
1. The CLKG (ICM) board consists of the following five units:

It selects the suitable reference clock from several input clock under the
control of the main control unit. The clock reference can be from 8 KHz frame
synchronization signal of DTB or SDTB/SDTB2 clock reference, 2 MHz / 2 Mbits
of Building Integrated Timing System (BITS).
It compares the adjustment clock signal and input reference phase and provides
the quantized data for the main control unit, to control the voltage controlled
It implements the active/standby changeover (the impact of the switching on the

clock shall be within the allowed range). The active/standby CLKG (ICM) is locked
in the same reference, for the smooth switchover.
balanced- driven, the data is distributed to UIMU/GUIM.
5-20

Chapter 5 Board
5.5.3 CLKG (ICM) Panel

The rear board of CLKG (ICM) is RCKG1 and RCKG2. Figure 5-9 shows the CLKG (ICM)
board.
Figure 5-9 CLKG (ICM) Board
1. CLKG (ICM) Panel for front 3. RCKG1 panel for rear 5. RCKG1 panel for rear
board board (version 040503) board (version 071200)
2. Layout of CLKG (ICM) for 4. RCKG2 panel for rear 6. RCKG2 panel for rear
front board board (version 040502) board (version 071200)
5.5.4 CLKG (ICM) Interfaces

Table 5-11 shows the relevant interfaces on CLKG (ICM) board.
Table 5-11 Relevant interfaces on CLKG (ICM) board
CLKOUT Output 6 * clock output, connected to different

control shelves.
One CLKOUT outputs 1-to-6 cable. One
shelf has two UIM/GUIM boards, and uses
a group of active/standby clocks (a group of
active/standby clocks include two 16 M, two
8 K, and two PP2S signals). Therefore, one
CLKOUT can connect three shelves, that
is, three groups of clock outputs. RCKG1
CLKOUT Output outputs, that is, connecting six shelves.
RCKG1 panel for rear 2 x 8 K reference input. If SDTB/SDTB2

board (version 040503) 8 KIN1 Input provides the clock reference, this port
5-21

is connected with 8KOUT/DEBUG-

232 on RGIM1. If DTB provides the
clock reference, this port is connected
with 8KOUT/DEBUG-232 on RDTB.
If SPB/SPB2 provides the clock ref-
erence, this port is connected with
8KOUT/CPU1-RS232 on RSPB.
2 x 8 K reference input, connecting GPS

clock reference source. To guarantee the
reference redundancy, 8KIN2 can input link
8 KIN2 Input 8 K clock reference as the standby clock.
1 x 2 Mbps and 2 MHz input, connected to

external BITS clock reference source.
75 ohms coaxial cable or 120 ohms twist
2 Mbps/2 MHz Input pairs, max transmission distance 250 m

CLKOUT Output
control shelves.
RCKG2 has three CLKOUTs and provides
nine clock outputs, that is, connecting nine
shelves.
RCKG1 and RCKG2 working together can
connect 15 shelves. It is the max number
CLKOUT Output of clock connections currently for iBSC.
RCKG2 panel for rear 1 x GPS reference input, connecting the ex-
board (version 040502) PP2S/16CHIP Input ternal GPS clock reference source.

control shelves.
shelf has two UIM/GUIM boards and
uses two clock sockets, so a CLKOUT
can connect three shelves, that is, three
clock outputs. RCKG1 has two CLKOUTs
and provides six clock outputs, that is,
connecting six shelves.
RCKG1 panel for rear clock, connecting the rear board of
board (version 071200) CLKOUT Output UIM/GUIM board in the active/standby slot.
5-22

Chapter 5 Board
8 K reference input. If SDTB/SDTB2

provides the clock reference, this port
8 KIN1 Input 8KOUT/CPU1-RS232 on RSPB.
Bidirec- The system debugging serial port, connect-

RS232 tional ing the debugger.
1 x 2 Mbps and 2 MHz reference clock

input, connected to external BITS clock
reference source.
BITS REF Input pairs, max transmission distance 250 m

control shelves.
shelf has two UIM/GUIM boards and
uses two clock sockets, so a CLKOUT
can connect three shelves, that is, three
clock outputs. RCKG1 has two CLKOUTs
and provides six clock outputs, that is,
connecting six shelves.
clock, connecting the rear board of
CLKOUT Output UIM/GUIM board in the active/standby slot.
8 K reference input. If SDTB/SDTB2

provides the clock reference, this port
8 KIN2 Input 8KOUT/CPU1-RS232 on RSPB.
RCKG2 panel for rear Bidirec- The system debugging serial port, connect-
board (version 071200) RS232 tional ing the debugger.
5-23

1 x 2 Mbps and 2 MHz reference clock

input, connected to external BITS clock
reference source.
BITS REF Input pairs, max transmission distance 250 m
Note:
5.5.5 CLKG (ICM) Buttons

Table 5-12 shows the relevant buttons on CLKG (ICM) panel.
Table 5-12 CLKG (ICM) Panel Buttons
Name Description
RST Reset switch

After MANEN is pressed, the manual clock reference selection is
MANEN enabled, the MANI indicator is ON.

(corresponding indicators such as 8K1, 8K2, 8K3, or NULL will be
MANSL ON).
5.5.6 CLKG (ICM) Indicators

There are 19 indicators on the CLKG (ICM) panel. Table 5-13 describes its specific
meanings.
5-24

Chapter 5 Board
Table 5-13 CLKG (ICM) Panel Indicators
RUN green Running indicator Refer to "Description of combined indicator status"

Flashing at 5 Hz: Indicates the micro switch alarm;
during the boards running, the micro switch is turned
on and has alarm.
switch is turned on, the board, which is standby or
Board extraction does not use resource, can be extracted.

ACT green indicator OFF: Indicates the board is standby

selects
Reference indi- clock reference provided by BITS equipment, which
Bps1 green cator is transmitted in HDB3 coding form

selects
ON: Indicates CLKG (ICM) selects the second 2
Reference indi- Mbps clock reference provided by BITS equipment,
Bps2 green cator which is transmitted in HDB3 coding form

selects
Reference indi- clock reference provided by BITS equipment, which
Hz1 green cator is transmitted in TTL differential form

selects
Reference indi- form of TTL difference, which is provided by BITS
Hz2 green cator equipment.
5-25


selects
Reference indi- ON: Indicates that the selected reference is the 8K
8 K1 green cator clock extracted by the line.

selects
Reference indi- ON: Indicates that the clock reference is a 8 kHz
8 K2 green cator clock reference provided by external GPS

selects
8 K3 green cator clock reference sent by UIMU/GUIM or UIMC

selects
8 K4 green cator clock reference provided by the boards GPS

selects
Reference indi- ON: Indicates that no external reference is available
NULL green cator and system is in free oscillating status
Reference deteri- ON: Indicates the selected reference has deterio-

QUTD Red oration indicator rated
ON: Indicates that the board is currently in catch sta-

tus, that is, a reference has been found but has not
CATCH: green Catch indicator been locked onto
ON: Indicates that the board is currently in trace sta-

tus, that is, a reference has been found and locked
TRACE: green Trace indicator onto
ON: Indicates that the reference has been lost after

KEEP green Hold indicator being locked onto

FREE green Free indicator is in free running status

manually
Manual selection OFF: Indicates that the reference can not be
MANI: green indicator selected manually
5-26

Chapter 5 Board
5.5.7 CLKG (ICM) DIP Switches

DIP switches, S1 and S5, on CLKG (ICM) are used to select the matching impedance of
BITS clock line. The default resistance is 75 ohms. Table 5-14 shows the description of
DIP switches.
Table 5-14 CLKG (ICM) DIP Switches
Setting
Mode DIP 1 2 3 4 Default
S1 ON ON ON ON
75 ohms S5 ON ON ON ON
S1 ON ON ON ON
100 ohms S5 OFF OFF OFF OFF
S1 OFF OFF OFF OFF
120 ohms S5 OFF OFF OFF OFF 75 ohms
5.6 Control Main Processing (CMP) Board

5.6.1 CMP Functions
CMP finishes the service and call management at PS/CS domain and the resource
management of BSSAP and BSSGP sub-layers and the system itself.
5.6.2 CMP Principle

Figure 5-10 explains the description of CMP principle.
5-27

Figure 5-10 Principle of CMP Board
The CMP board consists of the following three units:
1. CPU unit
There are two independent CPU units on the board, CPU_A and CPU_B. Each
CPU unit provides FE electrical interface at control plane, the FE electrical interface
for communication of active/standby board, and RS232 and RS485 interfaces for
communication with other units. CPU_A is on the lower part of the board, which
implements the main control function of the board.
2. Logic unit
3. Power management unit
It implements the power management distribution of the board.
5.6.3 CMP Panel

CMP does not need the rear board. Install a blank panel at the corresponding slot. The
hard disk is not equipped for two CMP CPU units. Figure 5-11 shows the CMP board.
5-28

Chapter 5 Board
Figure 5-11 CMP Board
1. Panel for CMP front board 2. CMP Layout
5.6.4 CMP Interfaces

Table 5-15 shows the relevant interfaces on CMP board.
Table 5-15 Relevant interfaces on CMP board
CPU_B USB interface,

USB1 Bidirectional unused
CMP panel for front CPU_A USB interface,

board USB2 Bidirectional unused
5.6.5 CMP Buttons

Table 5-16 shows the panel buttons on the CMP board.
Table 5-16 CMP Panel Buttons
Name Description
RST Reset switch
5-29

Name Description
Active/Standby switchover for CPU_B
Do the switchover for the same CPU system on the adjacent

EXCH1 board.
Active/Standby switchover for CPU_A
Do the switchover for the same CPU system on the adjacent

EXCH2 board.
5.6.6 CMP Indicators

Table 5-17 shows the indicators on CMP board.
Table 5-17 CMP Panel Indicators
Name Color Name Description
CPU_A alarm indica- Refer to "Description of combined indicator

ALM1 Red tor status"
CPU_A RUN indica- Refer to "Description of combined indicator

RUN1 Green tor status"
CPU_A ac-
tive/standby indica- ON: Indicates the board is active
ACT1 Green tor OFF: Indicates the board is standby
ON: Indicates that the micro switch is

turned on; the board is not inserted to the
correct position, software version is not
downloaded.
Flashing at 5 Hz: Indicates the micro
switch alarm; during the boards running,
the micro switch is turned on and has
alarm.
can be extracted; during the boards
running, the micro switch is turned on, the
board, which is standby or does not use
resource, can be extracted.
CPU_A board ex- OFF: Indicates that the micro switch is
ENUM1 Yellow traction indicator proper.
CPU_B alarm indica- Refer to "Description of combined indicator

ALM2 Red tor status"
CPU_B RUN indica- Refer to "Description of combined indicator

RUN2 Green tor status"
5-30

Chapter 5 Board
CPU_B ac-
ACT2 Green tor OFF: Indicates the board is standby

turned on; the board is not inserted to the
correct position, software version is not
downloaded.
switch alarm; during the boards running,
the micro switch is turned on and has
alarm.
can be extracted; during the boards
running, the micro switch is turned on, the
board, which is standby or does not use
resource, can be extracted.
CPU_B board ex- OFF: Indicates that the micro switch is
ENUM2 Yellow traction indicator proper.
5.7 Digital Trunk Board (DTB)

5.7.1 DTB Functions
Ditial trunk board (DTB) provides the following functions:
l Provides 32 E1/T1 physical interfaces.
l Extracts 8 kHz synchronization clock from a line and transfer it through a cable to
CLKG/ICM as a reference clock.
l Supports 120/75 ohms resistance selection, and supports coaxial cable and twisted
pair.
l Supports 100 ohms twisted pair for T1.
5.7.2 DTB Principle

Figure 5-12 shows the working principle of DTB board.
5-31

Figure 5-12 DTB Principle
1. The DTB board comprises of the following five units:

a. Main control unit: It manages the boards and controls the internal connection.
b. Interface unit: It connects the circuit switching unit, provides the E1/T1 and HW
interfaces, and finishes the extraction of line clock.
c. Circuit switching unit: It switches over the circuit HW for the interface unit.
d. Logic processing unit: It implements the inner logic switchover for the board and
the adaptation function.
e. Clock processing unit: It receives the clock sent from backplane and provides it to
the board after frequency division and time scheduling.
E1/T1 data from the line side passes the interface unit processing link layer and is sent
to the circuit switching unit for the switching. And then, via the interface unit, the data
is sent to UIMU/GUIM board, and vice versa.
5.7.3 DTB Panel

The rear board for DTB board is RDTB. Figure 5-13 shows the DTB board.
5-32

Chapter 5 Board
Figure 5-13 DTB Board
1. SDTB Panel of front board 2. Layout of DTB board 3. RDTB Panel for rear board
for front board (version
040501)
There are two versions for DTB: version 040501 and 060201. There is a difference
between version 060201 and 040501. The DTB with version 060201 has the different
positions. Its jumper position is shown in Figure 5-14.
Figure 5-14 Layout of DTB board for front board (version 060201)
5-33

5.7.4 DTB Interfaces

Table 5-18 shows the relevant interfaces on the DTB board.
Table 5-18 Relevant interfaces on DTB board
32 x E1 Interface to connect the external

system
75/120 ohms E1 interface; 100 ohms T1
T1/E1 1-16 interface
T1/E1 17-32 Bidirectional Maximum transmission distance: 250 m
RDTB
Panel for 8KOUT/DEBUG- Leads out 8K reference clock signal and
rear board 232 Bidirectional debugging signal at RS232 serial port
5.7.5 DTB Buttons

Table 5-19 shows the relevant buttons on DTB board.
Table 5-19 DTB Panel Buttons
Name Description
RST Reset switch
5.7.6 DTB Indicators

There are 36 indicators on DTB panel. Table 5-20 explains their meanings.
Table 5-20 DTB Panel Indicators
Running indica-
ON: Indicates that the micro switch is turned on; the

board is not inserted to the correct position, software
version is not downloaded.
during the boards running, the micro switch is turned on
and has alarm.
extracted; during the boards running, the micro switch is
turned on, the board, which is standby or does not use
Board extrac- resource, can be extracted.
ENUM Yellow tion Indicator OFF: Indicates that the micro switch is proper.
5-34

Chapter 5 Board

OFF: indicates unconfigured database at this E1/T1

Always ON: indicates configured database at this E1/T1
but E1/T1 disconnected
Flashing in the frequency of 1Hz (slowly flash):
32 x E1 Indica- indicates configured database at this E1/T1 and E1/T1
L1~ L32 Green tors is connected
5.7.7 DTB DIP Switches and Jumpers

1. Description of Jumpers on DTB Board
a. DTB Jumpers
DTB board (version 040501) has a jumper (X23) for board debugging. The position
of X23 is shown in "DTB Board". X23 shall be disconnected when the board is
working normally.
DTB board (version 060201) has two jumpers (X18 and X19) for board debugging.
The position of X18 and X19 is shown in "DTB Board Layout (Version 060201)".
The board enters debugging mode if any one of X18 and X19 is short circuited.
X18 and X19 shall be disconnected when the board is working normally.
b. RDTB Jumpers
Figure 5-15 shows the RDTB jumpers.
5-35

Figure 5-15 Jumpers on RDTB board
E1 line on RDTB uses the 75 ohms unbalanced coaxial transmission mode by

default. The originating end connects the protective ground through jumpers and
receiving end connects to a capacitor and then protective ground through jumpers.
Specific implementation is selected through jumpers of X9 to X16 on RDTB.
Table 5-21 shows the connection mode of X9 to X16.
Table 5-21 X9-X16 Connection Mode
X9-X16 Connection Mode Description
1-2 Connect E1_TX (N) -R to protective ground (line N)
3-4 Connect E1_RX (N) -R to protective ground (line N)
5-6 Connect E1_TX (N+1) -R to protective ground (line N+1)
7-8 Connect E1_RX (N+1) -R to protective ground (line N+1)
5-36

Chapter 5 Board
Note:
Connection blocks of jumpers X9-X16 on RDTB should be removed if E1 uses 120
ohms PCM balanced transmission mode.
2. Description of DIP Switches

Table 5-22 shows the description of DIP switches on DTB board.
Table 5-22 DIP Switches on DTB Board
Setting Default
DIP Sw. Purpose Mode 1 2 3 4 1 2 3 4
75
ohms ON ON ON ON
S1~S6 The matching
S9 impedance to connect 120 OF- OF- O- O- O- O-
S12 E1 is 75 or 120 ohms ohms F OFF OFF F N N N N
75
Used to indicate the
ohms ON ON ON ON
matching receiving re-
S7 sistance of proper E1 120 OF- OF- O- O- O- O-
S8 chips for CPU. ohms F OFF OFF F N N N N
short
Used to indicate the
haul ON ON ON ON
short/long haul of
S10 proper E1 chips for long OF- OF- O- O- O- O-
S11 CPU. haul F OFF OFF F N N N N
1. Each DIP switch corresponds to one E1 chip. S7 corresponds to E1 chips 1 to 4 (E1 channels 1
to 16). S8 corresponds to E1 chips 5 to 8 (E1 channels 17 to 32). CPU reads this status during
power-on and initiates each E1 chip according to this status.
2. Each DIP switch corresponds to four E1 chips. S10 corresponds to E1 chips 1 to 4 (E1 channels
1 to 16). S11 corresponds to E1 chips 5 to 8 (E1 channels 17 to 32). CPU reads this status
during power-on and initiates each E1 chip according to this status.
5.8 E1 IP Interface Board (EIPI)

5.8.1 EIPI Functions
EIPI provides the IP access based on E1/T1, under the assistance of DTB. EIPI board has
no external interface and rear board. One EIPI board together with two DTB boards can
support up to 64 E1/T1 interfaces.
5-37

5.8.2 EIPI Principle

Figure 5-16 shows the working principle of EIPI board.
Figure 5-16 Principle of EIPI Board
1. The EIPI board consists of the following three units:

plane.
b. Logic unit
c. Interface Unit
EIPI does not provide external interface.
The interface unit accesses HW data, and sends the data to HPS subcard. After
being processed by HDLC protocol, the data is sent to the service processing unit and
separated to be data at user plane and control plane. The data at user plane is sent to
GUP2 for processing via switching network at user plane and the data at control plane
is sent to CMP for processing via switching network at control plane.
5.8.3 EIPI Panel

EIPI board does not have corresponding rear board. Figure 5-17 shows the EIPI board.
5-38

Chapter 5 Board
Figure 5-17 EIPI Board
5.8.4 EIPI Interfaces

EIPI does not provide external interface.
5.8.5 EIPI Buttons

Table 5-23 shows the panel buttons of EIPI board.
Table 5-23 EIPI Panel Buttons
Name Description
RST Reset switch
5-39

5.8.6 EIPI Indicators

There are four indicators on the panel of EIPI board. Table 5-24 gives the specific
meanings.
Table 5-24 EIPI Panel Indicators
Running indi-
RUN Green cator Refer to "Description of combined indicator status"

on and has alarm.
Board extrac- does not use resource, can be extracted.
ENUM Yellow tion indicator OFF: Indicates that the micro switch is proper.

5.9 GB Line Interface (GLI) Board

5.9.1 GLI Functions
GLI board implements functions such as physical layer adaptation, IP packet check,
fragmentation, transfer management, and traffic management. The GLI board can handle
the data with 2.5 Gbps and provide 4+4 GE interfaces to implement the interface among
different resource shelves / GB resource shelves and the external interface function.
5.9.2 GLI Principle

Figure 5-18 shows the working principle of GLI board.
5-40

Chapter 5 Board
Figure 5-18 Principle of GLI Board
1. The GLI board consists of the following five units:

a. Optical interface unit
It provides GE optical interface and supports physical backup.
b. Logic unit

c. Ethernet access unit
It implements GE PHY and MAC functions.
d. Service processing unit
It implement the query, fragmentation, forwarding, and traffic management of
bi-directional IP packet.
e. Queue management unit
It manages the queue bi-directionally.
a. GLI receives the media plane data from the resource shelf/gigabit resource shelf
via the optical port.
b. The data in the direction from GE optical port to the board is sent to the switching
interface after being processed by service processing unit, and then sent to the
PSN switching network board via high speed link.
In the direction from PSN board to GLI, the data is transmitted by corresponding
optical port after being processed and framed by the service processing unit.
5.9.3 GLI Panel

Figure 5-19 shows the GLI board.
5-41

Figure 5-19 GLI Panel
5.9.4 GLI Interfaces

Table 5-25 shows the relevant interfaces on the GLI board.
Table 5-25 Relevant Interfaces on GLI Board
Eight STM-1 optical interfaces on the front

panel connect GUIM for GB resource shelf
or UIMU for resource shelf, used for different
8 pairs of resource shelf service access platform (provide
GLI panel TX-RX Bidirectional four GE optical ports in pair and for backup
5-42

Chapter 5 Board
mutually. For example, SD1 & SD2 are a set of

backup, same as SD3 & SD4, as so on.)
5.9.5 GLI Buttons

Table 5-26 shows the panel buttons of the GLI board.
Table 5-26 GLI Panel Buttons
Name Description
RST Reset switch
5.9.6 GLI Indicators

Table 5-27 shows the indicators on GLI board.
Table 5-27 GLI Panel Indicators
Running indica-

alarm; during the boards running, the micro switch

The LED indica- ON: The logic is proper (OFF if there is logic in
tor at optical in- FPGA, otherwise always ON.)
terface is acti- Flashing: Indicates the system is receiving or
ACT1-8 Green vated. transmitting data after the logic is proper.
5-43

ON: indicates optical interface has received

optical signals.
Optical signal in- OFF: indicates optical interface has not received
SD1-8 Green dicator optical signals.
5.10 GB Line Interface (GLI4) Board

5.10.1 GLI4 Functions
GLI4 board implements functions such as physical layer adaptation, IP packet check,
fragmentation, transfer management, and traffic management. The GLI board can handle
the data with 2.5 Gbps and provide 4+4 GE interfaces to implement the interface among
different resource shelves / GB resource shelves and the external interface function.
5.10.2 GLI4 Principle

Please refer to the "GLI Principle" section of this manual.
5.10.3 GLI4 Panel

Figure 5-20 shows the GLI4 board.
5-44

Chapter 5 Board
Figure 5-20 GLI4 Panel
5.10.4 GLI4 Interfaces

Table 5-28 shows the relevant interfaces on the GLI4 board.
5-45

Table 5-28 Relevant Interfaces on GLI4 Board
Eight STM-1 optical in-

terfaces on the front
panel connect GUIM
for GB resource shelf
GLI4 panel 8 pairs of TX-RX Bidirectional
or UIMU for resource
shelf, used for different
resource shelf service
access platform
5.10.5 GLI4 Buttons

Table 5-29 shows the panel buttons of the GLI4 board.
Table 5-29 GLI4 Panel Buttons
Name Description
RST Reset switch
5.10.6 GLI4 Indicators

Table 5-30 shows the indicators on GLI4 board.
Table 5-30 GLI4 Panel Indicators
Refer to "Description of combined indi-

RUN Green Running indicator
cator status"

ALM Red Alarm indicator
indicator status"

turned on; the board is not inserted to
the correct position, software version
is not downloaded.
Board extraction
ENUM Yellow switch alarm; during the boards
Indicator
running, the micro switch is turned on
and has alarm.
Flashing at 1 Hz: Indicates that the
board can be extracted; during the
boards running, the micro switch is
5-46

Chapter 5 Board
turned on, the board, which is standby

or does not use resource, can be
extracted.
OFF: Indicates that the micro switch is
proper.
Active/standby in- ON: Indicates the board is active

ACT Green
dicator OFF: Indicates the board is standby
ON: The logic is proper (OFF if there is

The LED indicator logic in FPGA, otherwise always ON.)
ACT1-8 Green at optical interface Flashing: Indicates the system is
is activated. receiving or transmitting data after the
logic is proper.
ON: indicates optical interface has

Optical signal indi- received optical signals.
SD1-8 Green
cator OFF: indicates optical interface has not
received optical signals.
5.11 Gigabit Ethernet Network Interface (GIPI) Board

5.11.1 GIPI Functions
The IP interface between ZXG10 iBSC, BTS, SGSN, and MSC/MGW is implemented by
GIPI. Each GIPI provides a GE interface or four FE interfaces.
According to functions, the GIPI board is divided into the following four functional boards:
Abis Interface Gigabit IP Interface Board (IPBB), A-Interface Gigabit IP Interface Board
(IPAB for signal), A-Interface Gigabit IP Interface Board (IPI, for signal and service), and
Gb Interface Gigabit IP Interface Board (IPGB)
5.11.2 GIPI Principle

Figure 5-21 shows the working principle of GIPI board.
5-47

Figure 5-21 Principle of GIPI board
1. The GIPI board consists of the following three units:

plane.
b. Logic unit

c. Interface Unit
It provides a GE interface and Ethernet interface for debugging.
Data accesses the interface unit and is sent to service processing unit and separated
to be the data at user plane and control plane. The data at user plane is sent to GUP2
for processing via switching network at user plane and the data at control plane is sent
to CMP for processing via switching network at control plane.
5.11.3 GIPI Panel

RGER is the rear board of GIPI. Figure 5-22 shows the GIPI board.
5-48

Chapter 5 Board
Figure 5-22 GIPI Board
1. GIPI panel for front board 2. RGER panel for rear board 3. RMNIC panel for rear board
Note:
Usually, GIPI uses RGER as the rear board; when iBSC need connect OMCB or MR, GIPI
uses RMNIC as the rear board.
5.11.4 GIPI Interfaces

The rear board RGER provides one gigabit Ethernet interface for the external network.
Table 5-31 shows the relevant interfaces on GIPI board.
5-49

Table 5-31 Relevant Interfaces on GIPI Board
Gigabit ethernet optical interface, connected to

BTS, SGSN, and MSC/MGW
It cannot be effective with the GE1 interface.
Single-mode optical port, wavelength 1310 nm,
tx optical power -9.5 dBm ~ -3 dBm, rx sensitivity
GIPI Panel for < -20 dBm, max rx optical power -3 dBm,
front board TX-RX Bidirectional transmission distance 10 km, LC connector used
Gigabit Ethernet electric interface, connected to

BTS, SGSN, and MSC/MGW
It cannot be effective with the TX-RX interface.
1000baseT electric port, maximum transmission
GE1 Bidirectional distance: 50 m
GE2 Bidirectional Gigabit Ethernet interface, unused
Ethernet network interface for debugging; con-

DEBUG1-232 Bidirectional nected to the debug machine (unused).
RGER panel Ethernet network interface for debugging; con-

for rear board DEBUG2-232 Bidirectional nected to the debug machine (unused).
When iBSC need connect OMCB or MR, GIPI uses RMNIC as the rear board. For the
interfaces on rear board RMNIC, refer to "Relevant Interfaces on BIPI Board".
5.11.5 GIPI Buttons

Table 5-32 shows the panel buttons of GIPI board.
Table 5-32 GIPI Panel Buttons
Name Description
RST Reset switch
5.11.6 GIPI Indicators

There are six indicators on the panel of GIPI board. Table 5-33 describes its specific
meanings.
Table 5-33 GIPI Panel Indicators
Refer to "Description of combined indicator sta-

RUN Green Running indicator tus"
5-50

Chapter 5 Board
Refer to "Description of combined indicator sta-

ALM Red Alarm indicator tus"

Board extraction In- or does not use resource, can be extracted.
ENUM Yellow dicator OFF: Indicates that the micro switch is proper.

ON: indicates optical interface has received

optical signals.
Optical signal indica- OFF: indicates optical interface has not received
SD Green tor optical signals.
ON: the logic is proper (OFF if there is logic in

The LED indicator FPGA, otherwise always ON.)
at optical interface is Flashing: indicates the system is receiving or
ACT Green activated. transmitting data after the logic is proper.
5.12 Gigabit Universal Interface Module (GUIM)

5.12.1 GUIM Functions
Gigabit Universal Interface Module (GUIM) implements Ethernet level-2 switching at
control-plane/user-plane in the gigabit resource shelf, circuit-domain timeslot multiplexing
switching, and gigabit resource shelf management, and provides external interface for the
gigabit resource shelf.
GUIM provides the clock-driven function in the gigabit resource shelf. Input PP2S, 8 kHz
and 16 MHz signals, distribute the signals to various slots after phase lock and driving,
and provide 16 MHz, 8 kHz and PP2S clocks to the boards in the gigabit resource shelf.
GUIM provides the GB resource shelf management function and the RS-485 management
interface. It also provides the function of board reset and in-position signal collection for
the GB resource shelf.
5-51

5.12.2 GUIM Principle

Figure 5-23 shows the working principle of GUIM board.
Figure 5-23 GUIM Principle
1. The GUIM board consists of the following four units:

a. CPU unit
It connects TS switching unit, logic unit, and Ethernet switching unit via the control
bus. It configures the switching unit and manages the GB resource shelf.
b. Logic unit
c. Timeslot (TS) switching unit
It implements 16 K circuit switching and provides an internal circuit switching net
for the GB resource shelf.
d. Ethernet switching unit
It implements the user-plane/control-plane Ethernet switching function on the GB

resource shelf.
The external data is from boards on the shelf where UIMU locates. It enters Ethernet
switching unit or TS switching unit for switching, and then is sent to the target board
or level-1 switching interface board.
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Chapter 5 Board
5.12.3 GUIM Panel

The rear boards of GUIM are RGUM1 and RGUM2. Figure 5-24 shows the GUIM board.
Figure 5-24 GUIM Board
1. GUIM panel for front board 2. RGUM1 panel for rear 3. RGUM2 panel for rear
board board
5.12.4 GUIM Interfaces

Table 5-34 shows the relevant interfaces on GUIM board.
5-53

Table 5-34 Relevant interfaces on GUIM board
Direc-
Location Interface tion Description
The fiber on front panel connects the GLI board at

GUIM Panel for front 4 pairs of Bidirec- switching unit. Use 4×1 Gbps optical interface at user
board RX-TX tional plane for expansion.
Provides one cascading network port (through the two

Bidirec- rear boards in active and standby slots), connected to
FE1 tional CHUB or UIMC on the control shelf.
Provides external network ports (the two rear boards in

Bidirec- active and standby slots each provides one), and can
FE3 tional be used as DEBUG network port.
Bidirec- Provides external network ports (the two rear boards in

FE5 tional active and standby slots each provides one).
Connected the clock board and transmits 8 Kbps/16

CLKIN Input Mbps/PP2S clock signals.
RGUM1 panel for DEBUG- Bidirec- Debugging serial port for CPU system, connected to
rear board 232 tional the debug machine.
Provides one cascading network port (through the two

rear boards in active and standby slots), connected to
Bidirec- CHUB on the control shelf or UIMC, and can be used
FE2 tional as DEBUG network port.


Connected the clock board and transmits 8 Kbps/16

RGUM2 panel for DEBUG- Bidirec- Debugging serial port for CPU system, connected to
rear board 232 tional the debug machine.
Note:
The FE3, FE4, FE5, and FE6 interfaces on the rear board of GUIM cannot be used for
control plane cascading.
5.12.5 GUIM Buttons

Table 5-35 shows the panel buttons on the GUIM board.
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Chapter 5 Board
Table 5-35 GUIM Panel Buttons
Name Description
RST Reset switch
5.12.6 GUIM Indicators

Table 5-36 shows the indicators on GUIM board.
Table 5-36 GUIM Board Indicators
Running indica-


and has alarm.
extracted; during the boards running, the micro switch is
turned on, the board, which is standby or does not use
Board extraction resource, can be extracted.
Packet domain ON: indicates that GUIM packet domain is active

ACT-P Green indicator OFF: indicates that GUIM packet domain is standby
ON: indicates that the current optical interface is

activated
GE interface 1 OFF: indicates that the current optical interface is not
ACT Green status indicator activated
ON: indicates that the optical module has received the

GE interface 1 optical signal
optical signal in- OFF: indicates that the optical module has not received
SD Green dicator the optical signal
5-55


activated


activated


activated

Circuit domain in- ON: indicates that the GUIM circuit domain is active
ACT-T Green dicator OFF: indicates that the GUIM circuit domain is standby
Status indicator ON: indicates the cascade 100 Mbps interface 1 ~ 6 is

of cascade inter- connected at control plane.
face 1 ~ 6 at con- OFF: indicates the cascade 100 Mbps interface 1 ~ 6 is
L1~ L6 Green trol plane not connected at control plane.
5.13 Gigabit Universal Interface Module (GUIM2)

5.13.1 GUIM2 Functions
Gigabit Universal Interface Module (GUIM2) implements Ethernet level-2 switching at
control-plane/user-plane in the gigabit resource shelf, circuit-domain timeslot multiplexing
switching, and gigabit resource shelf management, and provides external interface for the
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Chapter 5 Board
GUIM2 provides the clock-driven function in the gigabit resource shelf. Input PP2S, 8 kHz
and 16 MHz signals, distribute the signals to various slots after phase lock and driving,
and provide 16 MHz, 8 kHz and PP2S clocks to the boards in the gigabit resource shelf.
GUIM2 provides the GB resource shelf management function and the RS-485
management interface. It also provides the function of board reset and in-position signal
collection for the GB resource shelf.
5.13.2 GUIM2 Principle

Please refer to the "GUIM Principle" section of this manual.
5.13.3 GUIM2 Panel

Figure 5-25 shows the GUIM2 board.
5-57

Figure 5-25 GUIM2 Board
5.13.4 GUIM2 Interfaces

Table 5-37 shows the relevant interfaces on GUIM2 board.
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Chapter 5 Board
Table 5-37 Relevant interfaces on GUIM2 board
connect to GLI/GLI4
boards, or connect to
GUIM2 Panel for front
4 pairs of RX-TX Bidirectional GUIM/GUIM2 boards
board
on other resource
shelves.
5.13.5 GUIM2 Buttons

Table 5-38 shows the panel buttons on the GUIM2 board.
Table 5-38 GUIM2 Panel Buttons
Name Description
RST Reset switch
5.13.6 GUIM2 Indicators

Table 5-39 shows the indicators on GUIM2 board.
Table 5-39 GUIM2 Board Indicators
Running indica-
RUN Green Refer to "Description of combined indicator status"
tor

ACT Green
indicator OFF: Indicates the board is standby

during the boards running, the micro switch is
Board extrac-
ENUM Yellow turned on and has alarm.
tion Indicator
does not use resource, can be extracted.
OFF: Indicates that the micro switch is proper.
5-59

ON: indicates that GUIM2 packet domain is active

Packet domain
ACT-P Green OFF: indicates that GUIM2 packet domain is
indicator
standby
ON: indicates that the GUIM2 circuit domain is

Circuit domain active
ACT-T Green
indicator OFF: indicates that the GUIM2 circuit domain is
standby

GE interface activated
ACT1-4 Green
status indicator OFF: indicates that the current optical interface is
not activated
ON: indicates that the optical module has received

GE interface
the optical signal
SD1-4 Green optical signal
OFF: indicates that the optical module has not
indicator
received the optical signal
Status indicator ON: indicates the cascade 100 Mbps interface 1 ~

of cascade in- 6 is connected at control plane.
L1-6 Green
terface 1 ~ 6 at OFF: indicates the cascade 100 Mbps interface 1 ~
control plane 6 is not connected at control plane.
5.14 GSM Universal Processing (GUP) Board

5.14.1 GUP Functions
According to functions, the GUP board is divided into the following three types of functional
boards: Ater Interface Processing Board (TIPB), Abis Interface Processing Board (BIPB),
and Dual Rate Transcoder Board (DRTB).
The TIPB board realizes TDM/IP conversion at Ater interface. In other words, finding out
20 ms TRAU frames according to channel and making them into IP packet.
The CS service and PS service from BTS are switched to the BIPB board through the
circuit switching network of the UIM board. The 20 ms TRU frames (or PCU frames) are
found out according to channel on BIPB, then the TRU frames (or PCU frames) are made
into IP packet and sent to TCU (or UPU) for processing.
The DRTB board realizes TRAU frame transcoding and rate adaptation and provides
FR/EFR/HR/AMR/TFO functions.
5.14.2 GUP Principle

Figure 5-26 shows the working principle of GUP board.
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Chapter 5 Board
Figure 5-26 Principle of GUP board
1. The GUP board consists of the following six units:

a. CPU unit
It implements the management functions of board, processes the signaling at Abis
interface and provides external FE interface at control plane.
b. Logic unit
c. DSP unit
It includes multiple DSP chips, implementing code transformation, rate adaptation,

and data package conversion.

It implements the Ethernet connection of multiple DSPs and provides external user
plane FE interface.
e. Clock unit
It provides necessary clock signal for each external unit on the board.
f. Circuit switching unit

It connects the serial interface of the DSP with circuit switching unit.
5-61

The uplink data flow direction is the opposite of the downlink data flow direction. The
following takes the uplink data flow for an example.
a. When it is used as BIPB, the TDM data accesses Abis interface, then it is
distributed to DSP unit for processing via circuit switching unit, converted to IP
data packet and sent to the other board via Ethernet switching unit.
b. When it is used as DRTB, the voice data IP package from user plane Ethernet
received by interface unit is distributed to DSP for code transformation and rate
adaptation, converted to PCM code flow and switched to trunk board by UIMU.
c. When it is used as TIPB, the user plane data from UIM board is distributed to DSP
through the Ethernet switching unit, converted to TDM data, and then sent to other
board through the circuit switching unit for processing.
5.14.3 GUP Panel

GUP board does not have corresponding rear board. Figure 5-27 shows the GUP panel.
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Chapter 5 Board
Figure 5-27 GUP Panel
5.14.4 GUP Interfaces

GUP does not provide external interface.
5.14.5 GUP Buttons

Table 5-40 shows the GUP panel buttons.
Table 5-40 GUP Panel Buttons
Name Description
RST Reset switch
5-63

5.14.6 GUP Indicators

There are 4 indicators on the panel of GUP board. Table 5-41 describes its specific
meanings.
Table 5-41 GUP Panel Indicators
Running indica-

turned on and has alarm.

5.15 GSM Universal Processing (GUP2) Board 2

5.15.1 GUP2 Functions
According to functions, the GUP2 board is divided into the following five kinds of functional
boards: Ater Interface Processing Board (TIPB), Abis Interface Processing Board (BIPB),
A-Interface Processing Board (AIPB), User Plane Processing Board (UPPB2), and Dual
Rate Transcoder Board (DRTB).
The TIPB2 board realizes TDM/IP conversion at Ater interface. In other words, finding out
20 ms TRAU frames according to channel and making them into IP packet.
At STM-1 interface or E1 Abis interface, the CS and PS services from BTS are switched
to the BIPB2 board through the circuit switching network of the UIM board or through the
circuit switching network of the GUIM board. The 20 ms TRU frames (or PCU frames) are
found out according to channel on BIPB2, then the TRU frames (or PCU frames) are made
into IP packet and sent to TCU (or UPU) for processing. At IP Abis interface, in addition
to the above functions, the BIPB2 board is also used for RTP protocol processing.
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Chapter 5 Board
The AIPB board is used for RTP protocol processing at A-interface and making data into
IP packet.
The UPPB2 board is used for user plane protocol processing under A/Gb mode, including
BSSGP, PDCP, and GTP_U protocol.
The DRTB board realizes TRAU frame transcoding and rate adaptation, and provides
FR/EFR/HR/AMR/TFO functions.
5.15.2 GUP2 Principle

Figure 5-28 shows the working principle of GUP2 board.
Figure 5-28 Principle of GUP2 board
1. The GUP2 board consists of the following six units:

a. CPU unit
Implements the management functions of board, processes the signaling at Abis
interface and provides external FE interface at control plane.
b. Logic unit
c. DSP unit
Include multiple DSP chips, implementing code transformation, rate adaptation,
and data package conversion.
5-65


Implements the Ethernet connection of multiple DSPs and provides external GE
interface at user plane.
e. Clock unit
Provides necessary clock signal for each internal unit of the board.
f. Circuit switching unit
Connects the serial interface of the DSP with circuit switching unit.
The uplink data flow direction is the opposite of the downlink data flow direction. The
following takes the uplink data flow for an example.
a. When it is used as BIPB2, the TDM data accesses Abis interface, then it is
distributed to DSP unit for processing via circuit switching unit, converted to IP
data packet and sent to other board for processing via Ethernet switching unit.
b. When it is used as DRTB2, the voice data IP package from user plane Ethernet
received by interface unit is distributed to DSP for code transformation and rate
adaptation, converted to PCM code flow and switched to trunk board by GUIM.
c. When it is used as UPPB2, the user plane data from GUIM board accesses the
user plane FE/GE interface, then it is distributed to DSP through the Ethernet
switching unit. DSP performs relevant user plane protocol processing, and then
switches the data to SPB2 board through the user plane GE interface.
5.15.3 GUP2 Panel

GUP2 board does not have corresponding rear board. Figure 5-29 shows the GUP2 panel.
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Chapter 5 Board
Figure 5-29 GUP2 Panel
5.15.4 GUP2 Interfaces

GUP2 does not provide external interface.
5.15.5 GUP2 Buttons

Table 5-42 shows the GUP2 panel buttons.
Table 5-42 GUP2 Panel Buttons
Name Description
RST Reset switch
5-67

5.15.6 GUP2 Indicators

There are 4 indicators on the panel of GUP2 board. Table 5-43 describes its specific
meanings.
Table 5-43 GUP2 Panel Indicators
Running indica-
RUN green tor Refer to "Description of combined indicator status"


5.16 Integrated Clock Module (ICM)

5.16.1 ICM Functions
Functions of ICM are as follows:

l Receives GPS satellite system signals, extracts and generates 1PPS signal
and corresponding navigation message (TOD message), and generates PP2S,
19.6608MHz, and system 8K clock reference required by the system.
l Supports BITS, one line (8 K), and two GPS8K (from the local board and external
GPS) as the reference for local clock.
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Chapter 5 Board

HOLD, and FREE.
In comparison with ICM and CLKG (ICM), add GPS function, which can provide GPS
satellite information for the system and be available for system positioning function, and
also add a source for referential clock.
5.16.2 ICM Principle

Figure 5-30 shows the working principle of ICM board.
Figure 5-30 Principle of ICM Board
1. The ICM board consists of five units:


It selects the suitable reference clock from several input clock under the control
of the master unit. The clock reference can be from 8 KHz frame synchronization
signal of DTB or SDTB2 clock reference, 2 MHz / 2 Mbits of Building Integrated
Timing System (BITS), and GPS signal.
5-69

It compares the adjustment clock signal and input reference phase and provides
the quantized data for the main processing unit, to control the voltage controlled
It implements the active/standby changeover (the compact of the switching on the
clock shall be within the allowed range). The active/standby ICM is locked in the
same reference, for the smooth switchover.
balanced- driven, the data is distributed to GUIM.
c. Extract and generate 1PPS signal for the received GPS signal, take the generate
PP2S, 19.6608MHz, and system 8 K clock reference required by the system, and
distribute them to shelves.
5.16.3 ICM Panel

The rear board of ICM is RCKG1 and RCKG2. Figure 5-31 shows the ICM board.
Figure 5-31 ICM board
1. ICM panel 3. RCKG1 panel for rear 5. RCKG1 panel for rear
2. Layout of ICM for front board (version 040503) board (version 071200)
board 4. RCKG2 panel for rear 6. RCKG2 panel for rear
board (version 040502) board (version 071200)
5.16.4 ICM Interfaces

Table 5-44 shows the relevant interfaces on ICM board.
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Chapter 5 Board
Table 5-44 Relevant Interfaces on ICM Board
Direc-
Cable is connected to GPS antenna, receiving GPS

GPS Input satellite signal
PP2S Output From GPS module to the front panel PP2S
10M Output From GPS module to the front panel 10M
Bidirec- From GPS module to the front panel debugging serial

ICM panel MON tional port
CLKOUT Output 6 * clock output, connected to different resource

shelves/GB resource shelves and control shelves.
One CLKOUT outputs 1-to-6 cable. One shelf has two
UIM/GUIM boards, and uses a group of active/standby
clocks (a group of active/standby clocks include two
16 M, two 8 K, and two PP2S signals). Therefore, one
CLKOUT can connect three shelves, that is three groups
of clock outputs. RCKG1 has 2 CLKOUTs and provides
CLKOUT Output six clock outputs, that is connecting six shelves.
2 x 8 K reference input. If SDTB/SDTB2 provides the

clock reference, this port is connected with 8KOUT/DE-
BUG-232 on RGIM1. If DTB provides the clock refer-
ence, this port is connected with 8KOUT/DEBUG-232 on
RDTB. If SPB/SPB2 provides the clock reference, this
8 KIN1 Input port is connected with 8KOUT/CPU1-RS232 on RSPB.
2 x 8 K reference input, connecting GPS clock reference

source. To guarantee the reference redundancy, 8KIN2
8 KIN2 Input can input link 8 K clock reference as the standby clock.
RCKG1
panel for 1 x 2 Mbps and 2 MHz input, connected to external
rear board BITS clock reference source.
(version 75 ohms coaxial cable or 120 ohms twist pairs, max
040503) 2 Mbps/2 MHz Input transmission distance 250 m
CLKOUT Output nine clock output interfaces connect different resource

CLKOUT Output
RCKG2 has three CLKOUTs and provides nine clock
outputs, that is connecting nine shelves.
RCKG1 and RCKG2 working together can connect 15
RCKG2
shelves. It is the max number of clock connections
panel for
CLKOUT Output currently for iBSC.
rear board
(version 1 x GPS reference input, connecting the external GPS
040502) PP2S/16CHIP Input clock reference source.
5-71

Direc-
CLKOUT Output Six clock output interfaces connect different resource

UIM/GUIM boards and uses two clock sockets, so a
CLKOUT can connect three shelves, that is, three clock
outputs. RCKG1 has 2 CLKOUTs and provides six clock
outputs, that is connecting six shelves.
The output of RCKG1 and RCKG2 with the same
number is a group of active/standby clock, connecting
the rear board of UIM/GUIM board in the active/standby
CLKOUT Output slot.
8 K reference input. If SDTB/SDTB2 provides the clock

reference, this port is connected with 8KOUT/DEBUG-
232 on RGIM1. If DTB provides the clock reference, this
port is connected with 8KOUT/DEBUG-232 on RDTB.
If SPB/SPB2 provides the clock reference, this port is
8 KIN1 Input connected with 8KOUT/CPU1-RS232 on RSPB.
Bidirec- The system debugging serial port, connecting the debug-

RS232 tional ger.
RCKG1
panel for 1 x 2 Mbps and 2 MHz reference clock input, connected
rear board to external BITS clock reference source.
(version 75 ohms coaxial cable or 120 ohms twist pairs, max
071200) BITS REF Input transmission distance 250 m
CLKOUT Output Six clock output interfaces connect different resource

UIM/GUIM boards and uses two clock sockets, so a
CLKOUT can connect three shelves, that is, three clock
outputs. RCKG1 has 2 CLKOUTs and provides six clock
outputs, that is connecting six shelves.
The output of RCKG1 and RCKG2 with the same
number is a group of active/standby clock, connecting
the rear board of UIM/GUIM board in the active/standby
CLKOUT Output slot.
8 K reference input. If SDTB/SDTB2 provides the clock

RCKG2 reference, this port is connected with 8KOUT/DEBUG-
panel for 232 on RGIM1. If DTB provides the clock reference, this
rear board port is connected with 8KOUT/DEBUG-232 on RDTB.
(version If SPB/SPB2 provides the clock reference, this port is
071200) 8 KIN2 Input connected with 8KOUT/CPU1-RS232 on RSPB.
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Chapter 5 Board
Direc-
Bidirec- The system debugging serial port, connecting the debug-

RS232 tional ger.
1 x 2 Mbps and 2 MHz reference clock input, connected

to external BITS clock reference source.
75 ohms coaxial cable or 120 ohms twist pairs, max
BITS REF Input transmission distance 250 m
Note:
5.16.5 ICM Buttons

Table 5-45 shows the panel buttons on the ICM board.
Table 5-45 ICM Panel Buttons
Name Description
RST Reset switch

After MANEN is pressed, the manual clock reference selection is enabled,
MANEN the MANI indicator is ON.

MANSL (corresponding indicators such as 8K1, 8K2, 8K3, or NULL will be ON).
5.16.6 ICM Indicators

There are 23 indicators on the ICM panel. Table 5-46 gives the specific meanings.
5-73

Table 5-46 ICM Panel Indicators
RUN Green Running indicator Refer to "Description of combined indicator status"

Board extraction In- does not use resource, can be extracted.

Indicates the clock reference that ICM board

selects
clock reference provided by BITS equipment,
Bps1 Green Reference indicator which is transmitted in HDB3 coding form

selects
ON: Indicates CLKG (ICM) selects the second 2
Mbps clock reference provided by BITS equipment,
Bps2 Green Reference indicator which is transmitted in HDB3 coding form

selects
clock reference provided by BITS equipment,
Hz1 Green Reference indicator which is transmitted in TTL differential form

selects
form of TTL difference, which is provided by BITS
Hz2 Green Reference indicator equipment.
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Chapter 5 Board

selects
ON: Indicates that the selected reference is the 8K
8 K1 Green Reference indicator clock extracted by the line.

selects
ON: Indicates that the clock reference is a 8 kHz
8 K2 Green Reference indicator clock reference provided by external GPS

selects
ON: Indicates that the selected reference is the 8K
8 K3 Green Reference indicator clock reference provided by GUIM or UIMC.

selects
ON: Indicates that the clock reference is a 8 kHz
8 K4 Green Reference indicator clock reference provided by the boards GPS

selects
ON: Indicates that no external reference is
NULL Green Reference indicator available and system is in free oscillating status
Reference deterio- ON: Indicates the selected reference has deterio-

QUTD Red ration indicator rated
ON: Indicates that the board is currently in catch

status, that is, a reference has been found but has
CATCH: Green Catch indicator not been locked onto
ON: Indicates that the board is currently in trace sta-

tus, that is, a reference has been found and locked
TRACE: Green Trace indicator onto
ON: Indicates that the reference has been lost after

KEEP Green Hold indicator being locked onto

FREE Green Free indicator is in free running status

manually
Manual selection in- OFF: Indicates that the reference can not be
MANI: Green dicator selected manually
5-75

Always ON: indicates system clock is OK.

Always OFF: Indicates that the 16CHIP Phase
Locked Loop (PLL) loses lock.
Flashing very quickly: Indicates that the output
16CHIP signal is proper
System clock refer- Flashing very slowly: Indicates that the output
SCS Green ence indicator PP2S signal is improper.
Always ON: Indicates that the circuit clock 12.8 M

PLL is locked properly.
Circuit clock refer- Always OFF: Indicates that the circuit clock 12.8
CCS Green ence indicator M PLL loses lock.
Receiver initialization, antenna feeder opened, and

normal indication
Always ON: Indicates antenna feeder ok.
Always OFF: indicates antenna feeder and satellite
ok, initializing.
Flashing at 1 Hz (slow): Indicates that antenna
feeder is broken.
Flashing at 2 Hz (quickly): Indicates that antenna
feeder is normal but cannot receive satellite signal.
Flashing at 0.5 Hz (very slow): Indicates that
antenna is short-circuited.
Antenna status indi- Flashing at 5 Hz (very fast): Indicates that no
ANT Green cator message is received during initialization.
Always OFF (black): GPS single-mode receiver.

Always ON (green): GPS/GONOLASS dual-mode
receiver
Green/Yel- Always ON (yellow): GPS/GONOLASS/ Triones
TYP low Mode indicator timed three-mode receiver.
5.16.7 ICM DIP Switches

DIP switches, S1 and S5, on ICM are used to select the matching impedance of BITS clock
line. The default resistance is 75 ohms. Table 5-47 shows the description of DIP switches.
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Chapter 5 Board
Table 5-47 ICM DIP Switches
Setup
Name of Default
Mode DIP Switch 1 2 3 4 Mode
S1 ON ON ON ON
75 ohms S5 ON ON ON ON
S1 ON ON ON ON
100 ohms S5 OFF OFF OFF OFF
S1 OFF OFF OFF OFF
120 ohms S5 OFF OFF OFF OFF 75 ohms
5.17 Operation and Maintenance Processing (OMP)

Board
5.17.1 OMP Functions
OMP provides the following functions:
l Implements all the operation and maintenance processes and related controls, and
provides a FE interface to connect OMM through 100 Mbps Ethernet.
l As the processing core of ZXG10 iBSC operation & maintenance, it can directly or
indirectly monitor and manage all boards in the system. It provides two links (Ethernet
and RS485) for configuration management of system boards.
5.17.2 OMP Principle

For OMP principle, refer to "CMP Principle". The difference is that CPU_A provides the
hard disk.
5.17.3 OMP Panel

As the OMP board, CPU_A provides hard disk and CPU_B does not provide the hard disk.
The rear board for OMP board is RMPB. Figure 5-32 shows the OMP board.
5-77

Figure 5-32 OMP Board
1. OMP panel for front board 2. OMP layout 3. RMPB panel for rear board
5.17.4 OMP Interfaces

Table 5-48 shows the relevant interfaces on OMP board.
Table 5-48 Relevant interfaces on OMP board
USB1 Bi. -
Front board USB2 Bi. -
External Ethernet network interface for CPU_A,

OMC1 Bi. unused.
OMC2 Bi. 1x100 M Ethernet interface, connected to OMM
Connected to GPS function module (unavailable

GPS485 Bi. currently)
PD485 Bi. Connected to RS485 interface on PDM (Up).
RS232 Bi. Out-of-band management serial port.
Debugging serial port for CPU_A, connected to

DEBUG1-232 Bi. the debugger.
RMPB Panel for Debugging serial port for CPU_B, connected to

rear board DEBUG2-232 Bi. the debugger.
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Chapter 5 Board
5.17.5 OMP Buttons

Table 5-49 shows the relevant buttons on the OMP board.
Table 5-49 OMP Panel Buttons
Name Description
RST Reset switch
Active/Standby switchover for CPU_B

EXCH1 Do the switchover for the same CPU system on the adjacent board.
Active/Standby switchover for CPU_A

EXCH2 Do the switchover for the same CPU system on the adjacent board.
5.17.6 OMP Indicators

Table 5-50 shows the indicators on OMP board.
Table 5-50 OMP Board Indicators
CPU_A alarm indi-

ALM1 Red cator Refer to "Description of combined indicator status"
CPU_A RUN indi-

RUN1 green cator Refer to "Description of combined indicator status"

CPU_A board ex- or does not use resource, can be extracted.
ENUM1 Yellow traction indicator OFF: Indicates that the micro switch is proper.
CPU_A ac-
ACT1 green tor OFF: Indicates the board is standby
Hard Disk Indicator Flashing at 5 Hz (quickly): indicates CPU_B is

HD1 Red 1 working
CPU_B alarm indi-

ALM2 Red cator Refer to "Description of combined indicator status"
5-79

CPU_B RUN indi-

RUN2 green cator Refer to "Description of combined indicator status"
CPU_B ac-
ACT2 green tor OFF: Indicates the board is standby

CPU_B board ex- or does not use resource, can be extracted.
ENUM2 Yellow traction indicator OFF: Indicates that the micro switch is proper.
Hard Disk Indicator Flashing at 5 Hz (quickly): indicates CPU_A is

HD2 Red 2 working
OMC network port ON: indicates that OMC network port 1 has been
OMC1 green indicator 1 connected
OMC network port ON: indicates that OMC network port 2 has been
OMC2 green indicator 2 connected
5.18 Packet Switching Network (PSN) Board

5.18.1 PSN Functions
Packet Switching Network (PSN) provides the following functions:
l Supports bi-directional user data switching at the rate of 40 Gbps in each direction.
l Implements 1+1 load sharing.
5.18.2 PSN Principle

Figure 5-33 shows the working principle of PSN board.
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Chapter 5 Board
Figure 5-33 Principle of PSN Board
1. The PSN board consists of the following three units:

a. CPU unit
It connects with UIMC via one FE for operation and maintenance and with the
matrix switching unit via the control bus for basic configuration and management.
b. Logic unit
It implements the required logical functions inside the boards.
c. Matrix switching unit

It provides external high-speed serial link, connecting with GLI and realizing the
data switching path.

The data from GLI is sent to the matrix switching unit via the high-speed serial link on
the backplane. After the switching, the data is sent to the target GLI.
5.18.3 PSN Panel

Figure 5-34 shows the PSN panel.
5-81

Figure 5-34 PSN Panel
5.18.4 PSN Interfaces

PSN does not provide external interface.
5.18.5 PSN Buttons

Table 5-51 shows the buttons on PSN board.
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Chapter 5 Board
Table 5-51 PSN Panel Buttons
Name Description
RST Reset switch
5.18.6 PSN Indicators

There are 4 indicators on the panel of PSN board. Table 5-52 describes its specific
meanings.
Table 5-52 PSN Panel Indicators

RUN green Running indicator status"


Flashing at 1 Hz: Indicates that the board can
be extracted; during the boards running, the
micro switch is turned on, the board, which
is standby or does not use resource, can be
Board extraction extracted.

ACT green Active/standby indicator OFF: Indicates the board is standby
5.19 Power Distribution (PWRD) Board

5.19.1 PWRD Functions
PWRD provides the following functions:
l Provides -48 V power to shelves and fans inside the cabinet.
l Detects rack power and the environment, and generates alarms accordingly.
5-83

l PWRD is monitored and managed by OMP through RS485 interface. It reports the
detected information to OMP and indicates through indicators on the power distribution
plug-in box panel.
5.19.2 PWRD Principle

Figure 5-35 shows the working principle of PWRD board.
Figure 5-35 General Structure of PWRD Board
By structure, PWRD falls into the following parts: one PDM, one PWRD, one PWRDB and
four fan group control modules.
1. PDM implements filter, lightning protection and isolation on 2-channel -48 V, sends
it to the busbar to supply shelves, samples and sends the samples to PWRD for
over-/under-voltage monitoring before the 2-channel power supply convergence.
2. PWRD detects the 2-channel -48 V over-/under-voltage, speed of 24 fans, ambient
temperature, ambient humidity, smoke alarm, infrared alarm, cabinet, and equipment
room door control.
PDM and PWRD form a power distribution subrack.
3. 2 x 3 fan group and the fan group control module form a fan subrack.
Fan subrack takes -48 V from the busbar and sends fan monitoring signals to PWRD.
4. PWRDB provides external monitoring signal interface for PWRD, accessing the
system monitoring signals.
5.19.3 PWRD Panel

Figure 5-36 shows the PWRD board.
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Chapter 5 Board
Figure 5-36 PWRD Board
5.19.4 PWRD DIP Switches and Jumpers
Note:
You should reset the board by the reset switch after changing the DIP and jumper settings.
DIP Switches
Table 5-53 shows the description of DIP switches on PWRD board.
Table 5-53 PWRD DIP Switches
Setting Default
ID Pur. Mode 1(H) 2 3 4(L) 1 2 3 4
CONFIG
switch (set
the working
mode to nor-
mal or de-
bugging and
the default
value is nor- It is used to set the working mode O-
S2 mal). independent of the user. ON OFF N ON
SWITCH (set 0(ON) ON ON ON ON

the commu-
nication ad-
dress of 485
and OMP,
use positions
switch to set
0-15 (16 dif-
ferent ad-
dresses in to- O-
S3 tal), and it 1(OFF) OFF OFF OFF OFF ON ON N ON
5-85

Setting Default
ID Pur. Mode 1(H) 2 3 4(L) 1 2 3 4
corresponds
to the rack id
for the board.
Jumper
On the PWRD board, there are 2x5 pins to be used as the short-circuit jumper X8 for 485
signal. If iBSC uses multiple racks, you should set the working mode of 485 busbar on the
PWRD board depending on the rack position.
1. If the PWRD board is located at the end of 485 busbar, you should connect the
resistance terminal. Only pin 1-2 and pin 9-10 are connected in short circuit. This is
the default value, as shown in Figure 5-37.
Figure 5-37 Jumpers
2. If the PWRD board is located in the middle of 485 busbar, you should transfer the 485
signal to the output port. Only pin 3-4 and pin 7-8 are connected in short circuit.
5.20 Server Board (SBCX)

5.20.1 SBCX Functions
SBCX provides the following functions.
l Provides interfaces for keyboard, mouse, and VGA.
l CPU is Sossaman dual-channel dual-core processor, with a main frequency of 2 GHz.
l Supports multiple operating systems, including Windows XP/2000/2003/Linux and
Soloris operating system.
l Provides 4 FE interfaces and 2 GE interfaces.
l Provides 4 USB interfaces.
l Supports booting from hard disk and USB.
5.20.2 SBCX Principle

Figure 5-38 shows the working principle of SBCX board.
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Chapter 5 Board
Figure 5-38 Principle of SBCX Board
THe SBCX board consists of the following five units:

1. CPU dual-core system: It is the core processing module of the board, including CPU,
memory controller, and main storage.
2. Peripheral device unit: It provides various external interfaces, including PS/2 interface,
USB interface, and VGA interface.
3. External interface unit: It provides 4 FE interfaces and 2 GE interfaces.
4. SAS controller: It provides SAS hard disk interface, realizes the SAS hard disk RAID
0/1.
5. SAS hard disk: It saves service data.
5.20.3 SBCX Panel

RSVB is the rear board of SBCX, as shown in Figure 5-39.
5-87

Figure 5-39 SBCX Board
1. SBCX Panel for front board 2. RSVB Panel for rear board
5.20.4 SBCX Interfaces

Table 5-54 shows the meanings of relevant SBCX interfaces.
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Chapter 5 Board
Table 5-54 Relevant SBCX Interfaces
USB1 Bi. USB Interface
KB Input PS/2 Keyboard Interface
MS Input PS/2 Mouse Interface
VGA Output Analog Monitor Interface

SBCX panel for
front board 2 pairs of TX-RX - Unused
External network port 1,

GB 1000baseT, maxi-
mum transmission dis-
OMC1 Bi. tance: 50 m
External network port 2,

GB 1000baseT, maxi-
mum transmission dis-
OMC2 Bi. tance: 50 m
External network port

3, 100baseT, maximum
transmission distance: 50
OMP1 Bi. m

HEART1 Bi. m

HEART2 Bi. m

transmission distance 50
OMP2/RS232 Bi. m, keep unused

RSVB panel for rear
board USB2 Bi. USB Interface
5.20.5 SBCX Buttons

Table 5-55 shows the buttons on SBCX board.
5-89

Table 5-55 SBCX Panel Buttons
Name Description
RST Reset switch
PWB Board power switch
ENUM1 Board-unplugging switch of SAS hard disk 1
ENUM2 Board-unplugging switch of SAS hard disk 2
5.20.6 SBCX Indicators

Table 5-56 describes the specific meanings of SBCX panel indicators.
Table 5-56 SBCX Panel Indicators
Running indica- Refer to "Description of combined indicator status",

RUN green tor unused.
Refer to "Description of combined indicator status",

ALM Red Alarm indicator unused.

does not use resource, can be extracted.
Board extrac- OFF: Indicates that the micro switch is proper.
ENUM Yellow tion Indicator Unused

Active/standby OFF: Indicates the board is standby
ACT green indicator Unused
ON: IDE hard disk is being accessed.

IDE Hard Disk OFF: IDE hard disk is idle.
HD green Indicator It is prohibited to unplug the board when HD is ON.
Board power in- ON: board is powered on.

PWR green dicator OFF: board is powered off.
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Chapter 5 Board
SAS hard disk

1 read/write in- ON: SAS hard disk 1 is being accessed.
SAS1 green dicator OFF: SAS hard disk 1 is idle.
SAS hard disk 1 ON: SAS hard disk 1 is not in position or is faulty.
ALM1 Yellow fault indicator OFF: SAS hard disk 1 is normal.
SAS hard disk

2 read/write in- ON: SAS hard disk 2 is being accessed.
SAS2 green dicator OFF: SAS hard disk 2 is idle.
SAS hard disk 2 ON: SAS hard disk 2 is not in position or is faulty.
ALM2 Yellow fault indicator OFF: SAS hard disk 2 is normal.
FC interface 1
running indica-
ACT green tor Unused
FC interface 1
SD Yellow rate indicator Unused
FC interface 2
running indica-
ACT green tor Unused
FC interface 2
SD Yellow rate indicator Unused
5.21 SONET Digital Trunk Board (SDTB)

5.21.1 SDTB Functions
SDTB is used as digital relay interface board, providing one 155 Mbps STM-1 interface.
SDTB provides the following functions.
l Provides one 155 Mbps STM-1 interface.
l Provides the APS function.
l Supports Channel Associated Signal (CAS) and Common Channel Signaling (CCS).
l Outputs two differential 8 K synchronous clock signals for reference of the clock board
5.21.2 SDTB Principle

Figure 5-40 shows the working principle of SDTB board.
5-91

Figure 5-40 Principle of SDTB Board
1. The SDTB board consists of the following five units:
b. Interface unit: It is connected with circuit switching unit, and provides STM-1
interface.
e. Clock processing unit: It receives the clock from system clock board, and provides
the reference clock signal extracted from STM-1.
From the receiving direction, the STM-1 optical data from the line side is processed by
the interface unit, sent to the circuit switching unit for switching, and then sent to the
UIMU/GUIM board,
and vice versa.
5.21.3 SDTB Panel

Figure 5-41 shows the SDTB panel.
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Chapter 5 Board
Figure 5-41 SDTB Panel
1. SDTB Panel for front board 2. RGIM1 panel for rear board
Note:
If it does not require to extract the 8 K clock reference from SDTB, then RGIM1 is not be
used. If it requires to extract the 8 K clock reference from SDTB, then RGIM1 is used.
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5.21.4 SDTB Interfaces

Table 5-57 shows the relevant interfaces on SDTB board.
Table 5-57 Relevant interfaces on SDTB board
Standard 155M STM-1 interfaces, LC

connector used
Single-mode S-1.1
Wavelength (nm): 1310 nm
Transmit optical power: -14 ~ -8 dBm
Receiving sensitivity ≤ -31 dBm
SDTB Panel for Max rx optical power: -8 dBm
front board TR-TX Bi. Max transmission distance: 15 km
RGIM1 panel for 8KOUT/DEBUG- Leads out 8K reference clock signal and
rear board 232 Bi. debugging signal at RS232 serial port
5.21.5 SDTB Buttons

Table 5-58 shows the relevant buttons on the SDTB board.
Table 5-58 SDTB Panel Buttons
Name Description
EXCH Active/Standby switchover switch
RST Reset switch
5.21.6 SDTB Indicators

There are six indicators on SDTB panel. Table 5-59 explains their meanings.
Table 5-59 SDTB Panel Indicators
Running indi-
RUN green cator Refer to "Description of combined indicator status"
Alarm indica-
ALM Red tor Refer to "Description of combined indicator status"
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Chapter 5 Board

on and has alarm.
extracted; during the boards running, the micro switch
is turned on, the board, which is standby or does not
Board extrac- use resource, can be extracted.
Board Ac-
tive/Standby ON: board is active.
Optical mod-
ule Ac- ON: optical interface is active.
tive/Standby OFF: optical interface is standby.
ACT green indicator This indicator is close to the SD indicator.
ON: indicates optical board has received optical

signals.
Optical signal OFF: indicates optical board has not received optical
SD green indicator signals.
5.22 SONET Digital Trunk Board2 (SDTB2)

5.22.1 SDTB2 Functions
SDTB2 is used as digital relay interface board, providing two 155 Mbps STM-1 interfaces.
SDTB2 provides the following functions.
l Provides 2 155M STM-1 standard interfaces.
l Provides the APS function.
l Supports Channel Associated Signal (CAS) and Common Channel Signaling (CCS),
provides an access processing capability of 126 E1s or 168 T1s.
l Outputs two differential 8 K synchronous clock signals for reference of the clock board
5.22.2 SDTB2 Principle

Figure 5-42 shows the working principle of SDTB2 board.
5-95

Figure 5-42 Principle of SDTB2 Board
1. The SDTB2 board consists of the following five units:
b. Interface unit: It is connected with circuit switching unit, and provides STM-1
interface.
e. Clock processing unit: It receives the clock from system clock board, and provides
the reference clock signal extracted from STM-1.
From the receiving direction, the STM-1 optical data from the line side is processed by
the interface unit, sent to the circuit switching unit for switching, and then sent to the
GUIM board,
and vice versa.
5.22.3 SDTB2 Panel

Figure 5-43 shows the SDTB2 panel.
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Chapter 5 Board
Figure 5-43 SDTB2 Panel
1. SDTB2 Panel for front

board
2. RGIM1 panel for rear board
Note:
If it does not require to extract the 8 K clock reference from SDTB2, then RGIM1 is not be
used. If it requires to extract the 8 K clock reference from SDTB2, then RGIM1 is used.
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5.22.4 SDTB2 Interfaces

Table 5-60 shows the relevant interfaces on SDTB2 board.
Table 5-60 Relevant interfaces on SDTB2 board
TR1-TX1 Bi. Standard 155M STM-1 interfaces

Single-mode S-1.1
Wavelength (nm): 1310 nm
Transmit optical power: -14 ~ -8 dBm
Receiving sensitivity ≤ -31 dBm
SDTB2 panel for front Max rx optical power: -8 dBm
board TR2-TX2 Bi. Max transmission distance: 15 km
RGIM1 panel for rear Leads out 8K reference clock signal and
board 8KOUT/DEBUG-232 Bi. debugging signal at RS232 serial port
5.22.5 SDTB2 Buttons

Table 5-61 shows the panel buttons on the SDTB2 board.
Table 5-61 SDTB2 Panel Buttons
Name Description
EXCH Active/Standby switchover switch
RST Reset switch
5.22.6 SDTB2 Indicators

There are 8 indicators on SDTB2 panel. Table 5-62 explains their meanings.
Table 5-62 SDTB2 Panel Indicators
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Chapter 5 Board

Board extraction or does not use resource, can be extracted.
Board Ac-
tive/Standby indi- ON: board is active.
ACT green cator OFF: Indicates the board is standby
ON: optical interface is active.

Optical module 1 OFF: optical interface is standby.
Active/Standby in- This indicator is close to the SD optical signal 1
ACT green dicator indicator

signals.
Optical signal 1 in- OFF: indicates optical board has not received
SD green dicator optical signals.
ON: optical interface is active.

Optical module 2 OFF: optical interface is standby.
Active/Standby in- This indicator is close to the SD optical signal 2
ACT green dicator indicator

signals.
Optical signal 2 in- OFF: indicates optical board has not received
SD green dicator optical signals.
5.23 Signaling Processing Board (SPB)

5.23.1 SPB Functions
According to functions realized, SPB can be used as LAPD processing board (LAPD),
signaling processing board (SPB), and Gb interface processing board (GIPB).
LAPD mainly handles the LAPD signal. The LAPD signal from BTS is accessed by
DTB/SPB board, and switched to LAPD board through the circuit switching network
5-99

on UIMU/UIMC board in the resource shelf. The LAPD board implements the LAPD
processing.
SPB mainly handles the MTP2 and X.25 protocols. Extracts 8 kHz synchronization clock
from a line and transfer it through a cable to clock generation board as a reference clock.
GIPB handles GPRS FR and NS, and some BSSGPs, and some Gb interface functions.
SPB supports the following cables:
l Supports 120/75 Ω resistance selection, and supports coaxial cable and twisted pair.
l Supports 100 Ω twisted pair for T1.
5.23.2 SPB Principle

Figure 5-44 shows the working principle of SPB board.
Figure 5-44 Principle of SPB Board
1. The SPB board consists of the following five units:
a. Interface unit: It is connected with circuit switching unit, and provides E1 interface.
b. Circuit switching unit: The circuit of the interface unit and backplane realizes the
switching function.
c. CPU unit: It implements the function of signaling processing, board management

and internal connection control.
d. Control plane switching unit: It implements the data switching and provides the
FE interface at control plane.
e. User plane switching unit: It implements the data switching and provides the FE
The data from E1 interface or backplane is sent to the circuit switching unit for switching
after being processed by the interface unit, then sent to CPU, and at last sent to other
board by switching unit for processing.
5.23.3 SPB Panel

Figure 5-45 shows the SPB board.
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Chapter 5 Board
Figure 5-45 SPB Board
1. SPB panel for front board 2. SPB Layout 3. RSPB Panel for rear board
5.23.4 SPB Interfaces

Table 5-63 shows the relevant interfaces on SPB board.
Table 5-63 Relevant interfaces on SPB board
16 x E1 Interface to connect the

external system
75/120 ohms E1 interface; 100 ohms
T1 interface
Maximum transmission distance:
T1/E1 1-16 Bi. 250 m
Leads out 8K recovery clock signal

8KOUT/CPU1- and debugging signal at RS232 serial
RS232 Bi. port
Lead out RS232 serial port debug-

CPU2-RS232 Bi. ging signal.
Lead out RS232 serial port debug-

CPU3-RS232 Bi. ging signal.
RSPB Panel for Lead out RS232 serial port debug-

rear board CPU4-RS232 Bi. ging signal.
5-101

5.23.5 SPB Buttons

Table 5-64 shows the relevant buttons on SPB board.
Table 5-64 SPB Panel Buttons
Name Description
RST Reset switch
5.23.6 SPB Indicators

There are 4 indicators on the SPB panel. Table 5-65 describes its specific meanings.
Table 5-65 SPB Panel Indicators
Running indi-
RUN green cator Refer to "Description of combined indicator status"
On: An alarm exists on the board.

Off: No alarm is generated on the board.
Alarm indica- For specific meanings, refer to "Description of combined
ALM Red tor indicator status".

and has alarm.
extracted; during the boards running, the micro switch
is turned on, the board, which is standby or does not
Board extrac- use resource, can be extracted.
Ac-
tive/standby ON: Indicates the board is active
OFF: indicates unconfigured database at this E1/T1

Always ON: indicates configured database at this E1/T1
but E1/T1 disconnected
indicates configured database at this E1/T1 and E1/T1
is connected
16 x E1 Indica- Flashing in 5Hz (quickly): indicates there is link service
L1~ L16 green tors in this E1/T1.
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Chapter 5 Board
5.23.7 SPB DIP Switches and Jumpers

1. Description of DIP Switch
There are six 4-digit DIP switches on the SPB board. Table 5-66 shows the description
of SPB DIP switches.
Table 5-66 Description of SPB DIP Switches
Setup
Name of
DIP Switch Purpose Mode 1 2 3 4
Used to choose 75 ohms ON ON ON ON

the matching re-
sistance for dif-
S3~S6 ferent E1s. 120 ohms OFF OFF OFF OFF
Used to indicate Short haul ON ON ON ON

the short/long
haul of the
proper E1 chips
S1 for CPU. Long haul OFF OFF OFF OFF
Used to indi- 75 ohms ON ON ON ON

cate the match-
ing receiving re-
sistance of the
proper E1 chips
S2 for CPU. 120 ohms OFF OFF OFF OFF
a. S3~S6 are used to choose the receiving matching resistance in different E1s.
OFF indicates that the matching resistance is 120 ohms and ON indicates that
the matching resistance is 75 ohms.
l Channels 1-4 of S3 respectively represent the E1s in channel 1-4.
b. S1 and S2 indicate the receiving matching impedance and long/short haul state
of each E1 chip respectively. CPU reads this status during power-on and initiates
each E1 chip according to this status.
Channels 1-4 of S1/S2 respectively represent the E1 Chips 1-4 (namely, E1

channels 1-4, 5-8, 9-12, and 13-6).
l If S1 is OFF (1 is retrieved), it indicates long haul. If S1 is ON (0 is retrieved),

it indicates short haul.
l If S2 is OFF (1 is retrieved), it indicates that the matching impedance is 120
ohms. If S2 is ON (0 is retrieved), it indicates that the matching impedance is
75 ohms.
5-103

2. Jumper Description
SPB supports two types of external trunk cables: 75 ohms co-axial cables and 120
ohms balanced symmetric cables. There are four jumpers on the RSPB panel, as
shown in Figure 5-46.
Figure 5-46 Positions of RSPB Jumpers
If co-axial cables are used, short-circuit blocks shall be added to the 32 jumpers of
X11, X12, X13 and X14. In other words, the negative end of E1 transmitting differential
cable is grounded directly, and the negative end of E1 receiving differential cable is
grounded through the capacitor.
On RSPB, the E1 line is configured as 75 ohms co-axial transmission mode by default.
The settings of X11-X14 are shown in Table 5-67.
Table 5-67 RSPB Jumper Settings
X11 ~ X14 Connections Description
12 Connecting E1_TX (N) -R to protection ground (line N)
Connecting E1_RX (N) -R to protection ground (line

34 N)
Connecting E1_TX (N+1) -R to protection ground (line

56 N+1)
Connecting E1_RX (N+1) -R to protection ground (line

78 N+1)
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Chapter 5 Board
X11 ~ X14 Connections Description

9 10 N+2)

11 12 N+2)

13 14 N+3)

15 16 N+3)
Note:
Short-circuit blocks of jumpers X11-X14 on rear board shall be removed if E1 uses 120
ohms balanced cable.
5.24 Signaling Processing Board 2 (SPB2)

5.24.1 SPB2 Functions
According to functions, SPB2 can be used as signaling processing board (SPB2) and Gb
interface processing board (GIPB2).
SPB2 mainly handles the MTP2 and X.25 protocols, extracts 8 kHz synchronization clock
from line, and transfers it through a cable to clock generation board as a reference clock.
GIPB2 processes GPRS FR, NS, and some BSSGP, and performs the Gb interface
functions.
SPB2 provides 16 E1/T1 links and supports the following cables:
l Supports 120/75 Ω impedance selection for E1, and supports coaxial cable and
twisted pair.
l Supports 100 Ω impedance twisted-pair for T1.
5.24.2 SPB2 Principle

Figure 5-47 shows the working principle of SPB2 board.
5-105

Figure 5-47 SPB2 Principle
1. The SPB2 board consists of the following five units:

a. Interface unit: It is connected with circuit switching unit, and provides E1 interface.
b. Circuit switching unit: The circuit of the interface unit and backplane realizes the
switching function.
c. CPU unit: It implements the function of signaling, board management and internal
connection control.
d. Control plane switching unit: It implements the data switching and provides the
FE interface at control plane.
e. User plane switching unit: It implements the data switching and provides the FE
The data from E1 interface or backplane is sent to the circuit switching unit for switching
after being processed by the interface unit, then sent to CPU, and at last sent to other
board by switching unit for processing.
5.24.3 SPB2 Panel

Figure 5-48 shows the SPB2 board.
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Chapter 5 Board
Figure 5-48 SPB2 Board
1. SPB2 panel for front board 2. RSPB Panel for rear board
5.24.4 SPB2 Interfaces

Table 5-68 shows the relevant interfaces on SPB2 board.
Table 5-68 Relevant interfaces on SPB2 board
16 x E1 Interface to connect the external

system
75/120 ohms E1 interface; 100 ohms T1
interface
T1/E1 1-16 Bi. Maximum transmission distance: 250 m
8KOUT/CPU1- Leads out 8K recovery clock signal and debug-

RS232 Bi. ging signal at RS232 serial port
CPU2-RS232 Bi. Lead out debugging signal at RS232 serial port.

RSPB Panel for
rear board CPU3-RS232 Bi. Lead out debugging signal at RS232 serial port.
5-107

CPU4-RS232 Bi. Lead out debugging signal at RS232 serial port.
5.24.5 SPB2 Buttons

Table 5-69 shows the relevant buttons on SPB2 board.
Table 5-69 SPB2 Panel Buttons
Name Description
RST Reset switch
5.24.6 SPB2 Indicators

There are 20 indicators on the SPB2 panel. Table 5-70 describes its specific meanings.
Table 5-70 SPB2 Panel Indicators
Running indica- Refer to "Description of combined indicator sta-

RUN green tor tus"
On: An alarm exists on the board.

Off: No alarm is generated on the board.
For specific meanings, refer to "Description of
ALM Red Alarm indicator combined indicator status".


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Chapter 5 Board
OFF: indicates unconfigured database at this

E1/T1
Always ON: indicates configured database at
this E1/T1 but E1/T1 disconnected
indicates configured database at this E1/T1
and E1/T1 is connected
16 x E1 Indica- Flashing in 5Hz (quickly): indicates there is
L1~ L16 green tors link service in this E1/T1.
5.25 Universal Interface Module for Control Plane

(UIMC)
5.25.1 UIMC Functions
UIMC mainly implements Ethernet level-2 switching in control shelf and manages the
control shelf. Provides an internal user plane GE interface to cascade UIMC with CHUB
in the control shelf.
UIMC provides the clock-driven function inside the control shelf. Input PP2S, 8 kHz and
16 MHz signals are distributed to various slots after phase lock and drive, to provide 16
MHz and 8 kHz clocks to the boards.
UIMC provides the management interfaces for control shelf and switching shelf; also
provides the signal collection functions of resetting the control shelf and switching shelf.
5.25.2 UIMC Principle

Figure 5-49 shows the working principle of UIMC board.
5-109

Figure 5-49 UIMC Principle
1. The UIMC board consists of the following three units:

a. CPU unit
bus. It configures the switching unit and manages the resource shelf/GB resource
shelf.
It externally provides debugging and active/standby external Ethernet interface.
b. Logic unit
c. Ethernet switching unit
It implements the control plane Ethernet switching function on the control shelf or
switching shelf.
The external data is from boards on the shelf where UIMC locates. It enters UIMC
Ethernet switching unit for the switching, and then is sent to the target board.
5.25.3 UIMC Panel

The rear boards of UIMC are RUIM2 and RUIM3. Figure 5-50 shows the UIMC board.
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Chapter 5 Board
Figure 5-50 UIMC Board
1. UIMC Panel for front board 2. RUIM2 panel for rear board 3. RUIM3 panel for rear board
5.25.4 UIMC Interfaces

Table 5-71 shows the relevant interfaces on UIMC board.
Table 5-71 Relevant interfaces on UIMC board
FE1 Bi.
FE3 Bi.
Provides 10 cascading network ports
FE5 Bi.
through the two rear boards in active and
FE7 Bi.
standby slots
FE9 Bi. FE7 and FE9 are used for TRUNK, unused.
RUIM2 panel for rear Connects clock board and transmits 8

board CLKIN Input Kbps/16 Mbps/PP2S clock signals.
5-111

Debugs network port in CPU system, con-

DEBUG-FE Bi. nected to the debug machine.
Debugs serial port for CPU system, con-

DEBUG-232 Bi. nected to the debug machine.
FE2 Bi.
FE4 Bi. Provides 10 cascading network ports

through the two rear boards in active and
FE6 Bi.
standby slots
FE8 Bi.
FE8 and FE10 are used for TRUNK,
FE10 Bi. unused.
Connects the clock board and transmits 8

CLKIN Input Kbps/16 Mbps/PP2S clock signals.
Ethernet debugging network port on CPU

sub-card, connected to the debugging ma-
DEBUG-FE Bi. chine.
RUIM3 panel for rear Serial debugging network port on CPU sub-
board DEBUG-232 Bi. card, connected to the debug machine.
5.25.5 UIMC Buttons

Table 5-72 shows the panel buttons on the UIMC board.
Table 5-72 UIMC Panel Buttons
Name Description
RST Reset switch
5.25.6 UIMC Indicators

Table 5-73 shows the indicators on UIMC board.
Table 5-73 UIMC Board Indicators
Active/standby in- ON: Indicates the board is active

ACT green dicator OFF: Indicates the board is standby
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Chapter 5 Board

Status indicator of ON: indicates the cascade 100 Mbps interface 1

cascade interface ~ 10 is connected at control plane.
1 ~ 10 at control OFF: indicates the cascade 100 Mbps interface 1
LINK1~10 green plane ~ 10 is not connected at control plane.
5.26 Universal Interface Module for User Plane (UIMU)

5.26.1 UIMU Functions
UIMU implements Ethernet level-2 switching in the resource shelf, CS domain timeslot
multiplexing switching, and resource shelf management, and provides external interface
for the resource shelf.
UIMU provides the clock-driven function in the gigabit resource shelf. The input 8 kHz and
16 MHz signals are distributed to various slots after phase lock and driving, to provide 16
MHz and 8 kHz clocks to boards in the gigabit resource shelf.
UIMU provides the resource shelf management function, RS-485 management interface in
the resource shelf, and the signal collection function to reset boards of the resource shelf.
5.26.2 UIMU Principle

Figure 5-51 shows the working principle of UIMU board.
5-113

Figure 5-51 UIMU Principle
1. The UIMU board consists of the following four units:

a. CPU unit
bus. It configures the switching unit and manages the gigabit resource shelf.
It provides debugging and active/standby external Ethernet interface.
b. Logic unit
c. Timeslot (TS) switching unit
It implements 16 K circuit switching and provides an internal circuit switching net
for the gigabit resource shelf.
It implements the user-plane/control-plane Ethernet switching function on the
The external data is from boards on the shelf where UIMU locates. It enters Ethernet
switching unit or timeslot switching unit for the switching, and then is sent to the target
board.
5.26.3 UIMU Panel

The rear board of UIMU is RUIM1. Figure 5-52 shows the UIMU board.
5-114

Chapter 5 Board
Figure 5-52 UIMU Board
1. UIMU Panel for front board 2. RUIM1 panel for rear board
5.26.4 UIMU Interfaces

Table 5-74 shows the relevant interfaces on UIMU board.
Table 5-74 Relevant interfaces on UIMU board
The fiber on front panel connects GLI board at

UIMU Panel for 2 pairs of switching unit. Use 2X1 Gbps optical interface
front board RX-TX Bi. at user plane for expansion.
5-115

FE C1/2 Bi. Provides four cascading network ports (through

the two rear boards in active and standby slots),
connected to CHUB or UIMC on the control
FE C3/4 Bi. shelf.
Provides external network ports (the two rear

boards in active and standby slots each pro-
FE-U Bi. vides one).
Connects clock board and transmits 8 Kbps/16

Debugs network port in CPU system, connects

DEBUG-FE Bi. the debugging machine.
RUIM1 panel for Debugs serial port for CPU system, connects
rear board DEBUG-232 Bi. the debugging machine.
5.26.5 UIMU Buttons

Table 5-75 shows the panel buttons on the UIMU board.
Table 5-75 UIMU Panel Buttons
Name Description
RST Reset switch
5.26.6 UIMU Indicators

Table 5-76 shows the indicators on UIMU board.
Table 5-76 UIMU Board Indicators

RUN green Running indicator status"

ACT green cator OFF: Indicates the board is standby

5-116

Chapter 5 Board

Board extraction In- extracted.
ON: indicates that UIMU packet domain is

active
Packet domain indi- OFF: indicates that UIMU packet domain is
ACT-P green cator standby
ON: indicates that the UIMU circuit domain

is active
Circuit domain indi- OFF: indicates that the UIMU circuit domain
ACT-T green cator is standby
ON: indicates the cascade 100 Mbps interface

1 ~ 4 is connected at control plane.
Status indicator of OFF: indicates the cascade 100 Mbps
cascade interface 1 interface 1 ~ 4 is not connected at control
LINK1~ LINK4 green ~ 4 at control plane plane.
ON: indicates that the current optical interface

is activated
GE interface 1 sta- OFF: indicates that the current optical
ACT1 green tus indicator interface is not activated
ON: indicates that the current optical interface

is activated
GE interface 2 sta- OFF: indicates that the current optical
ACT2 green tus indicator interface is not activated
ON: indicates that the optical module has

GE interface 1 opti- OFF: indicates that the optical module has
SD1 green cal signal indicator not received the optical signal
ON: indicates that the optical module has

GE interface 2 opti- OFF: indicates that the optical module has
SD2 green cal signal indicator not received the optical signal
5-117

5.27 User Plane Processing Board (UPPB)

5.27.1 UPPB Functions
UPPB handles the BSSGP, PDCP, GTP_U, and Iu_UP protocols in A/Gb and Iu modes.
5.27.2 UPPB Principle

Figure 5-53 shows the UPPB principle.
Figure 5-53 UPPB Principle
1. The UPPB board consists of the following five units:

a. CPU unit
It implements the management functions of board and handles the signals at Gb
interface. and provides external FE interface at control plane.
b. Logic unit
c. DSP unit
It includes multiple DSP chips and handles the core protocols at user plane.
It implements the Ethernet connection of multiple DSPs and provides external user
plane FE interface.
e. Clock unit
It provides necessary clock signal for each external unit on the board.
5-118

Chapter 5 Board
a. The user plane data from UIMU board enters the board via FE interface at user
plane, passes the Ethernet switching unit, and is distributed to the DSP unit.
b. After the DSP unit processes relative user plane protocols, the data is switched to
SPB via FE interface at user plane.
5.27.3 UPPB Panel

The UPPB board has no corresponding rear board. Figure 5-54 shows the panel of UPPB
board.
5-119

Figure 5-54 UPPB Panel
5.27.4 UPPB Interfaces

UPPB does not provide external interface.
5.27.5 UPPB Buttons

Table 5-77 shows the UPPB panel buttons.
5-120

Chapter 5 Board
Table 5-77 UPPB Panel buttons
Name Description
RST Reset switch
5.27.6 UPPB Indicators

There are 4 indicators on the panel of UPPB board. Table 5-78 describes its specific
meanings.
Table 5-78 UPPB Panel Indicators
Running indica- Refer to "Description of combined indicator

RUN green tor status"



5-121

5-122

Chapter 6
Auxiliary Equipment
Table of Contents
Alarm Box (ALB) ........................................................................................................6-1
Relevant GPS Devices ...............................................................................................6-9
6.1 Alarm Box (ALB)

6.1.1 ALB Functions
ALB can timely, accurately, visibly show the faults of communication equipment, easy for
maintenance staff and troubleshooting.
In general, the ALB is located in equipment room, connected with the equipment
at background. The background will send the alarm information collected from the
foreground to the alarm box to give alarm indication.
Functions of Alarm Box (ALB) are as follows:
1. SMS
NetNumen M31 sends the alarm message to ALB after the alarm message is
generated. The alarm message is sent to BTS by radio modem and received by the
final user.
2. LCD screen
The ALB receives the alarm message from background server and indicates it on the
ALB (by alarm indicator). ALB panel indicators display the detailed alarm messages
and you can scroll it by page down/up.
3. File transfer
Transfer the data by dialing in the ALB. The file size shall be lower than 200 K.
4. Voice alarm
The ALB can prompt the current alarm by voice hint.
5. GPRS message delivery
Receive the data from background and deliver it to emergency center timely by GPRS.
The ALB is designed in modular theory. It can implement the audible and visible function
based on alarm severity. Depending on the configuration, it can finish some enhanced
functions to meet the different product requirements.
The functions that can be expanded are described as follows.
6-1

l Alarm display function

ALB can show the information about current alarms, including the location, time, and
alarm contents.
l Alarm message delivery function
ALB can transfer the current alarm information by cable or radio mode to inform the
maintenance staff.
l Alarm information query function
ALB can receive the remote query command, send current alarm information to
remote side, or send the primary parameters to show the current operation state.
l Multi-offices in one
The different equipment in an office can use a common ALB to indicate the alarm
information from different devices.
l Operation & Maintenance Function
There is HMI on ALB. You can set the parameters and do self-diagnosis or query.
l Remote Function
ALB can be placed in the on-duty room with a distance of several hundred meters
from the equipment room.
l GPS timing function
By using the timing function of GPS receiver, the ALB can provide the accurate
absolute time or stable clock reference for synchronization.
6.1.2 Principle
Figure 6-1 shows the working principle of ALB board.
Figure 6-1 ALB Principle
6-2

Chapter 6 Auxiliary Equipment
Alarm box hardware includes five units.

1. Master unit
It is the core of alarm box, used to save OS, startup code and voice data. The space
for voice/word data is 8 MB and data storage space is 16 MB.
2. Interface Unit
The external interfaces of alarm box are as follows:
a. Ethernet interface
b. RS232 serial port
c. RS485 interface
d. Radio modem interface
e. Cable modem interface
f. GPS Interface
3. Man-machine Unit
It provides audible and visible alarm information and also provides the operation and
maintenance interface.
a. Alarm indicator
There are four alarm indicators, colored red, blue, yellow and green in order of
severity. When alarm occurs, the corresponding indicator will flash or be ON for a
long time.
There is no individual alarm indicator for environment alarm, but it is handled as
a certain level alarm.
b. Voice Alarm
The main control unit works in transparent HDLC mode, it sends the PCM voice
saved in FLASH to the PCM coder/decoder chip (CODEC) for coding, and the data
is converted to linear signal. Then the power amplifier drives the speaker, and the
audible alarm is realized.
The voice management at background realizes the voice recording, edit and
pre-play, and downloads the voice file into the FLASH of the alarm box.
c. LCD screen
LCM is used to display the alarm.

LCD is hung on the parallel bus of the master unit. LCM size is proper and it is
all-dots graphic display. Characters font size is controlled by software to display
different type of information.
LED has back facet power, which is generally OFF resulting in increased life of the
LED. When pressing the function button or displaying information, the back facet
power turns ON to display.
6-3

There are some function buttons on the alarm box, which realize the operation
and maintenance functions together with LCM.
4. Logic unit
Use EPLD to implement the required combinational and sequential logic.
5. Power supply unit
The input voltage of the alarm box is -48 V DC from the equipment room, and is
converted to +5 V, +3.3 V and other voltages for each unit by DC-DC power converter.
When the alarm box is in the duty room outside the equipment room, there may not be -48
V DC power, in this case, a external AC/DC power adapter is required to convert 110/220
V AC to 48 V DC, providing -48 V DC power to the alarm box. AC/DC power adaptor is an
optional accessory of the alarm box.
6.1.3 Panel
Figure 6-2 shows the appearance of alarm box.
Figure 6-2 ALB Appearance
Figure 6-3 shows the ALB panel.
6-4

Figure 6-3 ALB Panel
The left top of the panel is the indicator in arc shape and the LCD screen is located in the
center of the panel.
6.1.4 Interfaces
Figure 6-4 shows the interfaces of alarm box.
Figure 6-4 ALB Interfaces (on the Back)
1. Cable modem interface 5. MS antenna location 7. Power supply switch

2. Ethernet interface (connected with built-in
3. RS485 interface wireless modem)
4. RS232 serial port 6. Power supply interface
ZXG10 iBSC uses 2 to connect Hub and background EMS, 4 to download alarm box
versions, 6 to connect DC power supply, and 7 for power supply.
1. The alarm box comprises cover components, body components, PCB board,
apparatus, and assembly fasteners.
a. Cover components include LCD screen, buttons, indicators, and lamp plate.
b. Body components are the sheet-metal parts to mount the motherboard and
speakers.
c. PCB comprises motherboard, lamp plate, keyboard, and modem board.
6-5

d. Apparatus contains LCD screen, indicators, buttons, switches, RJ11, RJ45, DB9,
earphone hole, mobile antenna, GPS interface, 48V socket, and speakers.
e. Alarm box is locked.
f. The outline dimensions of an alarm box is: 220 mm x 310 mm x 58 mm (H x W x
D)
The relevant interfaces on the alarm box board are described in Table 6-1
Table 6-1 Relevant interfaces on ALB board
Location Interface Description
This interface connects the Ethernet receiver in 10 Mbps, com-

municates with foreground and background via TCP/IP, and re-
ceives the alarm information while the master unit is working in
Ethernet interface Ethernet mode.
This interface provides the standard EIA/TIA232-C interface,

communicates with foreground and background, and receives
the system alarm information while the master unit is working in
RS232 serial port UART mode.
This interface provides the external RS485 busbar,

communicates with foreground and background, and receives
the system alarm information while the master unit is working
in UART mode.
Another function of RS485 interface is to cascade the alarm
boxes, implements remote function, and transfers the alarm
information received in local alarm box to the next alarm box
via RS485 interface (currently, ZXG10 iBSC does not use this
RS485 interface interface).
This interface communicates with radio modem module via

RS232 serial port and implements the radio transmission of
alarm information while the master unit is working in UART
mode.
The working mode of radio MODEM module is GSM or CDMA.
Its transmission performance shall be compliant with the
Radio modem in- specification requirements (currently, ZXG10 iBSC does not
terface use this interface).
The parallel bus of the master unit attaches cable MODEM chip,
to provide the external cable modem interface and to implement
Cable modem in- the cable transmission of alarm information (currently, ZXG10
Box back terface iBSC does not use this interface).
6-6

Location Interface Description
This interface communicates with GPS receiver via RS233 se-

rial port, receives the GPS signal, and provides the accurate ab-
GPS interface solute time and stable clock reference for synchronization while
(RS232 serial the master unit is working in UART mode (currently, ZXG10
port) iBSC does not use this interface).
6.1.5 Buttons
Table 6-2 shows the buttons on ALB panel.
Table 6-2 ALB Panel Buttons
Name Description
M To select the menu
→ To move the cursor left when inputting the number.
← To move the cursor right when inputting the number.
↑ To select the menu, page up, or add 1 for the number
↓ To select the menu, page up, or reduce 1 for the number
C To return to the menu or to clear the input
OK To confirm the operation
RST To reset the ALB system
MUTE To mute/de-mute ALB
6.1.6 Indicators
Table 6-3 explains the ALB indicators.
Table 6-3 Description of ALB Indicators
Level-1 alarm in-

EMERGENCY Red dicator ON: indicates that the level-1 alarm exists.
Level-2 alarm in-

IMPORTANT Blue dicator ON: indicates that the level-2 alarm exists.
Level-3 alarm in-

COMMON Yellow dicator ON: indicates that the level-3 alarm exists.
Level 4 alarm in-

NOTIFICATION Green dicator ON: indicates that the level-4 alarm exists.
6-7

Bell on/off state

MUTE Green indicator ON: indicates that the trumpet is turned off.
ON: indicates that the network is connected.

Network connec- Flashing: indicates that the Ethernet link is
LINK Green tion indicator normal.
Program running Flashing in 1 Hz: indicates that the ALB is run-

RUN Green indicator ning normally.
6.1.7 Connection Mode

ALB includes the following connection modes: basic connection mode and expansion
connection mode.
1. Basic connection mode
Figure 6-5 shows the ALB basic connection mode.
Figure 6-5 Basic connection mode of ALB
2. Expansion connection mode

If the server’s IP address and ALB’s IP address are in the same network segment, the
server is called near-end server. If the server’s IP address and ALB’s IP address are
in different network segments, the server is called remote server.
ALB can be connected with the near-end server as well as the remote server. When
ALB is connected with the remote server, relevant route must be added in ALB, and
on-site alarms are received through the data network. This connection mode is called
expansion connection mode.
Figure 6-6 shows the expansion connection mode of ALB when NetNumen M31 server
is located at iBSC.
6-8

Figure 6-6 Expansion connection mode of ALB
ALB expansion function enables ALB to be installed in remote areas and connected
to the remote server, and receives on-site alarms through the data network. One ALB
can simultaneously connect five background servers at most.
6.2 Relevant GPS Devices

Global Position System (GPS) provides the clock and frequency reference for ZXG10 iBSC
system. It also provides GPS satellite signal for the system to realize the Assisted Global
Position System (AGPS).
The GPS antenna feeder system can be realized by the following two solutions:
l Direct Feeder Cable

l Indoor Forwardnig Scheme
6.2.1 GPS Active Antenna and Lightning Protector/Frequency

Divider
In feeder cable direct-connection solution and indoor forwarding solution, both the GPS
active antenna and the lightning protector/frequency divider are used.
In feeder cable direct-connection solution, the GPS active antenna is used as outdoor
receiving antenna; while in indoor forwarding solution, the GPS active antenna is used as
indoor receiving antenna.
Function Description
The GPS antenna receives GPS satellite navigation and positioning signals, and
demodulates the frequency, clock signal, and AGPS information through GPS signal
receiver. The clock signal is sent to relevant units in ZXG10 iBSC system while the AGPS
information is sent to the processing unit.
6-9

The GPS antenna lightning protector/frequency divider uses dual-frequency-dividing

coaxial cable protector, which is installed at the connector between communication
equipment and coaxial cable, or at lightning protection devices between two
communication equipments. It effectively prevents damages due to temporary
over-voltage caused by lightning induction.
The GPS antenna lightning protector/frequency divider adopts the high-frequency filter
principle and performs three-level protection for the DC feed channel. The RF insertion
loss is small, the discharge current is large, and the measured limiting voltage is low. It is
an ideal protection device for various public antenna communication equipments.
Device Description
1. Figure 6-7 shows the active GPS antenna.
Figure 6-7 Active GPS Antenna
1. GPS antenna 4. Feeder Cable 7. Binding tape

2. Installation fixing board 5. Pole
3. Installation tube 6. Fixing component
2. Figure 6-8 shows the GPS antenna lightning protector/frequency divider.
6-10

Figure 6-8 GPS Antenna Lightning Protector/Frequency Divider
Wiring Description
Figure 6-9 shows connections between ICM, GPS active antenna, and GPS antenna
lightning protector/frequency divider (fixed on the cabinet top).
Figure 6-9 Connection of ICM, Active GPS Antenna, and Lightning Protector/Frequency
Divider
1. GPS antenna
2. GPS Antenna Lightning
Protector/Frequency
Divider
Technical Parameters
1. Table 6-4 shows the technical parameters of active GPS antenna.
Table 6-4 Technical Parameters of Active GPS antenna
Parameter Specification
Frequency range 1575±5 MHz
Gain 38±2 dBi
DC voltage 4.5 ~ 6 V
DC current <35 mA
Antenna interface N (F) type
6-11

2. Table 6-5 shows the technical parameters of GPS antenna lightning

protector/frequency divider.
Table 6-5 Technical parameters of GPS antenna lightning protector/frequency

divider
Frequency range 1500~1600 MHz
Characteristic impedance 50 ohms
Insertion loss ≤ 4 dB
Standing wave ratio (VSWR) ≤ 1.2
Rated current 10 KA (8/20 μs)
Water-proof grade IP65
The input is N-F while the two outputs are

Interface Type SMA-F
Installation Mode Installing through the hole
The cross-sectional area of the grounding cable

Grounding cable must be larger than 6 mm2.
6.2.2 GPS L1 Signal Transponder and GPS Antenna Feeder

Lightning Protector
In indoor forwarding solution, the GPS L1 signal transponder and the GPS antenna feeder
lightning protector are used.
GPS L1 Signal Transponder

The GPS L1 signal transponder consists of three parts: GPS L1 outdoor receiving antenna,
GPS L1 indoor transmitting antenna, and GPS L1 signal controller.
1. Table 6-6 describes technical parameters of the GPS L1 outdoor receiving antenna.
Table 6-6 Technical parameters of GPS L1 outdoor receiving antenna
Frequency range 1575.42 MHz ± 10 MHz
Standing wave ratio (VSWR) less than 1.5
Gain 45 dB ± 2 dB
Polarization mode Clockwise circular polarization
Working temperature -45℃ ~ +65℃
Storage temperature -55℃ ~ +85℃
6-12

Connectors TNC
Cable length 100 m ± 0.2 m
2. Table 6-7 describes technical parameters of the GPS L1 indoor transmitting antenna.
Table 6-7 Technical parameters of GPS L1 outdoor transmitting antenna
Frequency range 1575 MHz±10 MHz
Gain 26 dB ± 2 dB
Connectors TNC
Cable length 10 m
Signal coverage range ≥ 200 m2
3. Table 6-8 describes technical parameters of the GPS L1 signal controller.
Table 6-8 Technical parameters of GPS L1 signal controller
Frequency range 1575 MHz ± 10 MHz
Noise Coefficient ≤ 1.5 dB
Gain 2 dB ± 2 dB, 16 dB ± 2 dB, 26 dB ± 2 dB
Voltage 220 VAC
Current 80 mA
Connectors TNC
GPS Antenna Feeder Lightning Protector

Table 6-9 shows the technical parameters of GPS antenna feeder lightning protector.
6-13

Table 6-9 Technical parameters of GPS antenna feeder lightning protector
Frequency range 1500~1600 MHz
Insertion loss ≤ 0.2 dB
Max transmission power ≤ 50 W
DC voltage 5.5 V
Rated current 10 KA (8/20 μs)
Remained voltage 20 V
Water-proof grade IP65
Interface Type The input is N-F.
Installation Mode Installing through the wall; installing by the copper lug
The cross-sectional area of the grounding cable must be

Grounding cable larger than 6 mm2.
6-14

Chapter 7
System Configuration
Table of Contents
Overview ....................................................................................................................7-1
Resource Shelf...........................................................................................................7-1
GB Resource Shelf.....................................................................................................7-8
7.1 Overview
ZXG10 iBSC has multiple interfaces. There are several connection modes for each
interface. The user can select the interface connection on demands.
The section below describes the typical configurations based on BUSN and BGSN.
7.2 Resource Shelf

7.2.1 E1 at Abis and A Interfaces
Figure 7-1 shows the configuration of E1 at Abis and A interfaces.
7-1

Figure 7-1 E1 at Abis and A Interfaces for Resource Shelf
7.2.2 IP+E1 at Abis and E1 at A-Interface

Figure 7-2 shows the configuration of IP+E1 at Abis and E1 at A interface.
7-2

Chapter 7 System Configuration
Figure 7-2 IP+E1 at Abis and IP at A Interface for Resource Shelf
7.2.3 IP+E1 at Abis and STM-1 at A-Interface

Figure 7-3 shows the configuration of IP+E1 at Abis and STM-1 (active/standby) at A
interface.
7-3

Figure 7-3 IP+E1 at Abis and STM-1 at A interface for Resource Shelf
7.2.4 IPoE at Abis and E1 at A-Interface

Figure 7-4 shows the configuration of IPoE at Abis and E1 at A-interface.
7-4

Figure 7-4 IPoE at Abis and E1 at A-Interface for Resource Shelf
7.2.5 E1 at Abis and STM-1 at A Interface

Figure 7-5 shows the configuration of E1 at Abis and STM-1 (active/standby) at A interface.
7-5

Figure 7-5 E1 at Abis and STM-1 at A interface for Resource Shelf
7.2.6 E1 at Abis and E1 (Outer TC) at Ater

Figure 7-6 shows the configuration of E1 at Abis and E1 (outer TC) at Ater.
7-6

Figure 7-6 E1 at Abis and E1 (Outer TC) at Ater interface for Resource Shelf
7.2.7 E1 at Abis and STM-1 (Outer TC) at Ater

Figure 7-7 shows the configuration of E1 at Abis and STM-1 (outer TC) at Ater.
7-7

Figure 7-7 E1 at Abis and STM-1 (Outer TC) at Ater interface for Resource Shelf
7.3 GB Resource Shelf

7.3.1 E1 (T1) used at Abis and A Interfaces
Figure 7-8 shows the configuration of E1 (T1) at Abis and A interfaces.
7-8

Figure 7-8 E1 at Abis and A Interfaces for GB Resource Shelf
7.3.2 E1 at Abis and STM-1 at A Interface

Figure 7-9 shows the configuration of E1 at Abis and STM-1 at A interface.
7-9

Figure 7-9 E1 at Abis and STM-1 at A interface for GB Resource Shelf
7.3.3 E1 at Abis and IP at A-Interface

Figure 7-10 shows the configuration of E1 at Abis and IP at A interface.
7-10

Figure 7-10 E1 at Abis and IP at A interface for GB Resource Shelf
7.3.4 IP at Abis and A Interfaces

Figure 7-11 shows the configuration of IP at Abis and A interfaces.
7-11

Figure 7-11 IP at Abis and A Interfaces for GB Resource Shelf
7.3.5 IP at Abis and E1 (T1) at A-Interface

Figure 7-12 shows the configuration of IP at Abis and E1 (T1) at A-interface.
7-12

Figure 7-12 IP at Abis and E1 (T1) at A-interface for GB Resource Shelf
7.3.6 IP at Abis and STM-1 at A-Interface

Figure 7-13 shows the configuration of IP at Abis and STM-1 at A-interface.
7-13

Figure 7-13 IP at Abis and STM-1 at A-interface for GB Resource Shelf
7.3.7 IPoE at Abis and E1 (T1) at A-Interface

Figure 7-14 shows the configuration of IPoE at Abis and E1 (T1) at A-interface.
7-14

Figure 7-14 IPoE at Abis and E1 (T1) at A-interface for GB Resource Shelf
7.3.8 IPoE at Abis and STM-1 at A-Interface

Figure 7-15 shows the configuration of IPoE at Abis and STM-1 at A-interface.
7-15

Figure 7-15 IPoE at Abis and STM-1 at A-interface for GB Resource Shelf
7.3.9 IPoE at Abis and IP at A Interface

Figure 7-16 shows the configuration of IPoE at Abis and IP at A interface.
7-16

Figure 7-16 IPoE at Abis and IP at A interface for GB Resource Shelf
7.3.10 E1 (T1) at Abis and Ater Interfaces

Figure 7-17 shows the configuration of E1 (T1) at Abis and Ater interfaces.
7-17

Figure 7-17 E1 (T1) at Abis and Ater for GB Resource Shelf
7.3.11 IP at Abis and E1 (T1) at Ater

Figure 7-18 shows the configuration of IP at Abis and E1 (T1) at Ater.
7-18

Figure 7-18 IP at Abis and E1 (T1) at Ater for GB Resource Shelf
7-19

7-20

Appendix A
Explanation of Combined
Indicator States
The board in the iBSC system indicates the different states through combination of RUN
and ALM indicators. For specific meaning about combination of RUN and ALM indicators,
refers to Table A-1.
Table A-1 Combination Meanings of RUN and ALM Indicators
State name RUN status Alarm status Meaning
Periodically flashing
Running normally at 1 Hz Always OFF Normal running
at 5 Hz Always OFF Version being downloaded
Version download fails: the

Periodically flashing Periodically flashing board version is inconsistent with
at 1 Hz at 5 Hz the configuration.
RELEASE version indicates that

VERSION Down- the version download succeeds
loading Always ON Always OFF and the version is being started.
Always OFF at 5 Hz Board self-test failure.
Periodically flashing Operation support system

Self-test fails Always OFF at 2 Hz startup failure.
Periodically flashing Periodically flashing

at 5 Hz at 5 Hz Logical address obtaining failure.
Periodically flashing Periodically flashing Basic process power-on failure

at 5 Hz at 2 Hz or timeout.

at 5 Hz at 1 Hz Core data area initialization.
Periodically flashing Periodically flashing Version and hardware are incon-

at 5 Hz at 0.5 Hz sistent with the configuration.
Alarm on running Periodically flashing Periodically flashing Media plane communication is

faults at 2 Hz at 5 Hz disconnected.
A-1

State name RUN status Alarm status Meaning

at 2 Hz at 2 Hz HW is disconnected.

at 1 Hz at 2 Hz Link break with OMP.
Periodically flashing Periodically flashing Active/standby changeover is be-

at 1 Hz at 1 Hz ing performed.
at 1 Hz Always ON Hardware clock is lost.
A-2

Figures
Figure 2-1 ZXG10 iBSC Cabinet Appearance ........................................................... 2-1
Figure 2-2 Cabinet Components ............................................................................... 2-2
Figure 2-3 Appearance of Cabinet Top...................................................................... 2-3
Figure 2-4 Structure of Cabinet Top .......................................................................... 2-3
Figure 2-5 Structure of Top Frame Component ......................................................... 2-4
Figure 2-6 Structure of Outlet Module ....................................................................... 2-5
Figure 2-7 Structure of Top Fan ................................................................................ 2-5
Figure 2-8 Top Filter.................................................................................................. 2-6
Figure 2-9 Structure of Fiber Wrap Tray .................................................................... 2-7
Figure 2-10 Office Information Label and Serial No. Label ........................................ 2-7
Figure 2-11 Rack Structure ....................................................................................... 2-8
Figure 2-12 Busbar ................................................................................................... 2-9
Figure 2-13 Cabinet Layout..................................................................................... 2-11
Figure 2-14 Connection of iBSC and Peripheral Device for GB Resource
Shelf ..................................................................................................... 2-12
Figure 2-15 Connection of iBSC and Peripheral Device for Resource Shelf ............ 2-13
Figure 2-16 Cabinet Cabling (Left View).................................................................. 2-15
Figure 2-17 Heat Dissipation Duct of ZXG10 iBSC.................................................. 2-18
Figure 3-1 Structure of Power Distribution Subrack................................................... 3-1
Figure 3-2 Front Panel of Power Subrack ................................................................. 3-2
Figure 3-3 Rear Panel of Power Subrack .................................................................. 3-2
Figure 3-4 Structure of Fan Subrack ......................................................................... 3-4
Figure 3-5 Front Panel of Fan Subrack ..................................................................... 3-4
Figure 3-6 Rear Panel of Fan Subrack...................................................................... 3-5
Figure 4-1 Positions of Different Shelves for the GB Resource Shelf......................... 4-2
Figure 4-2 Positions of Different Shelves for the Resource Shelf............................... 4-2
Figure 4-3 Backplane Structure................................................................................. 4-3
Figure 4-4 Configuration of Control Shelf .................................................................. 4-4
Figure 4-5 Principle of Control Shelf.......................................................................... 4-6
Figure 4-6 Rear Viw of BCTC Backplane with Version 040203.................................. 4-7
Figure 4-7 Rear Viw of BCTC Backplane with Version 060201.................................. 4-8
Figure 4-8 Layout of DIP Switch on RBID ................................................................. 4-9
I
Figure 4-9 Configuration of Packet Switching Shelf................................................. 4-11

Figure 4-10 Principle of Packet Switching Shelf ...................................................... 4-12
Figure 4-11 Rear Viw of BPSN Backplane with Version 040203 .............................. 4-13
Figure 4-12 Rear Viw of BPSN Backplane with Version 070200.............................. 4-14
Figure 4-13 Configuration of Resource Shelf .......................................................... 4-16
Figure 4-14 Principle of Resource Shelf .................................................................. 4-17
Figure 4-15 Rear Viw of BUSN Backplane with Version 040202.............................. 4-18
Figure 4-16 Rear View of BUSN Backplane with Version 040203............................ 4-18
Figure 4-17 Configuration of Control Shelf .............................................................. 4-20
Figure 4-18 Principle of Control Shelf...................................................................... 4-22
Figure 4-19 Rear View of BCTC Backplane ............................................................ 4-23
Figure 4-20 Layout of DIP Switch on RBID ............................................................. 4-24
Figure 4-21 Configuration of Packet Switching Shelf............................................... 4-26
Figure 4-22 Principle of Packet Switching Shelf ...................................................... 4-27
Figure 4-23 Rear View of BPSN Backplane ............................................................ 4-28
Figure 4-24 Configuration of GB Resource Shelf .................................................... 4-30
Figure 4-25 Principle of GB Resource Shelf ............................................................ 4-31
Figure 4-26 Rear View of BGSN Backplane ............................................................ 4-32
Resource Shelf ..................................................................................... 4-34
Figure 4-28 Ethernet Connection at Control Plane in an iBSC Cabinet for Resource
Shelf ..................................................................................................... 4-35
Figure 4-29 Wiring at User Plane in an iBSC Cabinet for Resource Shelf................ 4-36
Figure 4-30 Wiring of Monitoring Cables in an iBSC Cabinet for Resource
Shelf ..................................................................................................... 4-37
Figure 4-31 Wiring of Clock Extraction Distribution In the iBSC Dual-Cabinet for
Resource Shelf ..................................................................................... 4-38
Figure 4-32 Ethernet Connection at Control Plane in the iBSC Dual-Cabinet for
Resource Shelf ..................................................................................... 4-39
Figure 4-33 Wiring at User Plane in the iBSC Dual-Cabinet for Resource
Shelf ..................................................................................................... 4-39
Figure 4-34 Wiring of Monitoring Cables in the iBSC Dual-Cabinet for Resource
Shelf ..................................................................................................... 4-40
Figure 4-35 Wiring of Clock Extraction Distribution In an iBSC Cabinet for GB
Resource Shelf ..................................................................................... 4-41
Figure 4-36 Ethernet Connection at Control Plane in an iBSC Cabinet for GB
Resource Shelf ..................................................................................... 4-42
II
Figures
Figure 4-37 Wiring at User Plane in an iBSC Cabinet for GB Resource Shelf ........... 4-43
Figure 4-38 Wiring of Monitoring Cables in an iBSC Cabinet for GB Resource
Shelf ..................................................................................................... 4-44
Figure 4-39 Wiring of Clock Extraction Distribution In the iBSC Dual-Cabinet for
GB Resource Shelf ............................................................................... 4-45
Figure 4-40 Ethernet Connection at Control Plane in the iBSC Dual-Cabinet for
GB Resource Shelf ............................................................................... 4-46
Figure 4-41 Wiring at User Plane in the iBSC Dual-Cabinet for GB Resource
Shelf ..................................................................................................... 4-46
Figure 4-42 Wiring of Monitoring Cables in the iBSC Dual-Cabinet for GB
Resource Shelf ..................................................................................... 4-47
Figure 5-1 Board Assembly....................................................................................... 5-2
Figure 5-2 Principle of BIPI Board............................................................................. 5-3
Figure 5-3 BIPI Board ............................................................................................... 5-4
Figure 5-4 Principle of CHUB Board.......................................................................... 5-7
Figure 5-5 CHUB Board............................................................................................ 5-8
Figure 5-6 Principle of CLKG (CLKG) board ........................................................... 5-11
Figure 5-7 CLKG (CLKG) Board ............................................................................. 5-12
Figure 5-8 Principle of CLKG (ICM) Board .............................................................. 5-20
Figure 5-9 CLKG (ICM) Board ................................................................................ 5-21
Figure 5-10 Principle of CMP Board........................................................................ 5-28
Figure 5-11 CMP Board .......................................................................................... 5-29
Figure 5-12 DTB Principle....................................................................................... 5-32
Figure 5-13 DTB Board........................................................................................... 5-33
Figure 5-14 Layout of DTB board for front board (version 060201).......................... 5-33
Figure 5-15 Jumpers on RDTB board ..................................................................... 5-36
Figure 5-16 Principle of EIPI Board ......................................................................... 5-38
Figure 5-17 EIPI Board ........................................................................................... 5-39
Figure 5-18 Principle of GLI Board .......................................................................... 5-41
Figure 5-19 GLI Panel............................................................................................. 5-42
Figure 5-20 GLI4 Panel........................................................................................... 5-45
Figure 5-21 Principle of GIPI board ......................................................................... 5-48
Figure 5-22 GIPI Board........................................................................................... 5-49
Figure 5-23 GUIM Principle..................................................................................... 5-52
Figure 5-24 GUIM Board......................................................................................... 5-53
Figure 5-25 GUIM2 Board....................................................................................... 5-58
Figure 5-26 Principle of GUP board ........................................................................ 5-61
III
Figure 5-27 GUP Panel........................................................................................... 5-63

Figure 5-28 Principle of GUP2 board ...................................................................... 5-65
Figure 5-29 GUP2 Panel......................................................................................... 5-67
Figure 5-30 Principle of ICM Board ......................................................................... 5-69
Figure 5-31 ICM board............................................................................................ 5-70
Figure 5-32 OMP Board.......................................................................................... 5-78
Figure 5-33 Principle of PSN Board ........................................................................ 5-81
Figure 5-34 PSN Panel ........................................................................................... 5-82
Figure 5-35 General Structure of PWRD Board....................................................... 5-84
Figure 5-36 PWRD Board ....................................................................................... 5-85
Figure 5-37 Jumpers............................................................................................... 5-86
Figure 5-38 Principle of SBCX Board ...................................................................... 5-87
Figure 5-39 SBCX Board ........................................................................................ 5-88
Figure 5-40 Principle of SDTB Board ...................................................................... 5-92
Figure 5-41 SDTB Panel......................................................................................... 5-93
Figure 5-42 Principle of SDTB2 Board .................................................................... 5-96
Figure 5-43 SDTB2 Panel ....................................................................................... 5-97
Figure 5-44 Principle of SPB Board....................................................................... 5-100
Figure 5-45 SPB Board......................................................................................... 5-101
Figure 5-46 Positions of RSPB Jumpers ............................................................... 5-104
Figure 5-47 SPB2 Principle................................................................................... 5-106
Figure 5-48 SPB2 Board....................................................................................... 5-107
Figure 5-49 UIMC Principle................................................................................... 5-110
Figure 5-50 UIMC Board ........................................................................................5-111
Figure 5-51 UIMU Principle................................................................................... 5-114
Figure 5-52 UIMU Board ....................................................................................... 5-115
Figure 5-53 UPPB Principle .................................................................................. 5-118
Figure 5-54 UPPB Panel....................................................................................... 5-120
Figure 6-1 ALB Principle ........................................................................................... 6-2
Figure 6-2 ALB Appearance...................................................................................... 6-4
Figure 6-3 ALB Panel................................................................................................ 6-5
Figure 6-4 ALB Interfaces (on the Back) ................................................................... 6-5
Figure 6-5 Basic connection mode of ALB ................................................................ 6-8
Figure 6-6 Expansion connection mode of ALB......................................................... 6-9
Figure 6-7 Active GPS Antenna .............................................................................. 6-10
IV
Figures
Figure 6-8 GPS Antenna Lightning Protector/Frequency Divider ............................. 6-11

Figure 6-9 Connection of ICM, Active GPS Antenna, and Lightning
Protector/Frequency Divider ................................................................. 6-11
Figure 7-1 E1 at Abis and A Interfaces for Resource Shelf........................................ 7-2
Figure 7-2 IP+E1 at Abis and IP at A Interface for Resource Shelf ............................ 7-3
Figure 7-3 IP+E1 at Abis and STM-1 at A interface for Resource Shelf ..................... 7-4
Figure 7-4 IPoE at Abis and E1 at A-Interface for Resource Shelf............................. 7-5
Figure 7-5 E1 at Abis and STM-1 at A interface for Resource Shelf .......................... 7-6
Figure 7-6 E1 at Abis and E1 (Outer TC) at Ater interface for Resource Shelf ........... 7-7
Figure 7-7 E1 at Abis and STM-1 (Outer TC) at Ater interface for Resource
Shelf ....................................................................................................... 7-8
Figure 7-8 E1 at Abis and A Interfaces for GB Resource Shelf.................................. 7-9
Figure 7-9 E1 at Abis and STM-1 at A interface for GB Resource Shelf .................. 7-10
Figure 7-10 E1 at Abis and IP at A interface for GB Resource Shelf ....................... 7-11
Figure 7-11 IP at Abis and A Interfaces for GB Resource Shelf ............................... 7-12
Figure 7-12 IP at Abis and E1 (T1) at A-interface for GB Resource Shelf ................ 7-13
Figure 7-13 IP at Abis and STM-1 at A-interface for GB Resource Shelf ................. 7-14
Figure 7-14 IPoE at Abis and E1 (T1) at A-interface for GB Resource Shelf............ 7-15
Figure 7-15 IPoE at Abis and STM-1 at A-interface for GB Resource Shelf............. 7-16
Figure 7-16 IPoE at Abis and IP at A interface for GB Resource Shelf .................... 7-17
Figure 7-17 E1 (T1) at Abis and Ater for GB Resource Shelf................................... 7-18
Figure 7-18 IP at Abis and E1 (T1) at Ater for GB Resource Shelf .......................... 7-19
V
Figures

Tables
Table 1-1 Hardware Architecture Description ............................................................ 1-1
Table 3-1 Indicators on Panel of Power Distribution Subrack..................................... 3-2
Table 3-2 Switches on Panel of Power Distribution Subrack..................................... 3-3
Table 3-3 Interfaces of Power Distribution Subrack ................................................... 3-3
Table 3-4 Indicators on the Panel of Fan Subrack ..................................................... 3-5
Table 3-5 Interfaces of Fan Subrack.......................................................................... 3-5
Table 4-1 Shelf Description ....................................................................................... 4-1
Table 4-2 Relationship Between Shelf and Backplane............................................... 4-3
Table 4-3 The boards that can be configured by the control shelf .............................. 4-4
Table 4-4 Description of Power Interfaces for Control Shelf....................................... 4-9
Table 4-5 Description of DIP Switches for the Backplane ........................................ 4-10
Table 4-6 Boards That can be Configured in Packet Switching Shelf....................... 4-11
Table 4-7 Description of Power Interfaces for Packet Switching Shelf ..................... 4-14
Table 4-8 The boards that can be configured by the resource shelf......................... 4-15
Table 4-9 Description of Power Interfaces for Resource Shelf ................................. 4-19
Table 4-10 The boards that can be configured by the control shelf .......................... 4-20
Table 4-11 Description of Power Interfaces for Control Shelf ................................... 4-24
Table 4-12 Description of DIP Switches for the Backplane ...................................... 4-25
Table 4-13 The Boards That can be Configured by Packet Switching Shelf............. 4-26
Table 4-14 Description of Power Interfaces for Packet Switching Shelf ................... 4-28
Table 4-15 The boards that can be configured by the GB resource shelf ................. 4-29
Table 4-16 Description of Power Interfaces for GB Resource Shelf ......................... 4-32
Table 5-1 Relevant Interfaces on BIPI Board............................................................. 5-5
Table 5-2 BIPI Panel Buttons .................................................................................... 5-5
Table 5-3 BIPI Panel Indicators ................................................................................. 5-5
Table 5-4 Relevant Interfaces on CHUB Board ......................................................... 5-9
Table 5-5 CHUB Panel Buttons ............................................................................... 5-10
Table 5-6 CHUB Panel Indicators............................................................................ 5-10
Table 5-7 Relevant interfaces on CLKG (CLKG) board............................................ 5-13
Table 5-8 CLKG (CLKG) Panel Buttons .................................................................. 5-16
Table 5-9 CLKG (CLKG) Panel Indicators ............................................................... 5-16
Table 5-10 CLKG (CLKG) Jumpers ......................................................................... 5-18
VII
Table 5-11 Relevant interfaces on CLKG (ICM) board ............................................. 5-21

Table 5-12 CLKG (ICM) Panel Buttons.................................................................... 5-24
Table 5-13 CLKG (ICM) Panel Indicators ................................................................ 5-25
Table 5-14 CLKG (ICM) DIP Switches..................................................................... 5-27
Table 5-15 Relevant interfaces on CMP board ........................................................ 5-29
Table 5-16 CMP Panel Buttons ............................................................................... 5-29
Table 5-17 CMP Panel Indicators............................................................................ 5-30
Table 5-18 Relevant interfaces on DTB board ......................................................... 5-34
Table 5-19 DTB Panel Buttons ................................................................................ 5-34
Table 5-20 DTB Panel Indicators............................................................................. 5-34
Table 5-21 X9-X16 Connection Mode...................................................................... 5-36
Table 5-22 DIP Switches on DTB Board.................................................................. 5-37
Table 5-23 EIPI Panel Buttons ................................................................................ 5-39
Table 5-24 EIPI Panel Indicators ............................................................................. 5-40
Table 5-25 Relevant Interfaces on GLI Board.......................................................... 5-42
Table 5-26 GLI Panel Buttons ................................................................................. 5-43
Table 5-27 GLI Panel Indicators .............................................................................. 5-43
Table 5-28 Relevant Interfaces on GLI4 Board........................................................ 5-46
Table 5-29 GLI4 Panel Buttons ............................................................................... 5-46
Table 5-30 GLI4 Panel Indicators ............................................................................ 5-46
Table 5-31 Relevant Interfaces on GIPI Board ........................................................ 5-50
Table 5-32 GIPI Panel Buttons ................................................................................ 5-50
Table 5-33 GIPI Panel Indicators............................................................................. 5-50
Table 5-34 Relevant interfaces on GUIM board....................................................... 5-54
Table 5-35 GUIM Panel Buttons.............................................................................. 5-55
Table 5-36 GUIM Board Indicators .......................................................................... 5-55
Table 5-37 Relevant interfaces on GUIM2 board ..................................................... 5-59
Table 5-38 GUIM2 Panel Buttons............................................................................ 5-59
Table 5-39 GUIM2 Board Indicators ........................................................................ 5-59
Table 5-40 GUP Panel Buttons ............................................................................... 5-63
Table 5-41 GUP Panel Indicators ............................................................................ 5-64
Table 5-42 GUP2 Panel Buttons ............................................................................. 5-67
Table 5-43 GUP2 Panel Indicators .......................................................................... 5-68
Table 5-44 Relevant Interfaces on ICM Board ......................................................... 5-71
Table 5-45 ICM Panel Buttons ................................................................................ 5-73
VIII
Tables
Table 5-46 ICM Panel Indicators ............................................................................. 5-74

Table 5-47 ICM DIP Switches ................................................................................. 5-77
Table 5-48 Relevant interfaces on OMP board ........................................................ 5-78
Table 5-49 OMP Panel Buttons ............................................................................... 5-79
Table 5-50 OMP Board Indicators ........................................................................... 5-79
Table 5-51 PSN Panel Buttons................................................................................ 5-83
Table 5-52 PSN Panel Indicators ............................................................................ 5-83
Table 5-53 PWRD DIP Switches ............................................................................. 5-85
Table 5-54 Relevant SBCX Interfaces ..................................................................... 5-89
Table 5-55 SBCX Panel Buttons ............................................................................. 5-90
Table 5-56 SBCX Panel Indicators .......................................................................... 5-90
Table 5-57 Relevant interfaces on SDTB board....................................................... 5-94
Table 5-58 SDTB Panel Buttons.............................................................................. 5-94
Table 5-59 SDTB Panel Indicators .......................................................................... 5-94
Table 5-60 Relevant interfaces on SDTB2 board..................................................... 5-98
Table 5-61 SDTB2 Panel Buttons............................................................................ 5-98
Table 5-62 SDTB2 Panel Indicators ........................................................................ 5-98
Table 5-63 Relevant interfaces on SPB board ....................................................... 5-101
Table 5-64 SPB Panel Buttons .............................................................................. 5-102
Table 5-65 SPB Panel Indicators........................................................................... 5-102
Table 5-66 Description of SPB DIP Switches ........................................................ 5-103
Table 5-67 RSPB Jumper Settings ........................................................................ 5-104
Table 5-68 Relevant interfaces on SPB2 board ..................................................... 5-107
Table 5-69 SPB2 Panel Buttons ............................................................................ 5-108
Table 5-70 SPB2 Panel Indicators......................................................................... 5-108
Table 5-71 Relevant interfaces on UIMC board ......................................................5-111
Table 5-72 UIMC Panel Buttons ............................................................................ 5-112
Table 5-73 UIMC Board Indicators ........................................................................ 5-112
Table 5-74 Relevant interfaces on UIMU board ..................................................... 5-115
Table 5-75 UIMU Panel Buttons ............................................................................ 5-116
Table 5-76 UIMU Board Indicators ........................................................................ 5-116
Table 5-77 UPPB Panel buttons............................................................................ 5-121
Table 5-78 UPPB Panel Indicators ........................................................................ 5-121
Table 6-1 Relevant interfaces on ALB board ............................................................. 6-6
Table 6-2 ALB Panel Buttons .................................................................................... 6-7
IX
Table 6-3 Description of ALB Indicators .................................................................... 6-7

Table 6-4 Technical Parameters of Active GPS antenna.......................................... 6-11
Table 6-5 Technical parameters of GPS antenna lightning protector/frequency
divider .................................................................................................... 6-12
Table 6-6 Technical parameters of GPS L1 outdoor receiving antenna.................... 6-12
Table 6-7 Technical parameters of GPS L1 outdoor transmitting antenna................ 6-13
Table 6-8 Technical parameters of GPS L1 signal controller.................................... 6-13
Table 6-9 Technical parameters of GPS antenna feeder lightning protector............. 6-14
Table A-1 Combination Meanings of RUN and ALM Indicators..................................A-1
X
Glossary
APS
- Automatic Protection Switching
Abis
- Abis Interface between BSC and BTS
BCTC
- Backplane of ConTrol Center
BGSN
- Backplane of Giga universal Service Network
BPSN
- Backplane of Packet Switch Network
BSSAP
- Base Station System Application Part
BSSGP
- Base Station System GPRS Protocol
BTS
- Base Transceiver Station
BUSN
- Backplane Of Universal Service Network
CAS
- Channel Associated Signaling
CCS
- Common Channel Signaling
CHUB
- Control plane HUB
CLKG
- CLOCK Generator
CMP
- Calling Main Processor
CS
- Circuit Switched
DTB
- Digital Trunk Board
FE
- Fast Ethernet
XI
GE
- Gigabit Ethernet
GLI
- Gigabit Line Interface
GLI4
- Gigabit Line Interface 4
GPRS
- General Packet Radio Service
GPS
- Global Positioning System
GUIM
- Gigabit Universal Interface Module
GUIM2
- GE Universal Interface Module 2
GUP
- Generic User Profile
ICM
- Integrated Clock Module
IP
- Internet Protocol
MGW
- Media GateWay
MSC
- Mobile Switching Center
OMM
- Operation & Maintenance Module
OMP
- Operation Main Processor
PCU
- Packet Control Unit
PS
- Packet Switched
PSN
- Packet Switched Network
PWRD
- PoWeR Distributor
QoS
- Quality of Service
XII
Glossary
RCHB1
- Rear Board 1 of CHUB
RCHB2
- Rear Board 2 of CHUB
RCKG1
- Rear Board 1 of CLKG
RCKG2
- Rear Board 2 of CLKG
RDTB
- Rear Board of DTB
RGER
- Rear Giga Ethernet Board of Resource
RGIM1
- General Rear Interface Module 1
RMNIC
- Rear Board of MNIC
RMPB
- Rear Board of MP
RSPB
- Rear Board of SPB
RSVB
- Rearcard of SerVe Board
RTP
- Real-time Transport Protocol
RUIM2
- Rear board of UIM (type2)
RUIM3
- Rear board of UIM (type3)
SBCX
- X86 Single Board Computer
SDTB
- Sonet Digital Trunk Board
SGSN
- Service GPRS Supporting Node
SPB
- Signaling Processing Board
STM
- Synchronous Transfer Mode
XIII
TC
- TransCoder
TCU
- TransCoder Unit
UIMC
- Universal Interface Module for Control plane (BCTC or BPSN)
UIMU
- Universal Interface Module for User Plane
XIV

ZXG10 IBSC (V6.20.62) Hardware Description

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ZXG10 iBSC

Base Station Controller

Revision No. Revision Date Revision Reason

R1.0 2011-09-29 First edition

Serial Number: SJ-20110909163609-003

Publishing Date: 2011-09-29(R1.0)

Chapter 2 Cabinet....................................................................................... 2-1

Chapter 3 Subrack...................................................................................... 3-1

Chapter 4 Shelf ........................................................................................... 4-1

Chapter 5 Board.......................................................................................... 5-1

Chapter 6 Auxiliary Equipment ................................................................. 6-1

Chapter 7 System Configuration............................................................... 7-1

Appendix A Explanation of Combined Indicator States ........................ A-1

What is in This Manual

Chapter 1, Overview Describes the hardware structure of ZXG10 iBSC.

Chapter 2, Cabinet Describes the structure of ZXG10 iBSC cabinet.

1.1 Product Description

1.2 Hardware Architecture

Table 1-1 Hardware Architecture Description

Introduces the structure and composition of ZXG10 iBSC cabinet,

Introduces the function, structure and panel of ZXG10 iBSC sub-

Explains the configuration and backplane descriptions of shelves

Introduces the function, indicator, button, jumper and DIP Switch

SJ-20110909163609-003|2011-09-29(R1.0) ZTE Proprietary and Confidential

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2.1 Cabinet Appearance

Figure 2-1 ZXG10 iBSC Cabinet Appearance

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2.2 Cabinet Structure

Figure 2-2 Cabinet Components

1. Cover 5. Service subrack 9. Side door

2.2.1 Cabinet Top

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Figure 2-3 Appearance of Cabinet Top

Figure 2-4 Structure of Cabinet Top

1. Fiber wrap tray 4. Filter cover 7. Top frame component

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Top Frame Component

Figure 2-5 Structure of Top Frame Component

1. Base plate for outlet module 3. Grounding label 5. Installation base of

Cable Oulet Module

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Figure 2-6 Structure of Outlet Module

1. Outlet frame 2. Outlet bar

Figure 2-7 Structure of Top Fan

1. Monitor circuit board 2. Fan 3. Installation base

SJ-20110909163609-003|2011-09-29(R1.0) ZTE Proprietary and Confidential

Figure 2-8 Top Filter

1. Power input 2. Power output

Fiber Wrap Tray

SJ-20110909163609-003|2011-09-29(R1.0) ZTE Proprietary and Confidential

Figure 2-9 Structure of Fiber Wrap Tray

1. Cover 2. Fiber wrap post 3. Base plate

2.2.2 Front/Rear Door

Figure 2-10 Office Information Label and Serial No. Label

1. Office information label 2. Serial No. label

l Office information label

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Figure 2-11 Rack Structure

1. Top frame 2. Polar 3. Adjustment track

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4. Side door 5. Bottom frame

Figure 2-12 Busbar

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