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Design of static and dynamic RAM arrays using a novel reversible logic gate and
decoder
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Abstract—Reversible logic is an emerging nanotechnology implemented in the design of a 4x2 reversible SRAM array.
used in the design and implementation of nanotechnology and A dual-port SRAM cell is designed using these proposed
quantum computing with the main goal of reducing physical reversible logic structures, and its implementation in a
entropy gain. Significant work have been produced in the synchronous n-bit reversible dual-port SRAM array is
design of fundamental reversible logic structures and presented. In Section VII, a DRAM cell designed using
arithmetic units, and recent developments in sequential design reversible elements is presented and verified. The DRAM
of reversible circuits has opened new avenues in the
cell and corresponding control logic is implemented in a
implementation of reversible combinational circuits, such as
the design and implementation of static (SRAM) and dynamic reversible 4x4 DRAM array.
random-access memory (DRAM). In this paper, a novel 4*4
MLMR gate is presented which is used for controlling the
read/write logic of a SRAM cell. Next, a reversible SRAM cell is II. REVERSIBLE LOGIC
designed and verified. Then, a novel 4*4 Reversible Decoder
(RD) gate, implemented as a 2-to-4 decoder with low delay and A. Reversible Design Goals
cost is presented and verified, and its implementation shown in Any reversible logic design must meet three
the construction of a 4x2 reversible SRAM array. Next, a dual- fundamental criteria. Since there must be an equal number of
port SRAM cell is presented and verified, and its
inputs and outputs, reduction of the ancillary inputs and
implementation in a synchronous n-bit reversible dual-port
SRAM array is shown. Then, a reversible DRAM cell is garbage outputs will improve the design space require to
presented and verified. The control logic for writing to the implement the logic. Second, the number of 1*1 and 2*2
DRAM based on Peres gates is shown. The control logic and the reversible calculations necessary to generate the logical
DRAM cell are then implemented in a reversible 4x4 DRAM output – defined as the quantum cost of the reversible circuit
array. - [6] should be minimized. Third, throughput must be
increased by reduction of the logical depth of the device –
Index Terms – Central Processing Unit; DRAM; Emerging
Technologies; Instruction Set Architecture; Low Power;
defined as the quantum delay [7].
Memory; Nanotechnology; Reversible Logic; SRAM; Quantum B. Fundamental Logic Gates
Computing
The fundamental 2*2 reversible-logic gate was
proposed by Feynman in [8]. The output states relate to the
I. INTRODUCTION input states in the following manner: and .
Since reversible logic structures require an identical number
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Fig. 5: Quantum Representation of RD gate
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configuration is shown in Fig. 10 below. The reversible VIII. CONCLUSION
DRAM has a quantum cost of 8 and a worst-case delay of 8.
Two novel 4*4 reversible logic gates were presented,
The reversible DRAM cell in Fig. 10 and control logic
verified and their advantages demonstrated. The MLMRG
utilizing modified Peres gates were used in the
was implemented as the control for the read/write logic in an
implementation of a 4x4 reversible DRAM array. The design
SRAM cell. The RD was implemented as a reversible
also used two RD gates which served as 2-to-4 decoders for
decoder in an SRAM array. A SRAM cell implemented with
the row select and column select signals. The write signal is
these reversible elements was presented and verified, and
passed through a Peres control gate (PCG) structure
then implemented in the design of a 4x2 reversible SRAM
consisting of two Peres gates. The logical configuration of
array. A dual-port SRAM cell was designed using these
the reversible 4x4 DRAM is shown in Fig. 20. The quantum
proposed reversible logic structures, and its implementation
cost of the device is 414, and the worst-case delay is 39. The
in a synchronous n-bit reversible dual-port SRAM array is
design for the SRAM Array was verified and simulated
presented. A DRAM cell designed using reversible elements
using VHDL in Xilinx 12.4.
was presented, verified and implemented in a reversible 4x4
DRAM array.
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