Department of Electronic and Telecommunication Engineering

University of Moratuwa
EN201 - Principles of Electronics1

Part 1 - LOGIC FAMILIES

The IC and the digital logic families are introduced in this section. This section presents the electronic circuits in each IC digital
logic family and analyzes their electrical operation. A basic knowledge of electrical circuits is assumed.

Contents

1 Introduction 2

2 Special Characteristics 3
2.1 Fan-In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 Fan-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.3 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.4 Rise Time/Fall Time and Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4.1 Gate Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4.2 Wire Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4.3 Rise/Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.5 Noise Margin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Device Specific Characteristics 6

3.1 Switching Speeds of Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Switching Speed of Bipolar Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.1 Operation of the BJT Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2.2 Operation of the Schottky transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3 Clock Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4 Diode Logic 9
4.1 DL OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2 DL AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.3 Issues Related to DL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5 Resistor Transistor Logic (RTL) 11

5.1 Operational Characteristics of a BJT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.2 Operation of the Basic RTL Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.3 Input/Output Characteristics of a RTL Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.4 Cascading RTL Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.5 RTL Gate Noise Margin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6 Diode-Transistor-Logic (DTL) 15

1 Prepared by Dr. E.C. Kulasekere

2 · EN201 - Principles of Electronics

6.1 Operation of the Basic DTL Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6.1.1 Cutoff analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1.2 Saturation analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1.3 Base discharge resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2 Fan-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2.1 Output transistor loading due to a single driven gate . . . . . . . . . . . . . . . . . . . . . 17
6.2.2 Output transistor loading due to N driven gate . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3 Integrated Circuit DTL Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.4 Input-Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.5 The Wired-AND Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.6 High Threshold Logic (HTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7 Transistor Transistor Logic (TTL) 22

7.1 Issues with DTL Logic Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.2 Basic TTL Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.3 Fabrication of the Input Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.4 The Multi-Emitter TTL Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

1. INTRODUCTION
There are several different families of logic gates. Each family has its capabilities and limitations, its advantages
and disadvantages. The following list describes the main logic families and their characteristics. More information
will follow later in the section.

Diode Logic (DL): These use diodes to perform AND and OR logic function. The fact that a diode can act
as a switch is used in these constructions. Very simple and inexpensive and can be used effectively in specific
situations. The NOT function cannot be implemented using DL. Hence the usefulness is limited.
Resistor-Transistor Logic (RTL): These use Transistors to combine multiple input signals, which also
amplify and invert the resulting combined signal. Often an additional transistor is included to re-invert the
output signal. This combination provides clean output signals that are either inverted or non-inverted. RTL
gates are almost as simple as DL gates, and remain inexpensive. However these draw a lot of current from
the power supply for each gate. Another limitation is that the RTL gate cannot switch at high speeds due to
the transistor. RTL gates have only historical significance since they are no longer used in the fabrication of
gates.
Diode-Transistor Logic (DTL): By letting diodes perform the logical AND or OR function and then
amplifying the result with a transistor, we can avoid some of the limitations of RTL. DTL takes diode logic
gates and adds a transistor to the output, in order to provide logic inversion and to restore the signal to full
logic levels. Again DTL gates are not longer used in gate fabrication and its only of historical significance.
The improved version of this is found in TTL.
Transistor-Transistor Logic (TTL): The physical construction of integrated circuits made it more effective
to replace all the input diodes in a DTL gate with transistors built with multiple emitters. The result is
transistor-transistor logic, which became the standard logic circuit in most applications for a number of years.
As the state of the art improved, TTL integrated circuits were adapted slightly to handle a wider range of
requirements, but their basic functions remained the same. These devices comprise the 7400 family of digital
ICs.
Emitter-Coupled Logic (ECL): Also known as Current Mode Logic (CML), ECL gates are specifically
designed to operate at extremely high speeds, by avoiding the ”lag” inherent when transistors are allowed to
become saturated. Because of this, however, these gates demand substantial amounts of electrical current to
operate correctly.
 Logic Families · 3

MOS/CMOS Logic: One factor is common to all of the logic families we have listed above: they use
significant amounts of electrical power. Many applications, especially portable, battery-powered ones, require
that the use of power be absolutely minimized. To accomplish this, the CMOS (Complementary Metal-Oxide-
Semiconductor) logic family was developed. This family uses enhancement-mode MOSFETs as its transistors,
and is so designed that it requires almost no current to operate. CMOS gates are, however, severely limited in
their speed of operation. Nevertheless, they are highly useful and effective in a wide range of battery-powered
applications.

The basic circuit in each IC digital logic family is either a NAND or a NOR gate. These are the primary
building blocks with which more complex blocks are derived. This is the reason behind learning the NAND/NOR
implementation during combinational circuit design.
In order to analyze the logic families we use some special characteristics such as fan-in, fan-out, power dissi-
pation, propagation delay, and noise margin. Now we look more closely at these parameters.

2. SPECIAL CHARACTERISTICS
2.1 Fan-In
Fan-in is the number of inputs a gate has. For example a two input AND gate has a fan-in of 2. A NOT
gate always has a fan-in of one. The fan-in has some effect on the delay offered by a gate. Normally the delay
increases as a quadratic function of fan-in.
In another form the fan-in can be defined as the number of standard loads drawn by an input to ensure reliable
operation of the gate. Most inputs have a fan-in of 1.

2.2 Fan-Out
The fan-out of a gate specifies the number of standard loads that can be connected to the output of the gate
without degrading its normal operation. A standard load is defined as the amount of current needed by an input
of another gate in the same logic family. The fan-out is also referred too as loading. Note that this quantity has
meaning only within one logic family. If the connection is between two logic families, then the interface circuitry
should accommodate the drive requirements and limitations of both families.
Fan-out is important because each logic gate can supply only a limited amount of current before the operation
is degraded. The computation for fan-in is carried out depending on the capability of the logic gate to maintain
either logic high or logic low. Consider Figure 1. When the gate is at logic high, it provides current IOH to all

I OH I OL

I IH I IL

I IH I IL

To other To other
inputs inputs

(a) High-level output (b)Low-level output

Fig. 1. Fan-Out Configuration
Fig. 10-3 Fan-Out Computation

the gates that are ©loading it.Hall,

2002 Prentice WhenInc. the gate is at logic low, it sinks current IOL from the loading gates. The
M. Morris Mano
DIGITAL DESIGN, 3e.
4 · EN201 - Principles of Electronics

fan-out (FO) of the gate is calculated from

 
IOH IOL
FO = min , .
IIH IIL
Example 1. A standard TTL gate has the following parameters. IOH = 400 µA, IIH = 40 µA, IOL = 16 mA
and IIL = 1.6 mA. Compute the FO.

Solution:- The ratios gives rise to the same number, in this case it is 10. Hence FO=10.
In general a TTL gate has a fan-out of 10. Now we look at the effects of loading the gate output beyond its
rated fan-out. It has the following effects.

1. In the LOW state the output voltage VOL may increase above VOL,max .
2. In the HIGH state the output voltage VOH may decrease below VOH,min .
3. The operating temperature of the device may increase thereby reducing the reliability of the device and
eventually causing the device failure.
4. Output rise and fall times may increase beyond specifications
5. The propagation delay may rise above the specified value.

Normally as in the case of fan-in, the delay offered by the gate increases with the increase in fan-out.

2.3 Power Dissipation

This is the amount of power required to operate the electronic circuit. It is the power delivered to the gate from
the power supply and not the power delivered by the gate to the load. If the supply voltage is VCC and the gate
draws a current ICC from the source, the amount of power dissipated by the gate is VCC ICC . However since
the current drain from the power supply depends on the logic state of the gate, the average current is computed
using
ICCH + ICCL
PD (Avg) = VCC .
2
The variables have their usual meaning.

Example 2. For a TTL logic gate the ICCH = 1 mA (for the high state the current drain is low since the
transistor is off ) and ICCL = 3 mA (for the low state the transistor has to be in saturation). The average power
dissipated with a supply of 5V is 10 mW. If the number of gates within the IC is 4, the total dissipation is 40
mW.

There is also another quantity called ICCT which is the current drawn by the gate during transition (High to
Low state and vise versa). For TTL type gates the ICCT is negligible when compared to ICCL and ICCH . For
CMOS, the currents ICCL and ICCH are negligible when compared to ICCT . Hence the average power dissipated
for CMOS is computed as

PD (Avg) = VCC ICCT .

The consequence of this is that the CMOS family power dissipation is dependent on the frequency of operation
and in TTL this is not so. Power Dissipation is an important metric for two reasons.

1. Amount of current and power available in a battery is nearly constant. Power dissipation of a circuit or
system defines battery life. The greater the power dissipation, the shorter the battery life.
2. Power dissipation is proportional to the heat generated by the chip or system. Excessive heat dissipation
may increase operating temperature and cause gate circuitry to drift out of its normal operating range and
will cause gates to generate improper output values.

Thus power dissipation of any gate implementation must be kept as low as possible.
For further analysis, the power dissipation can be classified into two components:
 Logic Families · 5

Ps Static Power Dissipation : Power consumed when the gate is at logic high or logic low (or when the clock
is turned off). The power dissipation in this case is cause by the leakage current. For example, when the
transistor size is reduced to 90 nm, leakage current could be as high as 40% of total power dissipation.
Pd Dynamic Power Dissipation : The power dissipated during input and output transitions. We can esti-
mate the actual power to be Pd since it includes the leakage as well as the power consumed during transitions.

The total power is then the addition of these two quantities.

2.4 Rise Time/Fall Time and Delays

A set of gates can be considered as long cascade of switches. Several transition times and delays can exist in
such a system. The delays in different paths of the circuit may be different depending on the number of logic
gates it has to pass in trying to get to the output.

Example 3. Explain the issues related to the above delays.

A reduction of the number of logic levels result in the reduction of signal delay and faster circuits. Further, the
reduction of the propagation delay in circuits may be more important that the reduction of the total number of
gates if speed of operation is a major factor. In what follows we analyze some of them

2.4.1 Gate Delay. The gate delay is also known as the propagation delay. This is the delay caused by signal
traveling through the gate. The time between the logic transition on an input and the corresponding logic
transition on the output of the logic gate. The propagation delay is measured at midpoints (Figure 2 The

Input

Time

Output

tPHL tPLH

Fig. 10-4 Measurement of Propagation Delay

Fig. 2. Measurement of Propagation Delay

propagation delay ©may not be the same for both transitions. The low to high transition is called turn-on delay
2002 Prentice Hall, Inc.
ant high to low transitionMano
M. Morris is called the turn-off delay. The delays of several cascaded gates add up. Because of
DIGITAL DESIGN, 3e.
this cumulative property of delays, it is of major concern when compared to other kinds of delays. The maximum
frequency of operation of the gate can be hindered by excessive delays.

2.4.2 Wire Delay. Gates are connected together with wires and this wires do delay the signal they carry, this
delays become very signification with increase in frequency, say when the when transistor sizes are sub-micron.
Sometimes wire delay is also called as flight time (i.e. signal flight time from point A to B). Wire delay is also
knows as transport delay.

2.4.3 Rise/Fall Times. The rise (and fall) times are seen to be defined as the time required for the output
from the gate to change from 10 to 90 percent r 90 to 10 percent voltage levels. Manufacturers of logic gates
and other digital components often specify the values in data sheets since they are important in finding out the
maximum frequencies at which they can be used.
6 · EN201 - Principles of Electronics

A B

X X

Delay

Fig. 3. Wire or Transport Delay

2.5 Noise Margin

When a digital signal is transmitted over a medium spurious electrical signal can induce noise. The noise
component comes in two forms, firstly the DC noise caused by the drift in the voltage level in the signal or AC
noise that comes in the form of random pulses caused by other switching circuits. The noise margin indicates
the maximum noise voltage that can be added to an input signal of a digital circuit but still will not cause an
undesirable change in the circuit output. Digital gates that have a higher noise margin is preferable in a noisy
environment.
The noise margin is computed using the voltage levels of the input signal and output signal. We first define
the voltage levels corresponding to the two logic levels.

VOH,min : The minimum output voltage in HIGH state . VOH,min is 2.4 V for TTL and 4.9 V for CMOS.
VOL,max : The maximum output voltage in LOW state . VOL,max is 0.4 V for TTL and 0.1 V for CMOS.
VIH,min : The minimum input voltage guaranteed to be recognized as logic 1. VIH,min is 2 V for TTL and 3.5
V for CMOS.
VIL,max : The maximum input voltage guaranteed to be recognized as logic 0. VIL,max is 0.8 V for TTL and
1.5 V for CMOS.
IOH,min : The maximum current the output can source in HIGH state while still maintaining the output
voltage above VOH,min .
IOL,max : The maximum current the output can sink in LOW state while still maintaining the output voltage
below VOL,max .
II,max : The maximum current that flows into an input in any state (1µA for CMOS).

The Figure 4 illustrates the noise margin graphically The definition of the two noise margin’s are given below.

LNM (Low noise margin): The largest noise amplitude that is guaranteed not change the output voltage
level when superimposed on the input voltage of the logic gate (when this voltage is in the LOW interval).
LNM=VIL,max − VOL,max .
HNM (High noise margin): The largest noise amplitude that is guaranteed not change the output voltage
level if superimposed on the input voltage of the logic gate (when this voltage is in the HIGH interval).
HNM=VOH,min − VIH,min .

The noise margin of a digital gate is then defined as

NM = min {HNM, LNM}

3. DEVICE SPECIFIC CHARACTERISTICS

There are several other issues that have to be considered during the implementation of logic gates.
 Logic Families · 7

VCC VCC

VOH
High-state
noise margin
VIH

VIL
Low-state
noise margin
VOL

0 0

(a) Output voltage range (b) Input voltage range

Fig. 10-5 Signals for Evaluating Noise Margin

Fig. 4. Signals for Evaluating Noise Margin

© 2002 Prentice Hall, Inc.
M. Morris Mano
DIGITAL DESIGN, 3e.
3.1 Switching Speeds of Diodes
This implementation is only relevant to logic gate implemented using a combination of diodes. Here we give a
thought to the matter of how rapidly the diode can switch from one condition to another. A principle speed
limitation is encountered when we try to switch the diode from ON to OFF state. The speed limitation in
switching from OFF to ON is generally negligible in comparison, and will be neglected inmost cases. The reason
is that when the external voltage is suddenly reversed biased in a diode circuit which has been carrying current
in the forward direction, the current will not immediately fall to its steady-state reverse voltage value.
The above problem can be eliminated by using Schottky diodes (metal-semiconductor diodes). The Schottky
diodes exhibit negligible storage time. Hence the recovery time of such a diode, typically is in the rage 50 ps,
an order of magnitude smaller than the pn diode. The cutin voltage of Schottky diode is around 0.2-0.5V. In
general we assume this value to be around 0.35V.

3.2 Switching Speed of Bipolar Transistor

This is due to the mechanism which accounts for the delay involved in turning a transistor ON or OFF. The
speed limitation comes from the fact that the transistor is driven into saturation and the time it takes to recover
from this state. Hence the speed of the transistor can be improved by preventing the transistor from going into
saturation. One way of doing this is by using a Schottky diode connected from collector to base.

3.2.1 Operation of the BJT Transistor. In order to explain the operation behind the switching speeds we use
a npn transistor with the voltages and currents in the standard positive direction. A summary of the junction
conditions for the different states of the transistor is given in the table given below.

Region State of Junctions

Cutoff Both emitter and collector junctions are reversed biased. VBC < 0
and VBE < 0.
Active The emitter junction is forward biased and the collector junction
is reversed biased. VBE > 0 and VBC < 0.
Saturation Both emitter and collector junctions are forward biased. VBE > 0
and VBC > 0.

If the diode in the BE junction has a cutin voltage of 0.65V, the transistor will reach the active region only
when this voltage is exceeded. Subsequent small increase in the base-emitter voltage will result in the rapid
8 · EN201 - Principles of Electronics

increase in the collector current (IC ). This is the active region. However when VBE reaches about 0.75V the
transistor will be driven into saturation. The onset of saturation will occur at VCE ≈ 0.35V. As this condition
occurs the base-collector voltage will reach zero and then tun positive such that the CB junction now becomes
forward biased. The extent to which it is forward biased is given by VBC = VBE − VCE = 0.75 − 0.35 = 0.4V.
At complete saturation we will see that this equation turns out to be VBC = 0.8 − 0.2 ≈ 0.6V (using the fact
that VCE,sat = 0.2V).

3.2.2 Operation of the Schottky transistor. When the transistor is in the active region, the diode does not
conduct. This is because the collector base junction is reversed biased. The diode will only conduct when the
collector base junction is forward biased. When the extent to which the CB junction is forward biased is 0.4V,
the diode will conduct (since the Schottky diode has a cutin around this region). However the diode will then
not allow the collector to fall lower than 0.4V below the base voltage. We have seen that at saturation with
VBE (sat) = 0.75V and VCE (sat) = 0.2V and hence the base-collector voltage has to be around 0.75−0.2 ≈ 0.55V
for full saturation to set in. That is, the diode never lets the collector voltage fall low enough to substantially
forward-bias the collector junction, and the transistor is thereby restrained from becoming saturated. Since it
is not completely driven into saturation the recovery during switching of the transistor is faster in a Schottky
transistor. The general circuit for this is given in Figure 5.

VCC VCC

RC RC

(a) (b)

Fig. 5. The Schottky Transistor

3.3 Clock Skew

Same signal arriving at different parts of design with different phase is know as skew. Skew is normally associated
with clock signals. In the Figure 6 given below, the clock signal CLK reaches flip-flop FF0 at time t0, hence
with respect to the clock phase at the source compared to the clock at FF0 input a clock slew of t0 time units
exists. Normally this is in nano seconds.

IN D Q D Q D Q OUT

FF0 FF1 FF2

CK0 CK CK2 CK CK1 CK

Fig. 6. Flip-Flop Circuit

 Logic Families · 9

Example 4. Draw the clock waveform at different parts of the design given in Figure 6.

4. DIODE LOGIC
In DL (diode logic), all the logic are implemented using diodes and resistors. It uses the fact that a diode has
to be forward biased to conduct. We look at some implementations

4.1 DL OR Gate
The circuit in Figure 7 shows a basic DL OR gate. We will assume that a logic 1 is represented by +5 volts, and

vA

vB vQ

vC

Fig. 7. Diode Logic OR Gate

a logic 0 is represented by ground, or zero volts. In the Figure 7, if both inputs are left unconnected or are both
at logic 0, output vQ will also be held at zero volts by the resistor, and will thus be a logic 0 as well. However, if
either input is raised to +5 volts, its diode will become forward biased and will therefore conduct. This in turn
will force the output up to logic 1. If both inputs are logic 1, the output will still be logic 1. Hence, this gate
correctly performs a logical OR function.
In the above description we have assumed that the diodes do not introduce any errors or lesses into the circuit.
However is it known that Silicon diodes introduce a forward voltage drop of 0.65-0.7V while in the conducting
state. Hence vQ ≈ 4.35V when at least one diode is conducting. Here is where the noise margin becomes useful.
We can get around this very nicely by specifying that any voltage above +3.5 volts shall be logic 1, and any
voltage below +1.5 volts shall be logic 0. It is illegal in this system for an output voltage to be between +1.5
and +3.5 volts; this is the undefined voltage region.

4.2 DL AND Gate

The DL implementation of the AND gate is shown in Figure 8. In comparison with the OR gate the diodes have
been reversed and the resistor is set to pull the output voltage up to a logic 1 state.
For this example, +V = +5 volts, although other voltages can just as easily be used. Now, if both inputs are
unconnected or if they are both at logic 1, output vQ corresponds to a logic 1. If either input is grounded (logic
0), that diode will conduct and will pull the output down to logic 0 as well. Both inputs must be logic 1 in order
for the output to be logic 1, so this circuit performs the logical AND function.
As in the case of a DL OR gate, if we consider a non-ideal diode, the output is held at vQ ≈ 0.65 if at least
one input is sent to 0V.

Example 5. Show that a positive logic AND gate is equivalent to a negative logic OR gate and vise versa.
10 · EN201 - Principles of Electronics

5V

vA

vB vQ

vC

Fig. 8. Diode Logic AND Gate

4.3 Issues Related to DL

We note the following points.

1. Diode Logic suffers from voltage degradation from one stage to the next.
2. Diode Logic only permits the OR and AND functions.
3. Diode Logic is used extensively but not in integrated circuits.

We analyze the first item given a little further. Consider the cascaded DL gates shown in Figure 9. The DL

VCC

B Z=AB+CD

D R

VCC

Fig. 9. Cascaded DL Circuit

gates can be used as individual gates such as in AND or OR gates. However, when DL gates are cascaded, as
shown in Figure 9, some additional problems occur. In this case we have two AND gates, whose outputs are
connected to the inputs of an OR gate. Very simple and apparently reasonable.
Now consider the following scenario. If we pull the inputs down to logic 0, sure enough the output will be held
at logic 0. However, if both inputs of either AND gate are at +5 volts, what will the output voltage be? That
diode in the OR gate will immediately be forward biased, and current will flow through the AND gate resistor,
through the diode, and through the OR gate resistor.
If we assume that all resistors are of equal value (typically, they are), they will act as a voltage divider and
equally share the +5 volt supply voltage. The OR gate diode will insert its small loss into the system, and the
output voltage will be about 2.1 to 2.2 volts. If both AND gates have logic 1 inputs, the output voltage can rise
to about 2.8 to 2.9 volts. Clearly, this is in the ”forbidden zone,” which is not supposed to be permitted.
 Logic Families · 11

If we go one step further and connect the outputs of two or more of these structures to another AND gate, we
will have lost all control over the output voltage; there will always be a reverse-biased diode somewhere blocking
the input signals and preventing the circuit from operating correctly. This is why Diode Logic is used only for
single gates, and only in specific circumstances.

5. RESISTOR TRANSISTOR LOGIC (RTL)

In order to analyze the RTL gate we need to understand the operations of a bipolar transistor. The Figure 10
gives us the characteristic curves of the BJT.

5.1 Operational Characteristics of a BJT

V cc

1C RC

Vo
1B
Vi
RB
1E

(a) Inverter circuit

1C
1B (mA)
(mA) 0.6
VCC
RC 0.5
0.4
0.4
1B = 0.2 mA
VBE (V) VCE (V)
0.6 0.7 0.8 VCC

(b) Transistor-base characteristic (c) Transistor-collector characteristic

Fig. 10-6 Silicon npn Transistor Characteristics

© 2002 Prentice Hall, Inc.
Fig. 10. Silicon npn Transistor Characteristics
M. Morris Mano
DIGITAL DESIGN, 3e.

The three regions of operation for the transistor and the corresponding state of the parameters is given in
Table 1 To demonstrate how the above table can be used in determining the state of the transistor we use the

Region VBE (V) VCE (V) Current Relationship

Cutoff < 0.6 Open circuit IB = IC = 0
Active 0.6-0.7 > 0.8 IC = hF E IB
Saturation 0.7-0.8 0.2 IB ≥ ICS /hF E

Table 1. Typical non Silicon Transistor Parameters

following example.

Example 6. Consider the inverter circuit shown in Figure 10(b) with the following parameters.
RC = 1 kΩ VCC = 5V
RB = 22 kΩ H (high level voltage) = 5V
hF E = 50 L (low-level voltage) = 0.2V
Analyze the circuit for a logic one and logic zero.
12 · EN201 - Principles of Electronics

5.2 Operation of the Basic RTL Gate

The RTL type of gate is no longer used in new designs. However this is a good starting point for analysis. RTL
gate is the historically first gate to have been used extensively. The basic gate, the NOR gate, of the RTL family
is shown in Figure 11. The volage level for the circuit is 0.2V for the low level and 1-3.6V for the high level.

VCC = 3.6V

640Ω

Y=(A+B+C)

450Ω 450Ω 450Ω

A B C

Fig. 11. RTL Basic NOR Gate

The operation of the NOR gate given in Figure 11 is given below. We adopt the convention of positive logic,
then the gate can be shown to act as a NOR gate. In RTL logic the voltage VL should be low enough for
the corresponding transistor to be cutoff when VL is applied to the gate input. VH on the other hand should
be capable of driving the transistor into saturation. It is necessary that VL < 0.6, the cut-in voltage of the
emitter-base junction and VH be equal to or higher than the voltage which when applied through the 450 Ω
resistor will bring the transistor to saturation.
If any input of the RTL gate is high, the corresponding transistor is driven into saturation. This causes the
output to be low, regardless of the states of the other transistors since Vo = VCC − IC RC with a very high IC
value makes Vo to be low. If all of the inputs are low at 0.2 V, all transistors will be cut off because VBE < 0.6
V. Hence the output at this state will be nearly the supply voltage. Note that the NOR gate can be used to
implement all the logic operations hence the family is complete. The resistor values given in the figure are
standard values available in the commercial implementation. The supply voltage is typically VCC = 3 V.
Exercise 1. Explain what is meant by current hogging in RTL gates. Explain how this is avoided using a
series resistor at the base of each transistor.

5.3 Input/Output Characteristics of a RTL Gate

The input-output voltage characteristics of a RTL gate is shown in Figure 12. It is drawn for a particular gate
input with all other transistors assumed to be in the cutoff region.
The following operations can be highlighted.
Input to transistor State of transistor Output of transistor
Vi < 0.65 V Cutoff Vo = VCC = 3 V
0.65 V < Vi < 0.8 V Active Vo decreases from 3 V to 0.2V
Vi > 0.8 V Saturation Vo = 0.2 V
At saturation (or output low state) the collector current is
3.0 − 0.2
IC = = 4.4 mA
640
Hence the power consumption of a single gate is around 12 − 13 mW. There is a low power RTL NOR gate
available with RC = 3.6 kΩ and RB = 1.5 kΩ. A disadvantage of the low power gate is that the larger resistors
will cause slower operations i.e. the propagation delay time is longer. The reason for this longer delay is that
all stray capacitances and capacitances inherent in the active device must charge and discharge through these
larger resistors.
 Logic Families · 13

Vo

0.2

0.65 0.8 Vi

Fig. 12. Input Output Characteristics

5.4 Cascading RTL Gates

Fan-out is limited by the fact that when the output of the driving gate is at logic 1 level, the transistor of
the driven gate must all be supplied enough current to saturate them. The current required is supplied by the
supply voltage of 3 V through the 640 Ω collector resistor of the driving gate and hence is limited by the simple
constraints of the Ohms law.
Apart from the above, there is another important fact to consider. Lets look at the combination of gate
cascades given in Fig 13.

Io 1 I1
G0
G1 0
1

I2
G2 0
0

Fig. 13. A Cascade of NOR gates

The output of gate G0 is at logic 1 and is supplying current to two other gates G1 and G2 whose outputs are
at logic 0. The current I1 supplied to the base of the transistor in gate G1 is wasted. That is, the output of
the gate will be at logic 0 even if the gate is not supplied with I1 . On the other hand the current I2 is essential
to keep the output of gate G2 at logic 0. It can be shown that the wasted current I1 is more than the useful
current I2 . In order to illustrate this we use the 2-input NOR gate given in Figure 14.
The transistor on the right hand side is saturated. Hence the output is driven to VCE (sat) = 0.2 V . as a
result the output of the transistor on the left hand side is held at 0.2 V even when Vi < 0.65 V . As the input Vi
increases to drive the transistor from cut off to the active region we have the following phenomena. When the
base emitter junction is forward biased, i.e. VBE = 0.65 V we have

VBC = VBE − VCE

= 0.65 − 0.2 = 0.45 V.
14 · EN201 - Principles of Electronics

VCC = 3.6V

640Ω

450Ω 450Ω
Vi 1

Fig. 14. Two input NOR gate

Hence both the B-E and C-B junctions are forward biased, hence the transistor should be in saturation. That
is the transistor is either in cutoff or in the saturation region.
However if the right hand side transistor was at cut off (i.e. the input is at logic low), then the situation
is different. Now as Vi increases the transistor moves from the cutoff region to the active region and then gos
into saturation once VBE = 0.75 V . We note that for the two cases there is a 0.1 V difference in the voltage
(Vi − VBE ). That is, there will be an additional base current of 0.1/450 = 220µA if the other input is at logic
high.
From the above we determine that the worst case situation occurs when one gate connected to the driving
gate is supplied with useful current where as for all the other gates the current supplied is wasted. We now
concentrate in calculating the base current required to saturate a transistor.
We know that for a transistor in saturation
IC
IB ≥ .
hF E
Further there exists a parameter σ (obtained from the Ebers-Moll model) such that
IC
.IB =
σhF E
Where σ = 1 indicates the transistor is in the active region and σ < 1 indicating that the transistor is in
saturation. If we assume that the transistor has hF E = 50, σ = 0.85 can be estimated using standard plots.
Since we already computed that at saturation IC = 4.4 mA we can compute
4.4 × 10−3
IB = ≈ 100 µA
50(0.85)
This is the base current required to drive a transistor into saturation. Noting that VBE (sat) = 0.75 V we find
the input a transistor requires to be in this saturation condition as

Vi = 450IB + VBE
= 450 × 100 × 10−6 + 0.75 ≈ 0.8 V

Hence the maximum available current from the driver transistor is

VCC − Vi 3.0 − 0.8
IOH = Io = = = 3.4 mA.
640 640
If we consider the worst case condition, all the other gates are being supplied by the wasted current. The input
voltage to these gates is held at 0.8 V. Hence the base current into these gates is given by
Vi − VBE 0.8 − 0.65
= ≈ 330 µA.
450 450
If we have a fan-out of N then
3400 = 100 + (N − 1)330
 Logic Families · 15

Thus we find out at room temperature N = 11. We also note that if hF E reduces due to temperature variations,
the fan out will also decrease.

5.5 RTL Gate Noise Margin

The noise margin is directly related to the operating temperature of the gate. However for simplicity we will
consider the noise margin at room temperature. Using the Figure 12 we see that the noise margin for low signal
input is
LN M = 0.65 − 0.2 = 0.45 V,
where as the noise margin for high signal input is

HN M = 3.0 − 0.8 = 2.2 V.

In particular the input-output characteristics take the form given in Figure 15

Vo

A B
VOH

C D
VOL
Vi
VOL VIL VIH VOH
LNM HNM

Fig. 15. Input output characteristics

Exercise 2. Plot the input-output characteristics of a RTL gate for different temperatures and show that the
temperature decreases, the following occur.
1. LNM increases.
2. HNM decreases.
3. The change in HNM is relative independent of temperature.
4. As the fan-out increases the noise margin decreases.

6. DIODE-TRANSISTOR-LOGIC (DTL)
The basic circuit element in DTL digital logic family is the NAND gate as shown in Figure 16. The construction
of this gate is the combination of diode logic AND gate and the transistor in its inverter configuration.
It should be noted that the gate performs the NAND function for positive logic.

6.1 Operation of the Basic DTL Gate

6.1.1 Cutoff analysis. Each input diode will be driven by the transistor output of the previous stage when gates
are cascaded. Hence if the preceding gate is at logic LOW, the voltage seen by the next stage is VCE (sat) = 0.2.
Assume at least one of the inputs A,B, or C is at 0.2 V. Then that diode will be forward biased and the voltage
at point P will be VP = VCE (sat) + VD = 0.2 + 0.75 = 0.95 V . Here we have assumed a diode forward drop of
0.75 V. That is we are assuming that the current through the diode
VCC − VP 5 − 0.95
ID = = ≈ 2 mA,
R 2
16 · EN201 - Principles of Electronics

VCC = 5V

R = 2kΩ
2kΩ
D1
A
Vo
D2 D4 D5
B
P
D3
C R = 20kΩ

-2V

Fig. 16. DTL Basic NAND Gate

is adequate to produce a voltage drop of 0.75 V acrose the diode D1 . If we assume that the diodes D4 and D5
are just driven to the forward biased region, VD,4 = VD,5 = 0.65 V (note that this is smaller than the cutin
voltage of D1 since the expected current through D4 and D5 is smaller than 2 mA. With this assumption we
can compute the base to ground voltage (VB of the transistor as

VB = VP − VD,4 − VD,5 = 0.95 − 0.65 − 0.65 = −0.35 V.

This is less than the cutin voltage of the base-emitter junction and hence the transistor is in the off region.
Since the transistor is in the cutoff region the current through the diodes D4 and D5 will flow through the
20 kΩ resistor and can be computed as,
VB − (−2) −0.35 + 2
I20kΩ = = = 0.08 mA.
20 20
It is indeed seen that this current is smaller than the current through D1 . Hence the output voltage of the
transistor is 5 V. This corresponds to logic level 1. Similarly we can show that if all the inputs are at logic level
0 (0.2 V), the output Vo will remain at logic level 1. However if all three diodes D1 to D3 are forward biased, the
current 2 mA will be divided among the three diode and thus this reduction in current will result in the cutin
voltage reducing by a small amount. This will further reduce VP and as a result VB will be reduced ensuring
that the transistor is still in the cutoff region.

6.1.2 Saturation analysis. If all of the inputs to the gate are at logic 1 (5 V) then the input diodes D1 , D2 and
D3 are off. Hence we have to show that the base current is now sufficient to drive the transistor into saturation.
This will result in Vo = VCE (sat) = 0.2 V. The current from the course VCC now flows through the 2 kΩ resistor
and the diodes D4 and D5 . Let us assume that the base current is IB and it is sufficient to cause VB ≈ 0.75 V.
Now
VB − (−2) −0.75 + 2
I20kΩ = = = 0.14 mA.
20 20
The voltage at point P is now VP = VD,4 + VD,5 + VB = 0.75 + 0.75 + 0.75 = 2.25 V. The current from the
source can now be computed as
VCC − VP 5 − 2.25
ID,4 = = ≈ 1.4mA.
R 2
Then the base current IB = ID,4 − I20kΩ = 1.4 − 0.14 = 1.26mA. Which is clearly sufficient to drive the
transistor into saturation. Further at this stage IC = (5 − 0.2)/2 = 2.4 mA. We can also show that IB (=
 Logic Families · 17

1.4mA) ≥ IC /hF E (= 2.4/50) which indicates that the transistor is in saturation.

6.1.3 Base discharge resistor. Consider a situation in which all the inputs are at logic 1 and all of a sudden
one input drops to logic 0. If there was no charge storage in the system, the base current IB would instantly drop
causing the base-emitter voltage to fall below the cutin voltage and the transistor will be immediately driven
to cutoff. However there is charge stored in the transistor. When VP drops cutting off D4 and D5 , this stored
charge leaves through the 20kΩ base resistor. Hence this resistor provides the discharge path. To increase the
rate of discharge, the resistor is connected to a −2 V power supply.

6.2 Fan-Out
The Figure 17 shows the DTL gate driving N other gates.

VCC = 5V VCC = 5 V
VCC = 5 V
Rc = 2 kΩ IRc
VCC = 5V
RB = 2 kΩ RB = 2 kΩ
Vo DA1
Rc = 2 kΩ IL ID
T1 IL1
Vi DA P D1 D2
T0
Rb = 20 kΩ
DB
VCC = 5 V
DC VCC = −2 V
RB = 2 kΩ
Gate G1 DAN

ILN

Fig. 17. DTL Gate with fan-out

The transistor T 0 is the output stage of the gate of a preceding level. The diodes DA1 to DAN are the input
diodes of N gate in the following level.
In order to find the fan-out for DTL circuit we have to consider the worst case situation of current drawn
from the gate G1 and the corresponding maximum loading that will occur at the output transistor of a gate.

6.2.1 Output transistor loading due to a single driven gate. In order to estimate the worst case loading of an
output transistor we look at the left hand segment of Figure 17 consisting of the diodes DA to DC and the
transistor T 0. The state of the gates in Figure 17 is as follows. T 0 is saturated hence Vi = VCE (sat) = 0.2 V.
T 2 is at cutoff and hence ID ≈ 0.
When the gate output transistor T 0 is sinking the current of gate G1 that it is driving. It encounters the
heaviest loading when all the other outputs of the driven gate are at logic level ‘1’ (equivalently when all the
other gates are kept floating). Note that when at least one of the inputs (say Vi ) is at the low voltage the
transistor T 2 is off. Hence the total current drawn from the source flowing through RB will sink through the
diodes DA to DC into the output stage transistors of the driving date (for example T 0 in the case of DA).
However, if DB is also driven by a output stage transistor which is saturated, then some of the current through
RB will flow across DB into the gate driving DB. As a consequence the loading in T 0 is reduced. Hence the
heaviest loading in T 0 will occur when all the other diodes not connected to T 0 are off (correspondingly the
input voltage is at logic high).
Hence, the total current (IL ) through RB that continues through DA and into the collector of T 0 is given by
VCC − (Vγ + VCE (sat) 5 − (0.75 + 0.2) 4
IL = = ≈ mA.
RB RB RB
18 · EN201 - Principles of Electronics

Here we have assumed that the cutin voltage of the diode is 0.75 V since the current through the diode is
substantial. Also since the T 2 is cutoff, ID was shown to be very small at a previous occasion. Hence the total
current through RB flows out through DA. If we substitute for RB we see that IL ≈ 2 mA. We also note that
in order to reduce this loading we can increase the resistance RB . However this is detrimental to the operation
of the gate as indicated at a previous occasion.

6.2.2 Output transistor loading due to N driven gate. We use the right hand side of Figure 17 consisting of
T 2 and diodes DA1 to DAN with the following gate states for the analysis that follows. T 2 is saturated (as
indicated above the maximum loading occurs when the output stage transistor of a gate is in saturation). To
saturate T 2, all inputs to the gate G1 should be at the logic High level and hence diodes DA, DB and DC
would be cutoff.
The current through RB now flows through diodes D1 and D2 into the base of the transistor T 2 and saturates
it. The current flowing in each of the N loading gates is the worst case current computed from the previous
section. i.e.
4
IL1 = IL2 = . . . = ILN ≈ .
RB
All assumptions used in section 6.2.1 is applicable here. Also the collector current through Rc of T 2 is given by
VCC − VCE (sat) 5 − 0.2
IRc = = ≈ 2.4 mA.
Rc 2 kΩ
Hence the total collector current (IC ) of T 2 is
4
IC = 2.4 + N.
RB
When T 2 is saturated
Vp = 2vγ + VBE (sat) = 2 × 0.75 + 0.75 = 2.25 V.
Here we have assumed that for D1 and D2, Vγ = 0.75 V considering the current through them. At a previous
instance we have shown that when T 2 is saturated IRb ≈ 0. Hence
VCC − Vp 2.75
IB ≈ ID = = .
RB RB
We also note that for a saturated transistor IC = σhF E IB where σ is determined using Figure ??. Using the
current information available  
4 2.75
2.4 + N = σhF E
RB RB
Then
N ≈ 0.7σhF E − 600RB .
Using the relationship for fan-out we note the following
1. To increase N we have to increase σ. That is, we have to restrict the extent to which the transistor is
saturated (see Figure ??).
2. For a fixed value of RB if we keep increasing N at some point σ = 1 and the transistor will move into the
active region. Hence the fan out will be limited at this point. The reason for this is that for each additional
load that we attache to the gate, an additional 2 mA will be added to the collector current of T 2. However
the base current is not effected by this. Since IC = σhF E IB , we see that σ has to increase.
3. We can also decrease RB to increase the fan-out. However this will result in increased power consumption of
the gate.

6.3 Integrated Circuit DTL Gate

Two IC versions of the DTL gate is available. One with Rc = 2 kΩ and the other is with Rc = 6 kΩ (Low power
version). Again we note that with Rc large, the system becomes sluggish resulting in higher propagation delays.
The IC version of the DTL gate is shown in Figure 18. Several improvements can be seen.
 Logic Families · 19

VCC

ρRB 1.6kΩ

Rc = 2kΩ/6kΩ

(1 − ρ)RB 2.15kΩ

T1 Vo
DA D2
P T2

DB
Rb = 5kΩ

DC

Fig. 18. IC version of DTL gate

1. The diode D1 has been replaced by the transistor T 1. This will make more base current available due to its
amplification action and ensure that the transistor will not reach the active region when loaded. Hence the
fan out is increased with this change.
2. The base leakage resistor is now connected to ground rather than a negative voltage. This will eliminate the
requirement of two voltage sources.
3. The total effect in T 2 dependence of N on σ is eliminated. The new fan-out is
0.7σhF E
N= .
ρ
6.4 Input-Output Characteristics
The following states are required to draw the input-output characteristics of a DTL gate. The discussion is
based on Figure 15 and Figure 18.

1. Point A in Figure 15.

When Vi = 0.2 V, T 2 is cut-off and Vo = VCC = 5 V. However in general Vo will depend on the fan out.
2. Point B in Figure 15.
As the input value increases from VCE (sat) = 0.2 Vo begins to fall off. i.e. when the transistor T 2 is at the
edge of cutoff. The input to DA is still close to 0.2 V. Hence the input diode DA is forward biased. Since T 2
is at the edge of cutoff VBE = 0.65 V. The current flowing from the source through RB will go through T 1,
D2 and travel through Rb rather than the base of T 2 (T 2 off means IB ≈ 0). In fact the current through Rb
is
Vγ 0.65
ID ≈ = = 0.13 mA.
Rb 5 kΩ
Also since DA is forward biased a significant amount of current will still be flowing through it. For this
condition

Vp = 2 ∗ 0.7 + 0.65 = 2.05 V

20 · EN201 - Principles of Electronics

Note that we have assumed a Vγ = 0.7 for the BE junction of T 1 and for the diode D2 as the current
through then is not sufficient to drive them into the saturated values. However the current through DA is
still significant. Hence its Vγ = 0.75 V. Hence

Vi = 2.05 − 0.75 = 1.3 V.

3. Point C in Figure 15.

Now the transistor T 2 is completely in saturation. i.e. we need to find the minimum value of Vi needed
to saturate T 2. As Vi increases, less and less current flows in DA and at some point the cutin voltage
of DA becomes Vγ = 0.65 V. At this point the BE junction of T 1, D2 and T 2 will all have junction
voltages of Vγ = 0.75 V due to the heavy current through them. Hence Vp = 3 × 0.75 = 2.25 V. Then
Vi = Vp − 0.65 = 1.6 V.
4. Point D in Figure 15.
At this point the input voltage Vi has increased to VOH and the output voltage Vo = 0.2 V.

6.5 The Wired-AND Connection

A useful extension to the DTL gates are its wired-AND connection where the outputs of two DTL gates are
connected together. This will make the outputs to a single connection as shown in Figure 19.

VCC

X1 T21

Y = X1.X2
VCC

X2 T22

Fig. 19. The Wired-AND connection

If the function implemented by the wired-AND gate is constructed using regular DTL gates, it would required
more gates. However the wired-AND connection will reduce the fan-out of DTL gates. Consider one output
transistor conducting while all the other output transistors of the wired connection being in the cutoff region.
Then the conducting transistor should not only sink the current of the loading gates, but also the currents due
to the pull-up resistors of all the transistors. This is shown in Figure 20.
Consider the situation where T 1 is saturated and T 2, . . . , T K are cutoff. Then the collection currents IC,T 2 =
. . . = IC,T K = 0. The driven gates are represented by their input diodes (DA1, DA2, . . . , DAN ) and a series
resistor R (the base resistor of the driven gate, it is assumed that R = 3.75 kΩ). The other input diodes are
ignored since we have already shown that the worst case situation of current drain from the gate occurs when
all the other input diodes are off.
For this case we note that the collector current into T 1, IC,T 1 is given by
K
X N
X
IC,T 1 = I1 + Ii + ILj . (1)
i=2 j=1
 Logic Families · 21

VCC

R IL1

DA1

VCC =5V VCC

R IL2

DA2
IR Rc = 2kΩ IR Rc IR Rc

X1 T1 X2 T2 XK TK

VCC

R ILN

DAN

Fig. 20. The Wired-AND connection for K gates

We note that the current in each diode is the same,

VCC − Vγ − VCE (sat) 5.0 − 0.75 − 0.2
IL1 = IL2 = . . . = ILN = = = 1.08 mA.
R 3.75 × 102
Where Vγ is the saturation cutin voltage of each diode. Likewise we can also determine that
VCC − VCE (sat) 5 − 0.2
I1 = I2 = . . . = IK = = = 2.4 mA.
Rc 2 × 103
Using the above information, eq (1) ca be rewritten as

IC,T 1 = KI1 + N IL1 . (2)

We now embark upon finding the reduction required in the output loading factor as a function of K. If we
increase the number of wired gated by 1, to keep the loading of T 1 the same we have to satisfy

IC1 = 2.4K + 1.08N1 = 2.4(K + 1) + 1.08N2 ,

where N1 is the fanout without any additional fan out while N2 is the fan out when K + 1 gates exist in the
wired connection. The above can be simplified to
2.4
N1 − N2 =≈ 2.2.
1.08
The above equation indicates that each gate connected in parallel with T 1 to form a wired-AND, we must reduce
the maximum output loading by 2.2 gates. The net result will be to keep the collector current fixed and therefore
T 1 is kept in saturation. In the specifications the given values is 2.5 gates have to be reduced for each new gate
in the wired-AND configuration.

6.6 High Threshold Logic (HTL)

The regular DTL gate is not good for noisy environments. HTL logic gates, on the other hand is useful in noisy
environments. The configuration of an HTL gate is given in Figure 21.
In the HTL gate, the noise threshold has been increased by increasing VCC . With the higher voltage, the D2
given in Figure 18 has been replaced by a zenner diode in Figure 21 so that the higher voltages can be sustained
during switching operations. Also note that the resistor values have been increased so that the currents are
22 · EN201 - Principles of Electronics

VCC = 15 V

ρRB 3 kΩ

Rc = 15 kΩ

(1 − ρ)RB 12 kΩ

T1 Vo
DA DZ
P + − T2
VZ
DB
Rb = 5 kΩ

DC

Fig. 21. The HTL Gate

kept low corresponding to the increased voltages. Hence the power dissipation of the gate is not appreciably
increased. However these higher resistors will make the gate operate slower (sluggishly) since the stray and gate
output capacitances now have have a higher time constant. DTL gates have a propagation time tens of nano
seconds where as the HTL gate has propagation times as high as hundreds of nano seconds. The zenner voltage
is chosen to be around 6.9 V.
In a DTL gate when the temperature rises, the diode and transistor cutin and saturation voltages change. All
temperature sensitivities add up for all the diodes in a DTL gate (for example in Figure 18). However in the
HTL gate, the temperature sensitivity of the diodes are in one direction while the temperature sensitivity of the
zenner diode in the opposite direction. Hence they cancel out leaving a gate that is less sensitive to temperature
variations.

Exercise 3. Plot the temperature characteristics for a DTL gate and an HTL gate. Compare the results and
comment on the temperature sensitivity. Compute the noise margins.

7. TRANSISTOR TRANSISTOR LOGIC (TTL)

The original TTL gate was a slight improvement on the DTL gate. However now we have a series of enhancements
that have been applied to the basic TTL gate to form different logic families. We will first explain the drawbacks
of a simple DTL gate and then get into the TTL operation.

7.1 Issues with DTL Logic Gates

The Figure 22 gives the configuration of a DTL gate with input diode replaced by the transistor version of a
diode.
We note the following.

1. Consider the case when Vi = 1, the current flows through T 2, D and into the base of T 3 and drives it into
saturation. The Vo ≈ 0.2 V. We note that T 1 is in its reverse active region where VBE < 0 (VB < VE ) and
VBC > 0 (VB > VC ).
 Logic Families · 23

VCC

ρRB 1.6kΩ

Rc = 2kΩ/6kΩ
(1 − ρ)RB 2.15kΩ

Vi T2 Vo
T1 D2
T3

Rb = 5kΩ

Fig. 22. The Basic DTL gate Configured as a TTL Gate

2. Consider the case when Vi = 0 (or 0.2 V). The output of the gate now goes to logic high since T 1 is saturated,
T 2 and D are off and hence T 3 is cutoff.
3. However for T 3 to get cutoff, it has to come out of saturation, pass through the active region and get to
the cutoff region. However the cutoff region cannot be reached until the stored base charge is dissipated.
Remember that this was a primary cause of a sow gate on previous occasions too. During the removal of the
base charge T 1 is saturated hence the base voltage of T 2 is Vi + VCE (sat)|T 1 = 0.2 + 0.2 = 0.4 V. This will
ensure that T 2 is cutoff.
4. As a result of the previous item, the base charge of T 3 cannot dissipate through D and T 2 since that path
is blocked with a transistor that is cutoff. Hence the charge dissipation happens through the base discharge
resistor Rb . Leaking the charge through Rb is a slow process and hence essentially constrains the speed of
switching of the gate.

7.2 Basic TTL Gate

The basic form of the TTL gate is shown in Figure 23.

VCC = 5 V

RB RC

Vo
Vi T3
T1

Fig. 23. The Basic Form of the TTL Gate

Again we analyse the states of the transistors when the input is at logic high and logic low.
24 · EN201 - Principles of Electronics

1. When the input Vi is at logic high T 1 will be in the reverse active region since VBE < 0 and VBC > 0. The
the current will flow from VCC through RB and then through the forward biased C-B junction of T 1 and into
the base of T 3 to saturate it. The output of the gate is thus Vo = VCE (sat))|T 3 = 0.2 V.
2. Now consider when the input voltage Vi drops to logic low (0.2 V). VBE > 0 hence the current from the
source travels through RB , E-B junction of T 1 and then to ground. The stored charge in the base of T 3 no
longer leaks through a resistor but through the forward biased C-B junction of T 1. It quickly dissipates and
then T 3 is driven into cutoff. Then Vo ≈ 5 V.
3. We additionally do a computation to see what happens at the transition state from the input going from logic
high to logic low. The difference between the DTL and TTL logic families comes in the form of operational
speeds. The speed limitation is a direct result of how fast the stored base charge is dissipated. For a DTL
gate (Figure 22) the initial discharge current is the current IRb through the resistor Rb , and it is given by
VBE (sat)|T 3 0.75
IRb = = = 0.15 mA.
Rb 5 kΩ
On the other hand for the TTL gate, the moment the input is dropped to 0.2 V T 1 is pushed to the active
region. If we assume that VBE |T 1 = 0.7 V and typically RB = 4 kΩ (Figure 23). That gives
VCC − VBE 5 − 0.7
IB |T 1 = = ≈ 1.1 mA.
RB 4
Since the transistor T 1 is in the active region, even if we assume a nominal value HF E = 20 for this transistor,
the collector current will be
IC |T 1 = hF E IB |T 1 = 20 × 1.1 = 22 mA.
It is obvious that the available base storage discharging current for a TTL gate is very much higher than the
initial base storage discharging current of a DTL gate. This makes the TTL gate faster.

7.3 Fabrication of the Input Transistor

A multiple emitter transistor fabrication and its symbol is given in Figure 24.
Base

EA n

EB n Collector

EC n

Fig. 24. Multiple Emitter Transistor

The operation of the multi-emitter transistor was explained above. Its operation simulates a AND gate. If
one of the inputs to the transistor emitters is at logic level 0, the transistor is in saturation and the output is at
the low level. If all of the inputs to the emitters is at logic level high, then the transistor is in the reverse active
region and the output is at high level. When this transistor is used as the input transistor in Figure 23 we will
have a NAND operation.

7.4 The Multi-Emitter TTL Gate

The multi-emitter configuration of the TTL gate is given in Figure 25.
We now look at the loading effects of the TTL gate. When the input to the gate is at logic level 1, T3 is in
saturation and T1 in the reverse active region.
 Logic Families · 25

VCC = 5 V

RB RC

Vo
VA T3
T1
VB
VC

Fig. 25. Multiple Emitter TTL Gate