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Published in IET Circuits, Devices & Systems

Received on 27th February 2008
Revised on 31st May 2009
doi: 10.1049/iet-cds.2008.0244

ISSN 1751-858X

Geometric centre tracking of tagged objects

using a low power demodulation smart
vision sensor
M. Habibi M. Sayedi
Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan, Iran
E-mail: mhdhabibi@gmail.com

Abstract: In this study, a modulated light detecting smart CMOS image sensor is presented. The design has the
ability to sense asynchronous signals transmitted from electronic markers such as flashing light emitting diodes
(LEDs) tagged on moving objects. The geometric centre of the detected region is returned as the output result.
With the presented sensor, object localisation and position detection functions are simplified, performed at
higher speeds in real time and power requirement is reduced. The sensor in-pixel processing filters out the
background image data, detects the modulated marker regions and projects the extracted region on the two
axes, while the geometric centre extraction units placed at each axis identify the coordinates assigned to the
marker. The design presents less sensitivity to object texture compared with techniques based on edge
extraction or binarisation. The sensor has been designed as a 64  64 pixel VLSI CMOS chip in the 0.35 mm
standard CMOS technology and analysed in the presence of mismatches and noise. Issues such as sensor
array scalability, speed and power dissipation are also examined in this study and features of the sensor are
reported and compared with some previous designs.

1 Introduction processing speed. For region identification and extraction

In many machine vision algorithms, it is required to identify
a specific region of the image data and to extract some
properties of the region (location for example) for further
processing [1]. Human motion capturing and robot
location tracking using special image markers, 3D profile
acquisition using laser scanners and unmanned flying
vehicle (UAV) positioning are some samples of these tasks
[2 – 4]. Conventionally, high-speed image sensors and
DSP processors are used in hardware implementation. The
sensor – processor combination requires additional external
hardware such as storage elements and controllers and thus
the overall processing power usage is usually high. An
alternative approach is the use of smart CMOS image
sensors where some or all of the processing is performed
inside the sensor [5, 6]. With elimination of external data
bus and additional hardware, the power usage can be
considerably reduced. Furthermore, it is possible to perform
some of the operations in-pixel and thus increase the
algorithms, some smart image sensors with in-pixel
processing capabilities have been previously reported. The
sensors presented in [7, 8] assume that the desired target is
the maximum intensity in the image and seek for the peak
brightness in a certain search window. In these techniques,
an object with the highest local intensity can be tracked.
However, since the highest local maximum feature is not
unique in an environment, one could be confused with
another. In [9] an image template matching sensor is
presented. The sensor identifies places in the image that
match a specific template. Since the camera or object
movement changes the pattern of the object captured
by the sensor, the applications of this sensor are limited.
Image binarisation has also been used in smart CMOS
image sensors for object tracking [10, 11]. Similarly, the
tracking process will face difficulties in this method, if
the object texture is close to the background. There have
been smart CMOS sensors presented that are capable of
detecting light signals modulated at a specific frequency

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[12 – 14]. A flashing LED mounted on an object will produce
a bright spot in the sensor focal plane. In these sensors, only
the modulated signal is extracted and all other components of
the captured scene are omitted, by which essentially light
filtering is performed. With the determination of the
modulated spot location, the coordinates of the actual
object can be obtained. Owing to ultra-low currents of
photodiodes, demodulation techniques are used in these
sensors to detect the desired signal [15, 16]. The drawback
of the sensors is requirement of a synchronous signal and
hence an external link, for the demodulation procedure. In
[17] a demodulation technique which eliminates the need
for the synchronous link has been reported, but the
procedure is not suitable for in-pixel signal detection. The
sensor presented in [18] uses asynchronous serial code
reception to identify modulated tags. Owing to long digital
codes used for synchronisation and adaptive background
signal elimination elements, the frame rate is relatively low.
In this paper, an image demodulation CMOS image
sensor which eliminates the need for an external
synchronisation link is presented. For this purpose, the
in-pixel orthogonal demodulation technique is introduced
and its circuit structure is presented. With the modulated
signals detected in-pixel, the region is projected on the x
and y axes and the geometric centre detectors on each axis
extract the coordinates of the marker.
In Section 2, the synchronous demodulation concept
which is used in electronic light filtering will be explained.
The proposed in-pixel orthogonal demodulation method is
introduced in Section 3, and in Section 4 the smart sensor
structure including the array of pixels and the geometric
centre detection units is presented. Sections 5 and 6
provide the sensor analyses and simulation results,
respectively. In Section 7, conclusions are presented.
2 Synchronous filtering pixel
In CMOS image sensors, direct processing of image data
encounters some difficulties. The reason is related to the
ultra-low currents produced at the photodiodes due to the
received radiation. At normal illumination levels, the
Figure 1 Basic operation principle of synchronous demodulation technique
a Synchronous demodulation circuit. The photodiode is replaced by a light dependent current source and equivalent node capacitance [14]
b Output result of a synchronous demodulation procedure
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amount of photocurrent is in the order of a few pico
amperes, which places the processing switches in
subthreshold region and also introduces long time
constants. Amplification of photocurrent will not help since
generally, the photocurrent noise itself is relatively high
and it will be amplified too. The solution used in the
synchronous demodulation method, for the implementation
of an electronic bandpass filter, is the use of correlation
technique by multiplication of sensors output currents in a
synchronous reference signal, followed by an integration
step. With this procedure, not only the output signal
amplitude can be increased but also because of the
bandwidth limitation imposed by the integration capacitor,
the effective noise amplitude is limited. Fig. 1 shows the
circuit used for this technique. The two switches Q1 and
Q2 integrate the photocurrent on either C1 or C2
capacitors. The final output result is the voltage difference
between the two integrating capacitors; hence, the two
switches act as a multiplier, scaling the photocurrent by
factors of þ1 and 21.
Approximating the photocurrent and the switch reference
gate pulses with sinusoid waveforms, in the conditions of
having the reference signal coherent with the photocurrent,
the differential output waveform is as follows
ð tint
1
Vout2  Vout1 ¼ [(Iback þ Isig sin(vt)) sin(vt)]
Cint 0
Isig Iback (1  cos(tint v)) Isig sin(tint v)
¼ tint þ þ
2 v 2v
Isig
! Vout2  Vout1 jtint ¼tn ¼2pn=v¼nT ¼ (nT )
2
(1)
in which Isig is the photocurrent amplitude, Iback is the
background photocurrent, T is the period of photocurrent
and reference signals, v equals 2p/T, tint is the integration
duration and n is an integer value related to the sample
iteration. In this equation, it is assumed that the integration
capacitors are far bigger than the photodiode capacitor and
that the input signal frequency is much lower than the
circuit time constant. To omit additional harmonics, the
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output differential voltage should be sampled at nT intervals
(synchronous with the reference signal).
Equation (1) shows that the output signal amplitude can
be increased by increasing tint , and that the output term is
proportional to the amplitude of the input photodiode
signal with angular frequency v and there is no relationship
with the background component. Thus, the background
illumination is filtered out and the modulated light
component remains. If the reference signal and the
photocurrent are not coherent, then (1) will not hold. For
example, if the reference signal is 908 out of phase in
relation with the photodiode signal, then the output result
sampled at nT will be zero.
Fig. 2 shows the structure required for the asynchronous
filtering procedure that consists of two demodulation
circuits. The two piecewise pulses F1 and F2 are 908 out
of phase. It is also assumed that the two photodiodes are
closely placed and thus their photocurrents are the same.
The circuit operation in the four different phases is as
follows: In phase 1 photocurrent is integrated on C1 and
C3, in phase 2 on C1 and C4, in phase 3 on C2 and C4
and finally in phase 4 on C2 and C3. The differential
output results are Vs ¼ Vc1 2 Vc2 and Vc ¼ Vc3 2 Vc4 . In
this case, the final asynchronous demodulation result can
be expressed as
Vout ¼ jjVc j þ jVs jj ¼ jjVc3  Vc4 j þ jVc1  Vc2 jj (3)

The main disadvantages in Fig. 2 are the requirement of

3 Proposed asynchronous
filtering pixel
To alleviate the problem of reference signal synchronisation
and the need for an external link, an asynchronous
demodulation technique is proposed. In this technique, two
orthogonal signals sin(vt) and cos(vt) are used in the
demodulation procedure to produce two differential output
signals Vs and Vc. Using these two values, the asynchronous
output result can be obtained as follows:
two closely spaced photodiodes, the charge sharing of the
integration capacitors through the photodiode capacitor and
the number of capacitors required for integration.
In [17] an alternative approach is used to evaluate Vout
using a single demodulation circuit where Vc and Vs are
extracted in two different but consecutive integration cycles.
With this method, the in-pixel extraction of the output
demodulation result is difficult to implement and
furthermore the maximum frame rate is halved.

ð nT For a practical in-pixel implementation of the

1
Vs jtint ¼nT ¼ [(Iback þ Isig sin(vt þ f)) sin(vt)] asynchronous demodulation circuit, it is noted that (3) can
Cint 0
be rewritten as
Isig
¼ (nT ) cos(f)
2 Vout ¼ max(j(Vc3 þ Vc1 )  (Vc4 þ Vc2 )j, j(Vc3 þ Vc2 )
ð nT
1  (Vc4 þ Vc1 )j) (4)
Vc jtint ¼nT ¼ [(Iback þ Isig sin(vt þ f)) cos(vt)]
Cint 0

Isig According to (4), two complementary demodulation

¼ (nT ) sin(f) sequences are possible, where among the two, the one
2
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi I producing the absolute maximum should be considered as
! Vout ¼ Vc2 þ Vs2 ¼
sig
(nT ) (2) the result. Since the integration capacitors are all equal thus
2 in each sequence, the states that integrate photocurrent

Figure 2 Double section demodulation circuit required for asynchronous filtering and corresponding control waveforms
and phases

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on capacitors with identical signs can be combined into
one integration cycle and states in which integration is
performed on capacitors with opposite signs can be
transferred to a no operation phase (NOP). The circuit
used for this purpose is shown in Fig. 3. The demodulation
circuit is modified to perform the different phases shown
in Fig. 3a, for the two possible complementary sequences.
Among the results obtained from the two sequences, the
greater absolute one is acceptable. If the signal is to be
demodulated using the first sequence of (4), then in phase
1, since the voltage integrated on C1 and C3 is eventually
summed up, it can be converted into a single integration
on C1. Demodulating the photocurrent signal using the
second sequence results in a ‘no operation’ in phase 1, since
the voltages produced on C1 and C3 in the second
sequence of (4) are subtracted from each other and they
cancel each other out. The states in other phases are
obtained similarly.
In the NOP phases, where both Q1 and Q3 are off, switch
Q2 connects the photodiode node to a constant voltage.
Without the Q2 switch, the photocurrents charge would
be temporarily integrated on the photodiode node and upon
the switching of the transfer switches, it would be integrated
on the integration capacitors. Furthermore, this switch
eliminates the charge sharing between the two integration
capacitors through the photodiode node and limits charge
sharing to the integration capacitors and a constant voltage.
Figure 3 The proposed asynchronous filtering pixel
a Modified asynchronous demodulation circuit and the in-pixel detector. The detector is activated if the absolute voltage difference
between the integration capacitors exceeds a threshold
b Corresponding control waveforms and phases of the proposed technique
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The absolute difference detector in Fig. 3b is used in-
pixel to detect the absolute difference of the obtained
result for each sequence and compare it with an
appropriate threshold. As it can be seen in the figure, the
differential pair is used to produce differential voltage on
one node and its negative value on the other node. If any
one of these voltage levels is capable to turn either Ma or
Mb on, this means that the absolute voltage difference
between the two integration capacitors has exceeded a
threshold value. Hence the output will be connected to
Vref2 by the Ma –Mb NOR gate, which identifies that
modulated light has been detected. To reduce power
dissipation, the detector is only momentarily turned on
at the end of each demodulation cycle. In practice, the
demodulation procedure needs not to be performed
in two different sequences at all cycles, instead the
demodulation is performed using one sequence; if the
modulated light is detected, the output of the absolute
detector will turn low. Consequently, if the output
remains high after the appropriate integration time, the
other sequence is applied immediately after the first one.
Should the output remain high, it is inferred that no
modulated signal exist in the scene and demodulation
continues with the complement sequence until a
modulated signal is detected. When a modulated marker
is found, the demodulation continues with the same
appropriate sequence. Eventually because of the slight
frequency difference between the modulated signal and
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the reference signal, the modulated signal will not be

identified in one cycle. At this point, the operation will
continue using the complement sequence and the
modulated signal tracking continuous.

4 Sensor structure
4.1 Overview
Fig. 4 shows the structure of the asynchronous filtering
smart sensor. A two-dimensional array of modulated light
detecting pixels constructs the sensor focal plane. The
clock phase signals are common among the pixels. The
surrounding scene is focused onto the focal plane using a
lens. An object tagged with a flashing LED will cause a
region on the two-dimensional array generate modulated
photocurrent signal. The region on the focal plane where
the LED light shines is related to the object actual
position by a mapping known as the camera matrix. By
identifying the region which receives the modulated light
signal, the location of object can be identified. In every
integration cycle, the detector output of each pixel will
be activated if modulated light is received by the pixel
photodiode. A row access method allows the pixel
detector results to be read out one row at a time. Owing
to the in-pixel detectors, it is possible to project the
region that receives modulated light on to the horizontal
and vertical axes. Projection on the horizontal axis is
possible by simply accessing all the rows at the same
time. In this situation, the decoder’s outputs on each
column are logically summed (OR function) and a 1 bit
logical projection of the region which has been
illuminated by modulated light is obtained on the
horizontal axis. Similarly for projection on vertical axis, a
series of column access lines are implemented in the
sensor. By simultaneous selection of the column access
lines the region will be projected on the vertical axis
using an OR function. The projection method
reduces the data required to be transferred to the sensors
periphery. The actual position assigned to each region
is obtained by two coordinate generation blocks
located at the periphery and the x and y axes. Their
function is to find the geometric centre of the projections
at each axis.

Figure 4 Structure of the asynchronous filtering sensor

4.2 Coordinate generators
The coordinate generator is shown in Fig. 5a for the
64  64 pixel sensor. Inputs In0 – In63 of the coordinate
generator are connected to the outputs of the projection
access gates in the basic pixel array. Outputs Out0 –
Out63, which represent the centre coordinates, are
connected to an encoder and outputted at the chip pins.
The coordinate generator block in Fig. 5 operates by
finding the edges of the projection in the first stage. The
two edges are then shifted right and left using two shift
registers. The location where two edges meet is the
centre point of the projection. When the centre point is
a Proposed sensor structure
b Decomposition of sensor structure to the vertical projection
switches
c Horizontal projection switches
found, the clock pulse of the shift registers (Aux_Clk)
is disabled to stop the shifting. On the next cycle of
the activate signal (new image frame), the procedure is
repeated. The shift register clock frequency must be such
that a centre point is found before the new cycle begins.
During the centre finding procedure, the size of the

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Figure 5 The coordinate generator

a Structure of the coordinate generator
b Coordinate generator timing sequence

segment can also be extracted by counting the number of 5 Sensor analyses

shift register clock cycles required to generate the centre
detected signal (Ack). The timing waveforms required to
control the coordinate generator are shown in Fig. 5b.
4.3 Sensor layout
The layout design of the sensor is performed in a 0.35 mm
standard CMOS technology. Fig. 6 shows the complete
layout design and the layout of one individual pixel.
In this section, the parameters that effect the sensor
operation, the sensor limitations and scalability and power
dissipation tradeoffs are presented.
5.1 Mismatch and noise analyses
The demodulation procedure and the absolute difference
detection of the proposed pixel is effected by several

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Figure 6 Layout design of the proposed sensor
a Layout of the complete design
b Layout of the basic pixel
parameters such as integration capacitor mismatches, switch
mismatches, supply voltage variations, random noise,
variations in background illumination, temperature
variations and the frequency error present in the modulated
markers frequencies. These effects can change the output
result of the demodulator section and also the threshold
value of the absolute difference detector. In order for the
sensor to operate correctly, the detector’s maximum
threshold activation voltage should be lower than the
minimum voltage produced by the demodulator section in
the presence of a detectable modulated light signal. On the
other hand, the detector’s minimum deactivation voltage
should be higher than the maximum voltage produced by
the demodulator section in the absence of modulated light
at the specific reference frequency. The result of mismatch,
noise and temperature variation analyses using Monte
Carlo and noise simulations is shown in Fig. 7. As the
graph shows, a modulated photocurrent of 10 pA produces
100 mV output on the demodulator in the absence of
parameter variation. Considering the overall voltage change
on the absolute difference detector and the demodulation
section output, a threshold voltage level of 60 mV can be
used to detect modulated photocurrent signals with
amplitudes as low as 10 pA. Since each pixel’s current-
Figure 7 Effect of different factors on the detector threshold voltage and the demodulator output
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to-light intensity ratio is equal to 15 pA/W/m2, the
sensitivity (minimum detectable modulated light intensity)
is equal to 0.6 W/m2.
5.2 Sensor dynamic range
The maximum amount of background illumination, which
can be handled by the sensor, is limited by the integration
capacitors discharge rate. With background illumination,
the integration capacitors discharge at a constant rate and
the common voltage of the difference detector decreases.
The minimum acceptable voltage for the difference
detector is approximately 1 V, thus the capacitors voltage
can change from the precharge voltage (2 V approximately)
to the detectors minimum common mode voltage. A rough
expression for the maximum background illumination will
thus be in the form
Iback max Dtmax
¼ DVmax (5)
2Cint
where DVmax ’ 1 V, Dtmax ’ 5 ms and Cint ’ 100 fF,
thus Iback_max ’ 40 pA. As a result, the dynamic range
of background illumination is approximately equal to
2.4 W/m2.
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5.3 Sensor tracking speed and
resolution limitation
A square target region with n  n pixels expansion and
acceptable modulated illumination can move with a speed
of n pixel per 5 ms without being lost, since in each
Figure 8 Frequency response of the presented pixel
Figure 9 Differential demodulated signal output variations with phase
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integration cycle, there exist a group of pixels that
receive modulated light in the entire procedure and enough
voltage is accumulated on the integration capacitors to
activate the detector. When the object is moving during
the integration cycle only some pixels complete the
entire demodulation procedure, thus the error of the sensor
is 1 pixel when object is stationary and n pixels when
moving. The situation is illustrated in the simulation
results section. If an m  m metre field of view is focused
on the 64  64 pixel chip focal plane, the 1 pixel error
will be equivalent to m/64 metre object position error on
each axis.
5.4 Structure scalability
The sensor array can be scaled to either widen the field of view
or to increase the tacking resolution (as mentioned earlier the
tracking error is equal to m/q metre, for an m  m metre field
of view focused on a q  q pixel chip focal plane).
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The power consumption in an m  m pixel sensor is noise voltage level increase with a root function relationship
roughly expressed with (6) with time [19].

Pdiss ¼ m2  ðVref
2 Fig. 9 shows the simulation results for the two
1 Cint  f þ Vref 1 Imean
complementary sequences demodulating a light signal with a
Pcmp ton frequency same as the reference signal but with an arbitrary
þ þ Pgen Þ þ Petc (6)
5 ms phase difference. The differential voltage of the integration
capacitors is considered as output in the figures. In row (a),
where Vref1 ’ 2 V, f is equal to the integration frequency the output is plotted against time while the phase difference
(200 Hz), Imean is the average photodiode current, Pcmp is is varied from 08 to 908. As it can be seen, after an
the static and dynamic power dissipation of one detector appropriate integration time (5 ms), using the first sequence,
unit, ton is the time required for the detectors to be the absolute value of the result produced at the output is
activated (20 ms), Pgen is the dynamic power dissipation
of one coordinate generator cell (the static dissipation is
negligible in this case) and Petc is other sources of power
dissipation (I/O pads, routings etc.). The first term of
Pdiss is due to the dynamic power dissipation of the
demodulator capacitances, the second term is related to
the power usage of the photodiodes, the third term is
related to the power usage of the comparators which
should be on for ton second in each clock cycle (5 ms).
The fourth term is related to the coordinate generator.
Although the number of coordinate generator cells
increases linearly with m but the frequency of this unit
should also increase with m to find the centre of the
projections in the appropriate time, thus the power usage
of this unit scales with m 2.

Simulation results show that the main contributions are

the power dissipation because of Imean and Pcmp , and the
power usage increases with the sensor array size.

6 Simulation results
To show the functionality of the proposed technique, the
circuits are implemented in a 0.35 mm standard CMOS
technology and the post-layout extractions are used in
the simulations. Owing to charge sharing effects, the
demodulation frequency is chosen 2.5 kHz. The radiation
striking the photodiode contains two components: one is
background illumination and the other is modulated
light. In moderate outdoor illumination, the amount of
photocurrent produced in each photodiode is roughly 10 pA.

The frequency response of the designed asynchronous

in-pixel filter is shown in Fig. 8. In the figure, the output
is plotted against the modulated signal frequency. The
output is considered as the maximum of the two absolute
results produced by the two complementary sequences. The
reference signal frequency remains constant and equal to
2.5 kHz. As the figure shows the peak output is produced Figure 10 Chip simulation results
for modulated signals with frequency of 2.5 kHz and drops a Test image data used to simulate modulated tag detection
sharply at other frequencies. during motion
b Sequence frames during a single 5 ms demodulation cycle
c Result of the demodulation and modulated region detection
Noise analyses show that signal-to-noise ratio is increased after the 5 ms demodulation cycle
during the integration process. This is due to the fact that the d Sensor y-axis digital output
signal level increases proportionally with time, whereas the e Sensor x-axis digital output

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relatively constant and does not vary with the change of phase, produced at the capacitor nodes decreases from a certain
whereas the result produced in the second sequence changes threshold the other sequence should be applied.
with phase. In row (b), phase difference is varied from 908
to 1808. In this case, an inverse situation takes place and the For the purpose of overall chip simulation, the
output remains constant using the second demodulation photocurrent produced in the photodiodes is modelled by
sequence. In row (c) the output is plotted against phase a time-dependent current source. The waveforms of the
difference for the integration time of 5 ms. When the result current sources are obtained from an illumination netlist
is constant for a specific phase range using one sequence, it file, which is created by custom software. The software
will be changing in that range using the other sequence. As converts the image sequences to the amount of illumination
explained earlier, it is not necessary to constantly striking each photoreceptor. Simulation is performed by
demodulate a signal using both sequences. Instead one merging the main circuit netlist with the illumination
sequence should be used, and if the absolute output netlist obtained from the image sequence. A test image
sequence captured for simulation is shown in Fig. 10a
where a two-dimensional arm moves across the plane in
both x and y directions. Fig. 10b shows part of the
Table 1 Proposed asynchronous pixel and sensor sequence during a 5 ms demodulation cycle. The LED
specifications flashes as it moves a few pixel across the scene during the
5 ms integration time. The result of the demodulation and
process 0.35 mm 2-poly, 3-metal, modulated region detection after the 5 ms integration is
standard CMOS shown in Fig. 10c where only the pixels constantly
chip die size 3 mm  3 mm illuminated with modulated light have been detected. In
Figs. 10d and 10e, the digital output of the sensor is shown
number of pixels 64  64 for the complete image sequence.
maximum frame rate 200 frames/s
The specifications of the proposed pixel and the sensor are
maximum Reference 2.5 kHz shown in Table 1. The presented structure is also compared
frequency with some of the present designs in Table 2. The main
pixel maximum power 0.8 mW/pixel advantages of the chip are its low power consumption
usage because of low clock frequency processing, high sensitivity
because of the long integration period used in the
pixel average power 30 nW/pixel demodulation procedure, no requirement for a
usage synchronisation link and the ability to obtain the
pixel fill factor 25% coordinates of the marker without any external processors.

pixel modulated light 0.6 W/m2

sensitivity 7 Conclusions
2
pixel background 2.3 W/m A low power, modulated marker tracking sensor was
dynamic range designed in a 0.35 mm standard CMOS technology. The
sensor average power 190 mW sensor can act as an electronic bandpass filter that omits
usage all background illumination light while detecting the
modulated signal source. As a simple application, the

Table 2 Comparison of the proposed sensor with some previous designs

Sensor Tech, mm Tracking technique Array size Speed, FPS Accuracy, pixels Power, mW
[7] 0.6 local peak tracking 11  11 10 k 0.1 —
[11] 0.5 binarisation 64  64 1k 1 112
[10] 0.18 binarisation 80  80 1k 0.1 30
[8] 0.8 global peak tracking 20  20 3k 0.013 15
[18] 0.35 direct code reception 128  128 30 1 682
[13] 0.6 synchronous demodulation 64  64 — 1 —
[15] 0.6 synchronous demodulation 120  110 2k 1 250
this work 0.35 asynchronous demodulation 64  64 200 1 0.2

76 IET Circuits Devices Syst., 2010, Vol. 4, Iss. 1, pp. 67– 77

& The Institution of Engineering and Technology 2009 doi: 10.1049/iet-cds.2008.0244

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location of the modulated signal on a two-dimensional array
of pixels can be used to determine the position of the object
carrying the modulated light tag. Unlike previous designs, no
addition link is required for signal synchronisation. The
modulated light detection procedure is performed in-pixel,
which holds the potential for in-pixel data processing and
data bandwidth reduction, suitable in distributed sensor
network configurations. The functionality and analyses of
the proposed technique is shown in the 0.35 mm CMOS
technology.
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& The Institution of Engineering and Technology 2009