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Shushanik Karapetyan
1st year PhD Student
Synopsys Armenia Educational Department,
State Engineering University of Armenia
Moscow
March 23, 2011
Logic simulation
Formal Verification
Physical Synthesis
Signoff
Power-aware verification
Formal Verification
needed to reveal power
Related bugs
Physical Synthesis
D Q Leakage
Clock Gating EN
CG
FF Multi-threshold
Clk Delay
Clock Gate Low-Vth Std-Vth High-Vth
OFF
0.9V
Power gating 0.9V Multi Voltage
0.9V 0.9V 0.7V 0.9V
Hardware
Description
Languages - + +
(Verilog, VHDL, etc.)
Vendor –Specific
Formats + - -
UPF + + +
A 0.9V
Periphery Power Domain
0.9/OFF
OFF
Supply Network
•iso
LS
LS
B C
LS
0.7V/1.2V 0.9V
LS
Operation Scenario
(OFF, 0.9V, 0.7V)
(0.9V, 0.9V, 1.2V) MV with power gating
VDDA
A 0.9V
VDD
VDDB VDD
0.9/OFF
Control
RR
VDDV
OFF
VSS
•iso
LS
LS
B
VDDA LS C
0.7V/1.2V 0.9V VDD
VDDB LS
VSS VSS
VSS
UPF
VDDA
A 0.9V Power Power
VDD
VDDB VDD Domain State
0.9/OFF
A 0.9/OFF
RR VDDV
OFF B 0.7/1.2
VSS
C 0.9
•iso
LS
LS
LS
Control
B
VDDA LS C
0.7V/1.2V 0.9V VDD
VDDB LS
VSS VSS
VSS
UPF
VDDA
A 0.9V Supply Voltage Power
VDD
VDDB VDD Net Level (V) Domain
0.9/OFF
VDD 0.9 C
RR VDDV
OFF VDDA 0.7 B
VSS
VDDB 1.2 B
•iso
LS
LS
VSS
UPF
VDDA
A 0.9V Required Periphery
VDD
VDDB VDD
0.9/OFF Level Shifters between A and B
RR VDDV Level Shifters between B and C
OFF
VSS Isolation between C and A
•iso
LS
LS
LS
Control Control Block inside A
B
VDDA LS C
0.7V/1.2V 0.9V VDD
VDDB LS
VSS VSS
VSS
UPF
VDDA
A 0.9V A B C Scenario
VDD
VDDB VDD
0.9/OFF 0.9 0.7 0.9 Allowed
RR VDDV 0.9 1.2 0.9 Allowed
OFF
VSS OFF 0.7 0.9 Allowed
•iso
LS
LS
LS
Control
B
VDDA LS C
0.7V/1.2V 0.9V VDD
VDDB LS
VSS VSS
VSS
•Modifications to low-power
Gate Level + Physical circuit structures
PG Gate Level UPF
PD boundary
Block PD primary
power net
Power Switch
• Special cells
• Special versions of library
• Characterization in additional corners
• Additional views/files/attributes
Contains 340 cells, cell list compiled based on the requirements for educational
designs
Typical combinational and sequential logic cells for different drive strengths
Typical combinational and sequential Special cells for different styles LPD
Flip-Flops Retention
Inverters/Buffers Logic Gates Isolation Cells Level Shifters
(regular+scan) Flip-Flops
Physical Always-on
Latches Delay Lines Clock gating Power Gating
(Antenna diode) Buffers
1.2
LS
LS
LS
LS
LS
0.9 0.7
LS
Level Shifters
D Q D Q
VSS VSS
Logic Symbol of Low to High Level Shifter Logic Symbol of High to Low Level Shifter
Low to High Level Shifter Truth Table High to Low Level Shifter Truth Table
0 0 0 0
1 1 1 1
VDDH VDDL
VS VS
S S
VDDL VDDH
High-to-Low Low-to-High
VDDH High
voltage
areas
Low voltage
area
VDDL
H
High
voltage
areas
VDDH
0.9
0.9 OFF/0.7
Isolation Cells
D D
Q Q
ISO ISO
Hold 0 Isolation Cell (Logic AND) Truth Table Hold 1 Isolation Cell (Logic OR) Truth Table
D ISO Q D ISO Q
0 1 0 Bypass 0 0 0 Bypass
1 1 1 mode 1 0 1 mode
X 0 0 X 1 1
Output clamped
0.7 – 1.08
0.9 OFF/0.7
Always on cells
VDDG
INP Z
VDD local
(on/off)
VSS
Always-on
Isolation Cells
0.7
0.9 OFF/0.7
D D
Q
Q
ISO
ISO
VSS VSS
Logic Symbol of Clamp 0 Isolation Cell Logic Symbol of Clamp 1 Isolation Cell
(Logic AND),Always On (Logic OR), Always On
Hold 0 Isolation Cell (Logic AND) Truth Table Hold 1 Isolation Cell (Logic OR) Truth Table
D ISO Q D ISO Q
0 1 0 Bypass 0 0 0 Bypass
1 1 1 mode 1 0 1 mode
X 0 0 X 1 1
Output clamped
Always on supply
Always on area
0.9 OFF/0.7
ENB ENB
LSUPEN
D Q Q
D
VSS VSS
Symbol of Low to High Level Shifter Symbol of High to Low Level Shifter
Active Low Enable, Clamp 0 Active Low Enable, Clamp 1
Output clamped
High
voltage
areas
VDDH
RR RR RR
CTR
1.08V/OFF
1.08V/OFF
0.7V sleep
0.9V
RR RR RR
CTR
1.08V/OFF
1.08V/OFF
0.7V sleep
0.9V
Power Gates
• Retention Register - preserve
status while the logic is turned off
• Coarse Grain - Power Gates
(switch cells)
VDDG VDDG
VDD VDD
SLEEP SLEEP
SLEEPOUT
Logic Symbol of Header Cell Logic Symbol of Header Cell(with SLEEPOUT output )
Header Cell Truth Table Header Cell (with SLEEPOUT output) Truth Table
0 1 1 0 1 1 0
1 1 hi-z 1 1 hi-z 1
100%
FF 80%
FF
60%
40%
FF 20%
Critical
Path 0%
Low-Vth Std-Vth High-Vth
FF
FF Leakage Delay
Multi-Vth libraries
AL BL CL Low Vth
AS BS CS Std Vth
AH BH CH High Vth
slew
Input Slew 0.7
slew
0.7 0.5 Process: Fast
slew Temp: 125o
0.7 0.5 Voltage: 1.32v
0.2
Iout 0.5 0.2 Process: Slow
0.1
Temp: -40o
0.2 0.1 .023 .047 .065 .078 .091 Voltage: 1.08v
Cchar output cap
0.1 .023 .047 .065 .078 .091 Process: Typical
output cap
Temp: 25o
.023 .047 .065 .078 .091 Voltage: 1.2v
output cap
Process
Corner
(NMOS proc. – Temperature (T) Power Supply (V) Notes
Name
PMOS proc.)
TTNT1p20v Typical - Typical 25 1.2 Typical corner
SSHT1p08v Slow - Slow 125 1.08 Slow corner
FFLT1p32v Fast - Fast -40 1.32 Fast corner
High leakage
FFHT1p32v Fast - Fast 125 1.32
corner
SSLT1p32v Slow - Slow -40 1.32 Low temperature
SSLT1p08v Slow - Slow -40 1.08 corners
Low Voltage Operating Conditions
TTNT0p80v Typical - Typical 25 0.80 Typical corner
SSHT0p70v Slow - Slow 125 0.70 Slow corner
FFLT0p90v Fast - Fast -40 0.90 Fast corner
High leakage
FFHT0p90v Fast - Fast 125 0.90
corner
SSLT0p90v Slow - Slow -40 0.90 Low temperature
SSLT0p70v Slow - Slow -40 0.70 corners
• Always on SLEEP
4 DFFs
• Retention cells
VDD VDDG