Chapter 1

DIGITAL SYSTEMS
DESIGN, VOLUME III

DIGITAL SYSTEMS
DESIGN, VOLUME III
Latch–Flip-Flop Circuits and
Characteristics of Digital Circuits
LARRY MASSENGALE
Digital Systems Design, Volume III: Latch–Flip-Flop Circuits and
Characteristics of Digital Circuits
Copyright © Momentum Press®, LLC, 2019.
All rights reserved. No part of this publication may be reproduced, stored

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First published in 2019 by

Momentum Press®, LLC
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ISBN-13: 978-1-94944-915-0 (print)

ISBN-13: 978-1-94944-916-7 (e-book)
Momentum Press Engineering Technology Collection
Cover and interior design by S4Carlisle Publishing Services Private Ltd.,

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First edition: 2019
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Printed in the United States of America

Abstract
Working as an engineer with advanced weapon systems for more than

25 years, it was crucial to understand the fundamentals of digital systems
design development methods and combinational logic circuits. Whether as
a technician or as an engineer, these fundamentals are the basics of engi-
neering and are essential in interpreting logic gate functionality. The intent
of this book is to provide much more information than most commercial
engineering references currently offer. Chapter 1, Latch and Flip Flop
Circuits, discusses fundamental operations of NAND gate latch, NOR
gate latch, gated S-C latch, gated D latch, four-bit bistable latch, D-type
flip flop, JK-type flip flop, and master slave JK-type flip flop circuits.
Chapter 2, Characteristics of Digital Circuits, provides a brief introduction
to circuit characteristics. This chapter discusses RC time constants, elec-
trical and dynamic behavior of circuits, timing considerations, and data
storage and transfer devices. The chapter review and answer sections con-
tain an extensive number of questions that afford comprehensive insights
into obtaining the answers. This book will be an extremely valuable asset
for technical and engineering students studying digital system design.
KEYWORDS
circuit behavior; data storage; flip flop; latch; RC time constant

Contents
List of Figures ix
List of Tables xv
Acknowledgments xvii
Chapter 1 Latch and Flip Flop Circuits 1

1.1. Introduction 1
1.2. Active Low Latch—NAND Gate Latch 1
1.3. Active High Latch—NOR Gate Latch 7
1.4. Active Low Gated Set-Clear (S-C) Latch 12
1.5. Active Low Gated D Latch 18
1.6. Four-Bit Bistable Latches 23
1.6.1. SN74LS75 24
1.6.2. SN74LS77 27
1.7. D-Type Flip Flop: Positive Edge Triggered
D-Type Flip Flop 29
1.7.1. Negative Edge Triggered D-Type Flip Flop 34
1.8. JK-Type Flip Flop: Positive Edge Triggered
JK Flip Flop 39
1.9. Master–Slave JK-Type Flip Flop 44
1.10. Chapter 1 Review Questions 49
1.11. Chapter 1 Review Answers 54
Chapter 2 Characteristics of Digital Circuits 79
2.1. Introduction 79
2.2. RC Time Constant 80
2.2.1. Charging 80
2.2.2. Discharging 84
2.3. Electrical Behavior of Circuits 87
2.3.1 Data Sheets and Specifications 87
2.3.2. Logic Levels and Noise Margins 93
viii • CONTENTS
2.3.2.1. Logic Level 93

2.3.2.2. Noise Margin 99
2.3.3. Circuit Behavior with Circuit Loads 103
2.3.4. Fan-outs 107
2.3.5. Effects of Loading 110
2.3.6. Unused Inputs 110
2.3.7. Current Spikes and Decoupling
Capacitors 112
2.3.8. Destruction of CMOS Devices 112
2.4. Dynamic Electrical Behavior 113
2.4.1. Gate Delays and Timing Diagrams 114
2.4.2. Transition Time 116
2.4.3. Propagation Delay 122
2.4.4. Power Consumption 124
2.5. Timing Considerations 126
2.5.1. Setup and Hold Times 126
2.5.2. Maximum Clocking Frequency fMAX 127
2.5.3. Clock Pulse High and Low Times 128
2.5.4. Asynchronous Active Pulse Width 128
2.5.5. Clock Transition Times 129
2.6. Data Storage and Transfer 129
2.6.1. Flip Flops Form Registers 129
2.6.2. Serial Input Serial Output (SISO) 130
2.6.3. Serial Input Parallel Output (SIPO) 133
2.6.4. Parallel Input Serial Output (PISO) 133
2.6.4.1. Shift Mode 134
2.6.5. Parallel Input Parallel Output (PIPO) 134
2.6.5.1. Bidirectional Shift Register 135
2.6.5.2. Universal Shift Register 136
2.7. Chapter 2 Review—Questions 137
2.8. Chapter 2 Review—Answers 143
Bibliography 169
About the Author 171
Index 173
List of Figures
Figure 1.1. Active low latch logic diagrams and state table 2
Figure 1.2. SET state of the active low latch 3
Figure 1.3. CLEAR state of the active low latch 4
Figure 1.4. RETAIN state of the active low latch 5
Figure 1.5. INVALID state of the active low latch 5
Figure 1.6. Active low latch used to determine waveform 6
Figure 1.7. Active low latch waveform 6
Figure 1.8. Active high latch logic diagrams and state table 7
Figure 1.9. SET state of the active high latch 8
Figure 1.10. CLEAR state of the active high latch 9
Figure 1.11. RETAIN state of the active high latch 10
Figure 1.12. INVALID state of the active high latch 10
Figure 1.13. Active high latch used to determine waveform 11
Figure 1.14. Active high latch waveform 11
Figure 1.15. Active low latch logic diagrams and state table 12
Figure 1.16. SET state of the active low gated S-C latch 13
Figure 1.17. CLEAR state of the active low gated S-C latch 14
Figure 1.18. RETAIN state of the active low gated S-C latch 15
Figure 1.19. INVALID state of the active low gated S-C latch 15
Figure 1.22. Active low gated S-C latch used to determine waveform 17
Figure 1.23. Active low gated S-C latch waveform 17
Figure 1.24. Active low gated D latch logic diagrams and state table 18
Figure 1.25. SET state of the active low gated D latch 20
Figure 1.26. CLEAR state of the active low gated D latch 21
Figure 1.27. NO CHANGE (NC) state of the active
low gated D latch (D = 0) 21
Figure 1.28. NO CHANGE (NC) state of the active low
gated D latch (D = 1) 22
Figure 1.29. Active low gated D latch used to determine waveform 22
x • List of Figures
Figure 1.30. Active low gated D latch waveform 23

Figure 1.31. SN74LS75 four-bit bistable latch logic diagrams
and state table 24
Figure 1.32. SET state of the four-bit bistable latch 25
Figure 1.33. CLEAR state of the four-bit bistable latch 25
Figure 1.34. NO CHANGE (NC) state of the four-bistable latch 25
Figure 1.35. SN74LS75 four-bit bistable latch used to determine
waveform 26
Figure 1.36. Active low gated D latch waveform 26
Figure 1.37. SN74LS75 four-bit bistable latch waveform 27
Figure 1.38. SN74LS77 four-bit bistable latch logic diagrams and
state table 27
Figure 1.39. SN74LS77 four-bit bistable latch used to determine
waveform 28
Figure 1.40. SN74LS77 four-bit bistable latch waveform 29
Figure 1.41. Positive edge triggered D flip flop logic diagrams
and state table 30
Figure 1.42. SET state for positive edge triggered D flip flop 31
Figure 1.43. CLEAR state for positive edge triggered D flip flop 31
Figure 1.44. NO CHANGE state for positive edge triggered
D flip flop (D = 0) 32
Figure 1.46. Positive edge detector circuit 33
Figure 1.47. Positive edge detector waveform 33
Figure 1.48. CLK and D inputs 33
Figure 1.49. Positive going transition D-type flip flop waveform 34
Figure 1.50. Negative edge triggered D flip flop logic diagrams
and state table 34
Figure 1.51. SET state for negative edge triggered D flip flop 36
Figure 1.52. CLEAR state for negative edge triggered D flip flop 36
Figure 1.53. NO CHANGE state for negative edge
triggered D flip flop (D = 0) 37
Figure 1.55. Negative edge detector circuit 38
Figure 1.56. Negative edge detector waveform 38
Figure 1.57. CLK and D inputs 38
Figure 1.58. Negative going transition D-type flip flop waveform 39
Figure 1.59. Positive edge triggered JK flip flop logic diagrams
and state table 39
Figure 1.60. S-C latch similarity to JK flip flop 41
List of Figures • xi
Figure 1.61. Similarity of S-C latch and JK flip flop truth tables 42
Figure 1.62. Toggling (racing) of JK flip flop (first cycle of toggling) 42
Figure 1.63. Toggling (racing) of JK flip flop
(second cycle of toggling) 43
(third cycle of toggling) 43
Figure 1.65. Waveform of JK flip flop toggling (racing) 44
Figure 1.66. JK MS flip flop logic diagrams and state table 45
Figure 1.67. JK MS flip flop clock cycles 46
Figure 1.68. JK MS latches first-half clock cycle, CLK= 1,
J = 1, and K = 0 47
Figure 1.69. JK MS latches second-half clock cycle, CLK′ = 1,
QM = 1, and QM′ = 0 47
(first cycle of toggling) 73
(second cycle of toggling) 74
(third cycle of toggling) 74
Figure 1.73. Waveform of JK flip flop toggling (racing) 75
Figure 1.74. JK MS latches first half-clock cycle, CLK = 1,
J = 1, and K = 0 77
Figure 1.75. JK MS latches second-half clock cycle, Clk′ = 1,
QM = 1, and QM′ = 0 78
Figure 2.1. Initial conditions of series RC circuit charging 81
Figure 2.2. Percentage of charge versus time constant 82
Figure 2.3. Charging capacitor voltage versus time constant 82
Figure 2.4. Charging capacitor current versus time constant 83
Figure 2.5. Percentage graph of voltage and current of charging
capacitor 84
Figure 2.6. Initial conditions of series RC circuit discharging 85
Figure 2.7. Discharging capacitor voltage versus time constant 85
Figure 2.8. Discharging capacitor current versus time constant 86
Figure 2.9. Percentage graph of voltage and current of discharging
capacitor 86
Figure 2.10. CMOS invertor 93
Figure 2.11. CMOS invertor switch model 94
Figure 2.12. Typical CMOS inverter transfer characteristics graph 95
Figure 2.13. Five operational regions of input–output transfer
characteristics curve 95
Figure 2.14. CMOS inverter input and output noise margin
characteristics 99
xii • List of Figures
Figure 2.15. Ideal CMOS inverter input/output characteristics 100

Figure 2.16. Actual CMOS inverter input/output characteristics 101
Figure 2.17. Practical CMOS inverter input/output characteristics 102
Figure 2.18. CMOS inverter input/output noise margin
characteristics revisited 102
Figure 2.19. CMOS inverter input/output noise margin
characteristics summary 103
Figure 2.20. Static CMOS inverter load-line plot 104
Figure 2.21. CMOS inverter resistive load model: (a) shows
actual load circuit (b) using Thevenin equivalent 105
Figure 2.22. CMOS inverter resistive load with high
Vin and low Vout 105
Figure 2.23. CMOS inverter Thevenin circuit with high input
(current flow) 106
Figure 2.24. CMOS inverter Thevenin circuit with low input
(current flow) 106
Figure 2.25. Standard TTL voltage specifications 107
Figure 2.26. Current sinking 10 load gates 108
Figure 2.27. Current sourcing 10 load gates 109
Figure 2.28. Pull-down resistor for TTL inputs 111
Figure 2.29. Pull-up resistor for TTL inputs 112
Figure 2.30. Propagation delay for an inverter 114
Figure 2.31. Timing diagram of AND, OR, and NOR network 115
Figure 2.32. Timing diagram with timing delay 115
Figure 2.33. Transition times: ideal, realistic, and actual 116
Figure 2.34. Equivalent circuit with RL, VL, and CL 117
Figure 2.35. (a) Low to high state and (b) instantaneously
change to low state showing discharge 117
Figure 2.36. Capacitor discharge rate 119
Figure 2.37. Fall time between high and low Vout boundaries 120
Figure 2.38. (a) High to low state, (b) Instantaneously
change to high state showing charge 120
Figure 2.39. Capacitor charge rate 122
Figure 2.40. Rise time between high and low Vout boundaries 122
Figure 2.41. Multiple output signal paths determined by inputs 123
Figure 2.42. CMOS inverter propagation delays 123
Figure 2.43. Setup and hold times for CMOS inverter 126
Figure 2.44. Maximum clocking frequencies on various flip flops 128
Figure 2.45. Clock low and high times 128
Figure 2.46. Asynchronous pulse width 129
Figure 2.47. Block diagram for serial input serial output
(SISO) register 130
List of Figures • xiii
Figure 2.48. FF-3 set for SISO register 131

Figure 2.49. FF-3, FF-2 set for SISO register 131
Figure 2.50. FF-3, FF-2, FF-1 set for SISO register 131
Figure 2.51. FF-3, FF-2, FF-1, FF-0 set for SISO register 132
Figure 2.52. SISO register waveform with binary input (1111) 132
Figure 2.53. Serial input parallel output (SIPO) register
block diagram 133
Figure 2.54. Parallel input serial output (PISO) register
block diagram 134
Figure 2.55. Parallel input parallel output (PIPO) register
block diagram 135
Figure 2.56. Four-bit bidirectional shift register block diagram 135
Figure 2.57. Four-bit unidirectional shift register block diagram 136
Figure 2.58. Initial conditions of series RC circuit charging 143
Figure 2.59. Percentage of charge versus time constant 144
Figure 2.60. Charging capacitor voltage versus time constant 145
Figure 2.61. Charging capacitor current versus time constant 145
Figure 2.62. Percentage graph of voltage and current of
charging capacitor 146
Figure 2.63. Initial conditions of series RC circuit discharging 147
Figure 2.64. Discharging capacitor voltage versus time constant 147
Figure 2.65. Discharging capacitor current versus time constant 147
Figure 2.66. Percentage graph of voltage and current of
discharging capacitor 148
Figure 2.67. CMOS invertor switch model 152
Figure 2.68. Typical CMOS invertor transfer charateristics graph 152
Figure 2.69. Five operational regions of input–output transfer
characteristics curve 153
Figure 2.70. CMOS inverter resistive load with high
Vin and low Vout 162
Figure 2.71. CMOS inverter Thevenin circuit with high input
(current flow) 163
Figure 2.72. CMOS inverter Thevenin circuit with low input
(current flow) 163
List of Tables
Table 1.1. SET′ and CLR′ inputs over time 6

Table 1.2. State table for time increments of latch waveform 7
Table 1.3. SET and CLR inputs over time 11
Table 1.4. State table for time increments of latch waveform 12
Table 1.5. SET, CLR, and gated inputs over time 17
Table 1.6. State table for time increments of active low gated S-C
latch waveform 18
Table 1.7. D and G inputs over time 22
Table 1.8. State table for time increments of active low gated
D latch waveform 23
Table 1.9. SN74LS75 four-bit bistable D and C inputs over time 26
Table 1.10. State table for time increments of SN74LS75 four-bit
bistable latch 27
Table 1.11. SN74LS77 four-bit bistable D and C inputs over time 28
bistable latch waveform 29
Table 2.1. Characteristics of digital circuits 79
Table 2.2. Percentage of voltage and current of charging capacitor 83
Table 2.3. Percentage of voltage and current of RC
discharging circuit 86
Table 2.4. Summary of electrical behavior of circuits 87
Table 2.5. Summary of regions for PMOS/NMOS devices 99
Table 2.6. Noise margin voltage levels 100
Table 2.7. Standard TTL gate voltage specifications 107
Table 2.8. Standard TTL gate current specifications 109
Table 2.9. Four modes of operations for the shift register 130
Table 2.10. SISO data words stored 132
xvi • List of Tables
Table 2.11. Percentage of voltage and current of RC

discharging circuit 148
Table 2.12. Summary of regions for PMOS/NMOS devices 156
Acknowledgments
I thank my wife for providing me with the inspiration and motivation

for writing this book. My children, Michael and Holly, were instrumen-
tal in keeping me on track to finish the text. Robert Solis, Bob Valencia,
Sean Tijerina, Mike Ormonde, Ming Ho, and Anthony Vernon, all en-
gineers working with various organizations, provided excitement in get-
ting me started on this project. Two people get my overwhelming thanks
for coaching me on. One is a brilliant engineer who works with cyber
operations, Christy Vera, and the other is my long-time professor friend,
Dr. Wei-Ming Lin, who reviewed the book with his insightful comments,
as always. Additionally, Dr. Margaret Wesner has been one of my greatest
supporters, giving me clarity, encouragement, and compassion during the
rough times I had while writing this book. Most of all, I thank the Lord
Jesus Christ for giving me the ability and knowledge to comprehend en-
gineering subject matters.
CHAPTER 1
Latch and Flip Flop

Circuits
1.1. INTRODUCTION
In Volume II Chapter 3 we discussed combinational logic circuits whose

outputs depended upon their inputs. These inputs and outputs cannot re-
tain their logic levels for future storage capability further operations. Un-
like combinational logic circuits, several digital system circuits have the
ability to store data, which requires memory capacity. These circuits are
referred to as sequential logic circuits and depend on their previous and
current state inputs. Their outputs will be tied back to their inputs in some
respect, providing the necessary feedback of their circuits. Latch and flip
flop circuits are these types of digital circuits. The latch circuit forms the
basic core for the foundation of flip flops. In this chapter we will learn
about the different types of latch and flip flop circuits.
Additionally, it is critical to understand that Transistor-Transistor
Logic (TTL) and Complementary Medal-Oxide Semiconductor (CMOS)
devices have special characteristics to prevent design flaws and damage
to chips. Many of the electrical behaviors with discrete circuits also apply
to these materials. These special characteristics will also be discussed in
this chapter.
1.2. ACTIVE LOW LATCH—NAND GATE LATCH
The active low latch has two inputs, identified as SET′ and CLR′, hence
active low latch. The latch outputs are Q and Q′. Figure 1.1 shows how one
NAND gate output feeds back to the other NAND gate input with oppo-
site polarity, the state of each input combination, the logic symbol for the
active low latch, and the active low latch waveform.
2 • DIGITAL SYSTEMS DESIGN, VOLUME III
a. NAND Gate Latch
U1
SET’ 2
1
3
OR2
U4
2
1
3
CLR’
OR2
b. Inverted OR Gate Latch
c. Active Low Latch State Table
Figure 1.1. Active low latch logic diagrams and state table
Latch and Flip Flop Circuits • 3
t0 t1 t2 t3 t4 t5
S’ Q
Set’
Clr’
Q’
C’ Q’
Q
d. Logic Symbol
e. Active Low Latch Waveform
Figure 1.1. Active low latch logic diagrams and state table (Continued )
Gate latch SET′ and CLR′ level will be explained next. As shown
in Figures 1.2to1.5, the completed aforementioned active low latch state
table is analyzed. We began with SET′ = 0 and CLR′ = 1, as shown in
Figure 1.2, where the output of logic gate G1 is a logic high or 1. This logic
1 is feedback from the output of gate G1 to the top input of logic gate G2.
This input logic 1 along with the CLR′ logic 1 will produce a logic low or
logic 0 output to logic gate G2. When the SET′ = 0 and CLR′ = 1 inputs
exist, this condition places the active low latch in a SET state as shown in
the state table in Figure 1.2.
U1
0
SET’ 2
1
3
G1 Q=0
OR2
U2
2
1
G2 1
1 3 Q’= 0
CLR’
OR2
SET' CLR' Q Q' STATE

0 1 1 0 SET
Figure 1.2. SET state of the active low latch

Next we show SET′ = 1 and CLR′ = 0 in Figure 1.3, where the output
of logic gate G1 is a logic low or logic 0. This logic 0 is feedback from the
output of gate G1 to the top input of logic gate G2. This input logic 0 along
with the CLR′ logic 0 will produce a logic high or logic 1 output to logic
gate G2. When the SET′ = 1 and CLR′ = 0 inputs exist, this condition
places the active low latch in a CLEAR state as shown in the state table in
Figure 1.3.
U1
0
SET’ 2
1 0
G1 Q=0
3
OR2
U2
0 2
1 1
0 3 G2 Q’ = 1
CLR’
OR2

0 1 0 1 CLEAR
Figure 1.3. CLEAR state of the active low latch
Next we show SET′ = 1 and CLR′ = 1. In Figure 1.4, we assume

that the latch circuit is in the SET state where Q = 1 and Q′ = 0. We can
assume that the circuit is either in the SET or the CLEAR state. In order
to explain our current input condition of SET′ = CLEAR = 1, we simple
trace back from the Q′= 0 output to the lower input to gate G1. The low
input causes gate G1′s output to retain a logic 1 output. When tracking
back from the logic 1 G1 output to the upper G2 input we have two logic
1 inputs causing the Q′ output of a logic 0. When both circuit inputs are
high or logic 1 the latch will retain the state it was in previously. We
can analyze both SET and CLEAR states of the latch circuit and deter-
mine that the latch will be in the RETAINed state. Figure 1.4 shows the
RETAIN state of the previous latch state—the previous SET state in our
example.
U1
1
SET’ 2
1
1
3
G1 Q=1
OR2
U2
2
1 0
G2 1
1 3 Q’ = 0
CLR’
OR2

1 1 1/0 0/1 RETAIN
Figure 1.4. RETAIN state of the active low latch
Finally we show SET′= 0 and CLR′ = 0 in Figure 1.5. When either

or both inputs are logic lows or logic 0s in our current case, we will obtain
logic highs at the output. Since SET′ = 0 and CLR′ = 0, both logic gates
G1 and G2 have logic high outputs at Q and Q′. With Q and Q′ outputs
both logic highs or logic 1s, the latch circuit is considered to be INVALID.
Figure 1.5 shows the INVALID state of the latch circuit.
U1
0
SET’ 2
1
1
3
G1 Q=1
1
OR2
U2
2
1 1
G2 1
0 3 Q’ = 1
CLR’
OR2

0 0 1 1 INVALID
Figure 1.5. INVALID state of the active low latch

Given Table 1.1 and Figure 1.6 we construct the waveform for the
active low latch.
Table 1.1. SET′ and CLR′ inputs over time
U1
SET’ 2
1
3
G1 Q
OR2
U2
2
1
G2 1
3 Q’
CLR’
OR2
Figure 1.6. Active low latch used to determine

waveform
Using the SET′ and CLR′ inputs we can determine the Q and Q′ out-
puts for time increment from the aforementioned information in this sec-
tion. Once we know the outputs for each time increment we can construct
the waveform shown in Figure 1.7.
Figure 1.7. Active low latch waveform

Additionally, we construct a state table providing each time incre-

ment’s state as shown in Table 1.2.
Table 1.2. State table for time increments of latch waveform
1.3. ACTIVE HIGH LATCH—NOR GATE LATCH
The active high latch has two inputs, identified as SET and CLR, hence
active high latch. The latch outputs are Q′ and Q. Figure 1.8 shows how
one NOR gate output feeds back to the other NOR gate input with oppo-
site polarity, the state of each input combination, the logic symbol for the
active high latch, and the active high latch waveform.
U3 U5
SET 2
1 SET 2
1
3 Q’ 3 Q’
NOR2 AND2
U4
U6
2
1 2
3 Q 1
Q
CLR 3
CLR
NOR2 AND2
a. NOR Gate Latch and Inverted Diagram b. AND Gate Latch Diagram
c. Active High Latch State Table
Figure 1.8. Active high latch logic diagrams and state table
t0 t1 t2 t3 t4 t5
S Q
Set
Clr
Q
C Q’
Q’
d. Logic Symbol
e. Active High Latch Waveform
Figure 1.8. Active high latch logic diagrams and state table (Continued )
Gate SET and CLR input levels will be explained next. As shown in
Figures 1.9 to 1.12, the completed aforementioned active high latch state
table is analyzed. We began with SET = 1 and CLR = 0, as shown in
Figure 1.9, where the output of logic gate G1 is a logic low or 0. This logic
0 is feedback from the output of gate G1 to the top input of logic gate G2.
This input logic 0 along with the CLR logic 0 will produce a logic high or
logic 1 output to logic gate G2. When the SET = 1 and CLR = 0 inputs
exist, this condition places the active high latch in a SET state as shown in
the state table in Figure 1.9.
U3
1
SET 2
1
0
3 Q’= 0
1
NOR2
U4
0 2 1
1
0 3 Q=1
CLR
NOR2
SET CLR Q Q' STATE

1 0 1 0 SET
Figure 1.9. SET state of the active high latch

Next we show SET = 0 and CLR = 1 in Figure 1.10, where the output
of logic gate G1 is a logic high or logic 1. This logic 1 is feedback from
the output of gate G1 to the top input of logic gate G2. This input logic 1
along with the CLR logic 1 will produce a logic low or logic 0 output of
logic gate G2. When the SET = 0 and CLR = 1 inputs exist, this condition
places the active high latch in a CLEAR state as shown in the state table
in Figure 1.10.
U3
0
SET 2
1
1
3 Q’= 1
0
NOR2
U4
1 2 0
1
1 3 Q=0
CLR
NOR2
SET CLR Q Q' STATE

1 0 0 1 CLEAR
Figure 1.10. CLEAR state of the active high latch
Next we show SET = 0 and CLR = 0 in Figure 1.11. We assume that

the latch circuit is in the CLEAR state where Q = 0 and Q′ = 1. We can
assume that the circuit is either in the SET or the CLEAR state. In order
to explain our current input condition of SET = CLEAR = 0, we simply
trace back from the Q′= 1 output to the upper input to gate G2. The high
input causes gate G2′s output to retain a logic 0 output. When tracking
back from the logic 0 of G2 output to the lower G1 input we have two logic
0 inputs causing the Q′ output of a logic 1. When both circuit inputs are
low or logic 0 the latch will retain its previous state. We can analyze both
SET and CLEAR states of the latch circuit and determine that the latch
will be in the RETAINed state. Figure 1.11 shows the RETAIN state of the
previous latch state—the previous CLEAR state in our example.
U3
0
SET 2
1 1
3 Q’= 1
0
NOR2
U4
2
1 0
1
0 3 Q=0
CLR
NOR2

0 0 1/0 0/1 RETAIN
Figure 1.11. RETAIN state of the active high latch
Finally, we show SET = 1 and CLR = 1 in Figure 1.12. When either

or both inputs are logic highs or logic 1s in our current case, we will obtain
logic lows at the output. Since SET = 1 and CLR = 1, both logic gates
G1 and G2 have logic low outputs at Q and Q′. With Q and Q′ outputs
both logic lows or logic 0s, the latch circuit is considered to be INVALID.
Figure 1.12 shows the INVALID state of the latch circuit.
U3
1
SET 2
1
0
3 Q’= 0
0
NOR2
U4
2
0 0
1
1 3 Q=0
CLR
NOR2

1 1 0 0 INVALID
Figure 1.12. INVALID state of the active high latch

active high latch.
Table 1.3. SET and CLR inputs over time
U1
SET 2
1
3
G1 Q
OR2
U2
2
1
3
G2 Q’
CLR
OR2
Figure 1.13. Active high latch used to determine

waveform
Using the SET and CLR inputs we can determine the Q and Q′ out-
tion. Once we know the outputs for each time increment we can construct
Figure 1.14. Active high latch waveform


Table 1.4. State table for time increments of latch waveform
1.4. ACTIVE LOW GATED SET-CLEAR (S-C) LATCH
The active low gated S-C latch has three inputs, identified as SET, G, and
CLR. The latch outputs are Q and Q′. Figure 1.15 shows the gated SET and
CLR inputs, how one inverted OR gate output feeds back to the other OR gate
input with opposite polarity, the state of each input combination, the logic
symbol for the active low S-C latch, and the active low S-C latch waveform.
U1
U3
2
SET 1 2
3
3
1 Q
NAND2
OR2
U4
U2
2
2 1
1 3
Q’
3
CLR
OR2
NAND2
Steering Gates Active Low Latch
a. Active Low S-C Latch Diagram
b. Gated S-C Latch State Table

Figure 1.15. Active low latch logic diagrams and state table
t0 t1 t2 t3 t4 t5 t6 t7 t8
S Q
G
S
G
C
C Q’
Q
c. Gated S-C Latch Q’
Logic Diagram
d. Gated S-C Latch Waveform
Figure 1.15. Active low latch logic diagrams and state table (Continued )
SET and CLR input levels will be explained next. As shown in Figures
1.16 to 1.20, the completed aforementioned active low gated S-C latch state
table is analyzed. We began with SET = 1, CLR = 0, and gated input = 1, as
shown in Figure 1.16, where the output of NAND Gate G1 is a logic low or
logic 0 and the output of NAND Gate G2 is a logic high or logic 1. Gate G1 out-
put is applied to one of the inputs of Gate G3 and the Gate G2 output is applied
to one of the inputs of Gate G4. As with NAND gate inputs, the inverted OR
gate requires all inputs must be highs for the inverted OR gate to have a logic
low output. Since one of the inputs is low, we know that the output of Gate G3
must be a logic high or logic 1 output. We can trace the logic high at Q back to
the top input of Gate G4. The other Gate G4 input is also high, providing a low
output of Gate G4. We can also trace this low back to the other input of Gate
G3, where we now know both inputs to Gate G3 are low. So Q = 1 and Q′ = 0.
The S-C latch circuit provides for two steering gates for synchronization, which
are added to the active low latch circuit, forming the active low gated S-C latch.
U1
U3
1 2
SET 0
G1 1 2
1
3
3 G3
1 Q=1
0
NAND2
OR2
G 1
U4
U2
1 2
2 1 G4 1
1 3
Q’ = 0
0 G2 0
3
CLR
OR2
NAND2
Figure 1.16. SET state of the active low gated S-C latch
Next SET = 0, CLR = 1, and gated input = 1, as shown in

Figure 1.17, where the output of NAND Gate G1 is a logic high or logic
1 and the output of NAND Gate G2 is a logic low or logic 0. Since one
of the G4 inputs is low, we know that the output of Gate G4 must be a
logic high or logic 1 output. We can trace the logic high at Q′ back to the
bottom input of Gate G3. The other Gate G3 input is also high, providing
a low output of Gate G3. We can also trace this low output back to the
other input of Gate G4, where we now know both inputs to Gate G4 are
low. So Q = 0 and Q′ = 1.
U1
U3
0 2
SET 1
G1 1 2
0
3
3 G3
1 Q=0
1
NAND2
OR2
G 1
U4
U2
0 2
2 0 G4 1
1 3
Q’ = 1
1 G2 1
3
CLR
OR2
NAND2
Figure 1.17. CLEAR state of the active low gated S-C latch
Next SET = 0, CLR = 0, and gated input = 1, as shown in

Figure 1.18, where the output of NAND Gate G1 is a logic high or logic
1 and the output of NAND Gate G2 is a logic high or logic 1. We assume
that both inputs to Gate G3 are high or logic 1s. The Gate G3 output will
be a logic low or logic 0. This logic low can be traced back to the upper
Gate G4 input. Since one of the G4 inputs is low, we know that the output
of Gate G4 must be a logic high or logic 1 output. We can trace the logic
high at Q′ back to the bottom input of Gate G3. The other Gate G3 input
is also high, confirming a low output of Gate G3. So Q = 0 and Q′ = 1.
Additionally, we could have assumed Gate G4 inputs as both high inputs,
providing a low output to Gate G4. If this were the case, then Q = 1
and Q′ = 0. This agrees with the active low gated S-C latch truth table
provided earlier.
U1
U3
0 2 1
SET 1 2
G1 0
3
3 G3
1 Q=0
1
NAND2
OR2
G 1
U4
U2
0 2
2 1 G4 1
1 3
Q’ = 1
0 G2 1
3
CLR
OR2
NAND2
Figure 1.18. RETAIN state of the active low gated S-C latch
Next SET = 1, CLR = 1, and gated input = 1, as shown in Figure 1.19,

where both the outputs of NAND Gate G1 and G2 are logic lows or logic
0s. When both NAND gates are logic 0s, both outputs for Gate G3 and
G4 will be logic highs or logic 1s. When Q = Q′, our state of the circuit
is invalid.
U1
U3
1 2
SET 0
G1 1 2
1
3
3 G3
1 Q=1
1
NAND2
OR2
G 1
U4
U2
1 2
2 0 G4 1
1 3
Q’ = 1
1 G2 1
3
CLR
OR2
NAND2
Figure 1.19. INVALID state of the active low gated S-C latch
Next SET = 0, CLR = 0, and gated input = 0, as shown in Figure 1.20,

where both outputs of NAND Gate G1 and G2 are logic highs or logic 1s.
We assume that both inputs to Gate G3 are high or logic 1s. The Gate G3
output will be a logic low or logic 0. This logic low can be traced back to
the upper Gate G4 input. Since one of the G4 inputs is low, we know that
the output of Gate G4 must be a logic high or logic 1 output. We can trace
the logic high at Q′ back to the bottom input of Gate G3. The other Gate
G3 input is also high, confirming a low output of Gate G3. So Q = 0 and
Q′ = 1. Additionally, we could have assumed Gate G4 inputs as both high
inputs, providing a low output to Gate G4. If this was the case, then Q = 1
and Q′ = 0. This agrees with the active low gated S-C latch truth table
provided earlier.
U1
U3
0 2
SET 1
G1 1 2
0
3
3 G3
1 Q=0
1
NAND2
OR2
G 0
U4
U2
0 2
2 1 G4 1
1 3
Q’ = 1
0 G2 1
3
CLR
OR2
NAND2
Additionally, if SET = 1, CLR = 1, and gated input = 0, we would

have the aforementioned situation. This configuration is shown in
Figure 1.21 and also agrees with the active low gated S-C latch truth table
provided earlier.
U1
U3
1 2 1
SET 1 2
G1 0
3
3 G3
1 Q=0
1
NAND2
OR2
G 0
U4
U2
0 2
2 1 G4 1
1 3
Q’ = 1
1 G2 1
3
CLR
OR2
NAND2
active low gated S-C latch.
Table 1.5. SET, CLR, and gated inputs over time
U1
U3
2
SET 1 2
G1
3
3 G3
1 Q
NAND2
OR2
U4
U2
2
2 1
1 3 G4 Q’
3 G2
CLR
OR2
NAND2
Figure 1.22. Active low gated S-C latch used to determine waveform
Using the SET, CLR, and gated inputs we can determine the Q and
Q′ outputs for time increment from the aforementioned information in
this section. Once we know the output for each time increment we can
construct the waveform shown in Figure 1.23.
Figure 1.23. Active low gated S-C latch waveform

Additionally we construct a state table providing each time incre-

Table 1.6. State table for time increments of active low gated S-C latch
waveform
1.5. ACTIVE LOW GATED D LATCH
The active low gated D latch has two inputs, identified as D and G; how-
ever, input D is inverted at the bottom steering gate. The latch outputs are
Q and Q′. Figure 1.24 shows the gated D and G inputs, how one inverted
OR gate output feeds back to the other OR gate input with opposite polar-
ity, the state of each input combination, the logic symbol for the active low
D latch, and the active low D latch waveform.
U1
U3
D 2
1 2
3 1
Q
3
NAND2
OR2
U4
U2
U5 2
2 1 Q’
1 3
2 1 3
OR2
NAND2
NOT
a. Active Low D Latch Diagram
Figure 1.24. Active low gated D latch logic diagrams and state table
D Q
G Q’
b. Gated D Latch State
Table c. Gated D Latch
Logic Diagram
t0 t1 t2 t3 t4 t5
Q’
d. Gated D Latch Waveform
Figure 1.24. Active low gated D latch logic diagrams and state table (Continued )
The previous latch circuits all have a critical defect in their design: the
invalid state. The gated D latch is an improvement over the latches we have
discussed so far. The gated D latch eliminates the SET and CLEAR inputs
and provides one input for the D input. The ideal latch allows for a SET,
CLEAR, and RETAIN state. The gated D latch also eliminates the Invalid
state and provides for synchronization of the circuit. It is known as the
data-type latch or delay-type latch and usually is a gated circuit. This latch
ensures that no equal combinations of data inputs are applied to the steer-
ing gates. The D input allows for only complementary inputs to the steer-
ing gates: one input applied to Gate G1 and an inverted D input applied to
Gate G2. When the gated G = 1, the latch will be in either the SET or the
CLEAR state. When the gated G = 0, the latch’s state at the enable pulse
transition is stored. This state is known as NO CHANGE (NC). When the
latch is enabled, the Q output will follow the D input logic level.
When D = 1 and G = 1, as shown in Figure 1.25, NAND Gate G1

is enabled with a logic low or logic 0 output. The D input is also applied
to the inverter, providing a logic low input to NAND Gate G2. NAND
Gate G2 provides a logic high or logic 1 output. The logic 0 at Gate G3
input will provide a logic 1 output. This logic 1 output from Gate G3
will be feedback to the upper input of Gate G4. Both of the inputs for
Gate G4 are logic 1s, providing a logic 0 output of Gate G4. This output
is feedback to the lower input of Gate G3, confirming that Gate G3 will
provide a logic 1 output. So the SET state will provide outputs Q = 1
and Q′ = 0.
U1
U3
D 1 2 0
1 2
3
G1 1
1
G3 Q=1
1 3
0
NAND2
OR2
U4
U2
U5 1 2
1 2 1 Q’ = 0
1 G4
1 3 0
2 1 3 G2
INV
0
OR2
NAND2
NOT
Figure 1.25. SET state of the active low gated D latch
When D = 0 and G = 1, as shown in Figure 1.26, NAND Gate G1

is disabled with a logic high or logic 1 output. The D input is also applied
to the inverter, providing a logic high input to NAND Gate G2. With both
inputs at NAND Gate G2 logic highs or logic 1s, the NAND GATE G2
output will be a logic 0. The logic 0 at the lower input of Gate G4 input
will provide a logic 1 output. This logic 1 output from Gate G4 will be
feedback to the lower input of Gate G3. Both of the inputs for Gate G3
are logic 1s, providing a logic 0 output of Gate G3. This logic 0 output
is feedback to the upper input of Gate G4, confirming that Gate G4 will
provide a logic 1 output. So the CLEAR state will provide outputs Q = 0
and Q′ = 1.
U1
U3
0 2
D 1
1 2
3
G1 1
0
G3 Q=0
1 3
1
NAND2
OR2
U4
U2
U5 0 2
1 2 1 Q’ = 1
0 G4
1 3 1
2 1 3 G2
INV
1
OR2
NAND2
NOT
Figure 1.26. CLEAR state of the active low gated D latch
When D = 0 and G = 0, as shown in Figure 1.27, both NAND Gates

G1 and G2 are disabled, providing logic highs or 1s output. Since the Q
output follows the D input, we assume that Q has a logic low or logic 0
output. This output is feedback to the upper input of Gate G4, providing a
logic high or logic 1 output. This output is feedback to the lower input of
Gate G3, confirming both logic 1s at Gate G3 inputs will provide a logic 0
output. So the NO CHANGE state with D = 0 input will provide outputs
Q = 0 and Q′ = 1.
U1
U3
0 2
D 1
1 2
3
G1 1
0
G3 Q=0
0 3
1
NAND2
OR2
U4
U2
U5 0 2
0 2 1 Q’ = 1
1 G4
1 3 1
2 1 3 G2
INV
1
OR2
NAND2
NOT
Figure 1.27. NO CHANGE (NC) state of the active low gated D latch (D = 0)
When D = 1 and G = 0, as shown in Figure 1.28, both NAND Gates

G1 and G2 are disabled, providing logic highs or 1s output. Since the Q out-
put follows the D input, we assume that Q has a logic high or logic 1 output.
This output is feedback to the upper input of Gate G4, providing a logic
low or logic 0 output. This output is feedback to the lower input of Gate
G3, confirming Gate G3 inputs will provide a logic 1 output. So the NO
CHANGE state with D = 1 input will provide outputs Q = 1 and Q′ = 0.
U1
U3
1 2
D 1
1 2
3
G1 1
1
G3 Q=1
0 3
0
NAND2
OR2
U4
U2
U5 1 2
0 2 1 Q’ = 0
1 G4
1 3 0
2 1 3 G2
INV
0
OR2
NAND2
NOT
Figure 1.28. NO CHANGE (NC) state of the active low gated D latch (D = 1)
active low gated D latch.
Table 1.7. D and G inputs over time
U1
U3
D 2
1 2
3
G1 1
G3 Q
3
NAND2
OR2
U4
U2
U5 2
2 1 Q’
1 3
G4
2 1 3 G2
INV
OR2
NAND2
NOT
Figure 1.29. Active low gated D latch used to determine waveform

Using the D and G inputs we can determine the Q and Q′ outputs for
time increment from the aforementioned information in this section. Once
we know the output for each time increment we can construct the wave-
form shown in Figure 1.30.
Figure 1.30. Active low gated D latch waveform

Table 1.8. State table for time increments of active low gated D latch
waveform
1.6. FOUR-BIT BISTABLE LATCHES
The SN74LS75 and SN74LS77 four-bit bistable latches are other circuits
using latches. Both these circuits are similar to the D-type latch. The value
of Q outputs of these bistable latch circuits will be the same as the value
of the D inputs. The Q outputs of the bistable latches store data when
the enable input goes low. In both the SN74LS75 and SN74LS77 four-bit
bistable circuits, when Enable C = 0, the top AND is inhibited and data is
prevented from entering the latch. Additionally, the Enable C is inverted
and enables the bottom AND gate which controls the NOR gate in order
to retain the current latch condition. When Enable C = 1 the bottom AND
gate will be inhibited while the top AND gate is enabled to allow the data
input to control the NOR gate, causing Q to follow the D input.
1.6.1. SN74LS75
This four-bit bistable latch has two inputs, identified as D and Enable C.
The latch outputs are Q and Q′. Figure 1.31 shows the gated D and Enable
C inputs, both Q and inverted Q (Q′) outputs, the state of each input com-
bination, and the logic symbol for the SN74LS75 four-bit bistable latch.
U2
Q
2
D 1
3 U4 U5
2
U1 AND2 1 2 1 Q’
U3 3
Enable 2 1 2
C 1 NOR2 NOT
3
NOT
AND2
a. SN74LS75 Four-Bit Bistable Latch Diagram
1Q
1D
1Q’
1C,2C
2Q
2D
2Q’
3Q
3D
3Q’
3C,4C
4Q
4D
4Q’
b. SN74LS75 Four-Bit Bistable c. SN74LS75 Four-Bit

Latch Bistable Latch State Table
Figure 1.31. SN74LS75 four-bit bistable latch logic diagrams and state table
When D = 1 and C = 1, as shown in Figure 1.32, AND Gate G2 is

enabled, providing a logic high or logic 1 output. The logic high controls
the NOR to enable data to the Q output. Additionally, the logic high output
for Gate G4 is inverted through Gate G5 and fed back to the bottom input
of Gate G3. Along with the inverted Enable C input at the upper input to
Gate G3, disable Gate G3.
U2
1
1
Q
2
D 1
G2
3 U4 U5
1
2
U1 AND2 1 2 1 0
G4 G5 Q’
U3 3
Enable 1 2 1 2
G1 0
C 1 NOR2 NOT
0 G3
3
NOT
AND2
Figure 1.32. SET state of the four-bit bistable latch
When D = 0 and C = 1, as shown in Figure 1.33, AND Gate G2 is

enabled with data being cleared or logic 0 output to Q.
U2
0
0
Q
2
D
G2 1
3 U4 U5
0
2
U1 AND2 1 2 1 1
G4 G5 Q’
U3 3
1 2 1 2 0
G1 1 NOR2 NOT
0 G3
3
NOT
AND2
1
Figure 1.33. CLEAR state of the four-bit bistable latch
As stated, when Enable C = 0, the top AND Gate G2 is inhibited and

data is prevented from entering the latch. Additionally, the Enable C is
inverted and enables the bottom AND gate, which controls the NOR gate,
in order to retain the current latch condition (Figure 1.34).
U2
1
0
Q
D 2
G2 1
3 U4 U5
0
2
U1 AND2 1 2 1 0
G4 G5 Q’
U3 3
Enable 0 2 1 2
G1 0
C 1 NOR2 NOT
1 G3
3
NOT
AND2
0
Figure 1.34. NO CHANGE (NC) state of the four-bistable latch

SN74LS75 four-bit bistable latch.
Table 1.9. SN74LS75 four-bit bistable D and C inputs over time
U2
Q
D 2
G2 1
3 U4 U5
2
U1 AND2 1 2 1 Q’
U3 3 G4 G5
Enable 2 1 2
C G1 1 NOR2 NOT
G3
3
NOT
AND2
Figure 1.35. SN74LS75 four-bit bistable latch used to determine waveform
Using the D and Enable C inputs we can determine the Q and Q′ out-
tion. Once we know the output for each time increment we can construct
Figure 1.36. Active low gated D latch waveform
Additionally, we construct a state table providing each time increment’s

state as shown in Table 1.10 and waveform in Figure 1.37.

bistable latch
Figure 1.37. SN74LS75 four-bit bistable latch waveform
1.6.2. SN74LS77
This four-bit bistable latch has two inputs, identified as D and Enable C.
This latch has only the Q output. Figure 1.38 shows the gated D and En-
able C inputs, the single output Q, the state of each input combination,
and the logic symbol for the SN74LS77 four-bit bistable latch. This circuit
works exactly like the SN74LS75 four-bit bistable latch with the exception
that the SN74LS77 has one Q output alone (no Q′ output).
U7
2
D
1
3 U9
2
U6 AND2 1 Q
U8 3
Enable 2 1 2
C 1 OR2
3
NOT
AND2
Figure 1.38. SN74LS77 four-bit bistable latch logic diagrams and state table
1Q
1D
1C,2C
2Q
2D
3Q
3D
3C,4C
4Q
4D
b. SN74LS77 Four-Bit
Bistable Latch State Table c. SN74LS77 Four-Bit Bistable
Latch Logic Diagram
Figure 1.38. SN74LS77 four-bit bistable latch logic diagrams and

state table (Continued )
SN74LS77 four-bit bistable latch.
Table 1.11. SN74LS77 four-bit bistable D and C inputs over time
U7
2
D
1
3 U9
2
U6 AND2 1 Q
U8 3
Enable 2 1 2
C 1 OR2
3
NOT
AND2
Figure 1.39. SN74LS77 four-bit bistable latch used to determine waveform
Using the D and Enable C inputs we can determine the Q output for
time increment from the aforementioned information in this section. Once
we know the output for each time increment we can construct the wave-
form shown in Figure 1.40.
Figure 1.40. SN74LS77 four-bit bistable latch waveform
Additionally, we construct a state table providing each time increment’s

state as shown in Table 1.12.

bistable latch waveform
1.7. D-TYPE FLIP FLOP: POSITIVE EDGE

TRIGGERED D-TYPE FLIP FLOP
The positive edge triggered D flip flop has two inputs, identified as D
and CLK; however, input D is inverted at the bottom steering gate. The D
flip flop outputs are Q and Q′. Figure 1.41 shows the gated D and CLK
inputs, how one inverted OR gate output feeds back to the other OR gate
symbol for the positive edge triggered D flip flop, and the positive edge
triggered D flip flop waveform.
U1
U3
D 2
1 2
3 1 Q
3
NAND2
OR2
Edge
CLK
Detector
U4
U2
CLK U5 2
2 1
Q’
PGT 1 3
PULSE 2 1 3
OR2
NAND2
NOT
a. Positive Going Transition (PGT) Pulse D-Type Flip Flop Diagram
D Q
CLK Q’
b. PGT D Flip Flop State

Table c. PGT D Flip Flop
Logic Diagram
t0 t1 t2 t3
CLK
D
Q
Q’
d. Positive Edge Triggered D Flip

Flop Waveform
Figure 1.41. Positive edge triggered D flip flop logic diagrams and state table
The edge detector circuit shown in Figure 1.41a produces a short

d uration positive pulse on the positive going transition (PGT) of the clock
pulse. This pulse enables the steering gates and functions identical to the
D-type latch. When the NAND gates are enabled, the Q output follows
the status of the D input. The date input should not be changed during
the active clock cycle. When the pulse is not available, the edge detector
produces a low input that inhibits the steering gates. Upon occurrence the
NAND gate latch is put into the RETAIN state to store data in the flip flop.
When D = 1 and CLK = ↑ (transitioning to a logic 1) as shown in
Figure 1.42, Gate G1 will be enabled with both high inputs resulting in a
logic low output. Gate G3 will have only one logic high input, resulting in
a high output. We know Q will follow the D input, which is a logic high.
We can trace the Q logic 1 back to the upper input of Gate G5. Gate G5
will have both inputs as logic 1s, resulting in a logic 0 output. The Q′ out-
put can be traced back to the lower input of G4, confirming both inputs of
Gate G4 as logic 0s, resulting in the logic 1 output. So Q = 1 and Q′ = 0.
U1
1 U3
1 2 0
D
1 2
3
G1 1
1
G4 Q=1
1 3
0
NAND2
OR2
1 Edge 1
CLK
Detector
1
U4
U2 1
CLK U5 1 2
0
2 1
1 G5 Q’ = 0
PGT G3
1 3
PULSE 2 G2 1 3
0
OR2
NAND2
NOT
Figure 1.42. SET state for positive edge triggered D flip flop
When D = 0 and CLK = ↑ (transitioning to a logic 1) as shown in

Figure 1.43, Gate G3 will be enabled with both high inputs resulting in a
logic low output. Gate G1 will have only one logic high input, resulting in
a high output. We know Q will follow the D input, which is a logic low. We
can trace the Q logic 0 back to the upper input of Gate G5. Gate G5 will
have both inputs as logic 0s, resulting in a logic 1 output. The Q′ output
can be traced back to the lower input of Gate G4, confirming both inputs of
Gate G4 as logic 1s, resulting in the logic 0 output. So Q = 0 and Q′ = 1.
U1
0 U3
0 2 1
D
1 2
3
G1 1
0
G4 Q=0
1 3
1
NAND2
OR2
1 Edge 1
CLK
Detector
0
U4
U2 0
CLK U5 1 2
1
2 1
0 G5 Q’ = 1
PGT G3
1 3
PULSE 2 G2 1 3
1
OR2
NAND2
NOT
Figure 1.43. CLEAR state for positive edge triggered D flip flop
When D = 0 and CLK = low input (transitioning to a logic 0) as shown

in Figure 1.44, Gate G1 will have both low inputs resulting in a logic high
output. Gate G3 will have only one logic high input, resulting in a high out-
put. We know Q will follow the D input and we can assume Q to be a logic
low. We can trace the Q logic 0 back to the upper input of Gate G5. Gate G5
will have only one logic high input, resulting in a logic 1 output. The Q′ out-
put can be traced back to the lower input of Gate G4, confirming both inputs
of Gate G4 as logic 1s, resulting in the logic 0 output. The circuit will be
in the NO CHANGE state storing the retained data. So Q = 0 and Q′ = 1.
U1
0 U3
0 2 1
D
1 2
3
G1 1
0
G4 Q=0
0 3
1
NAND2
OR2
1 Edge 0
CLK
Detector
0
U4
U2 0
CLK U5 0 2
1
2 1
1 G5 Q’ = 1
PGT G3
1 3
PULSE 2 G2 1 3
1
OR2
NAND2
NOT
Figure 1.44. NO CHANGE state for positive edge triggered D flip flop (D = 0)
When D = 1 and CLK = low input (transitioning to a logic 0) as shown

in Figure 1.45, Gate G3 will have both low inputs resulting in a logic high
output. Gate G1 will have only one logic high input, resulting in a high out-
put. We know Q will follow the D input and we can assume Q to be a logic
high. We can trace the Q logic 1 back to the upper input of Gate G5. Gate G5
will have both logic high inputs resulting in a logic 0 output. The Q′ output
can be traced back to the lower input of Gate G4, confirming only one logic
high input to Gate G4, resulting in a logic 1 output. The circuit will be in the
No Change state storing the retained data. So Q = 1 and Q′ = 0.
U1
1 U3
1 2 1
D
1 2
3
G1 1
1
G4 Q=1
0 3
0
NAND2
OR2
0 Edge 0
CLK
Detector
1
U4
U2 1
CLK U5 0 2
0
2 1
1 G5 Q’ = 0
PGT G3
1 3
PULSE 2 G2 1 3
1
OR2
NAND2
NOT
The positive going transition (PGT for a positive edge detector can
be developed from a circuit such as the one shown in Figure 1.46. When
ANDing, the two inputs together will create the positive going transition
pulse. One input is a positive clock pulse input while the other is a negative
clock pulse input. The negative clock be will delayed by 20 to 25ns due to
the invertor on this input. Figure 1.47 shows the waveform for the positive
edge detector.
Figure 1.46. Positive edge detector circuit
Figure 1.47. Positive edge detector waveform
Given Figure 1.48 we construct the waveform for the D-type flip flop.
Figure 1.48. CLK and D inputs

Using the CLK and D inputs we can determine the Q and Q′ outputs
for time increment from the aforementioned information in this section.
Once we know the output for each time increment we can construct the
waveform shown in Figure 1.49.
Figure 1.49. Positive going transition D-type flip flop waveform
1.7.1. NEGATIVE EDGE TRIGGERED D-TYPE FLIP FLOP
The negative edge triggered D flip flop has two inputs, identified as D
and CLK; however, input D is inverted at the bottom steering gate. The D
flip flop outputs are Q and Q′. Figure 1.50 shows the gated D and CLK
inputs, how one inverted OR gate output feeds back to the other OR gate
symbol for the negative edge triggered D flip flop, and the negative edge
triggered D flip flop waveform.
U1
U3
D 2
1 2
3 1 Q
3
NAND2
OR2
Edge
CLK
Detector
U4
U2
CLK U5 2
2 1
Q’
NGT 1 3
PULSE 2 1 3
OR2
NAND2
NOT
a. Negative Going Transition (NGT) Pulse D-Type Flip Flop Diagram
Figure 1.50. Negative edge triggered D flip flop logic diagrams and state table
D Q
CLK Q’
b. NGT D Flip Flop State

c. NGT D Flip Flop
Table
Logic Diagram
t0 t1 t2 t3
CLK
D
Q
Q’
d. Negative Edge Triggered D Flip Flop Waveform
Figure 1.50. Negative edge triggered D flip flop logic

diagrams and state table (Continued )
The edge detector circuit shown in Figure 1.51 produces a short du-
ration positive pulse on the negative going transition (NGT) of the clock
pulse. This pulse enables the steering gates and functions identical to the
D-type latch. When the NAND gates are enabled, the Q output follows
the status of the D input. The date input should not be changed during
the active clock cycle. When the pulse is not available, the edge detector
produces a low input that inhibits the steering gates. When this occurs the
NAND gate latch is put into the RETAIN state to store data in the flip flop.
When D = 1 and CLK = ↓ (transitioning to a logic 1 with a negative
down clock) as shown in Figure 1.51, Gate G1 will be enabled with both
high inputs resulting in a logic low output. Gate G3 will have only one
logic high input, resulting in a high output. We know Q will follow the D
input, which is a logic high. We can trace the Q logic 1 back to the upper
input of Gate G5. Gate G5 will have both inputs as logic 1s, resulting in
a logic 0 output. The Q′ output can be traced back to the lower input of
G4, confirming both inputs of Gate G4 as logic 0s, resulting in the logic 1
output. So Q = 1 and Q′ = 0.
U1
1 U3
1 2 0
D
G1 1 2 1
3 G4 1 Q=1
3
0
NAND2
OR2
1 Edge 1
CLK
Detector
1
U4
U2
CLK U5 1 2 0
2 1 1
G5 Q’ = 0
NGT 1 3
2 1 3
G3
PULSE G2
0 OR2
NAND2
NOT
Figure 1.51. SET state for negative edge triggered D flip flop
When D = 0 and CLK = ↓ (transitioning to a logic 1 with a negative

down clock) as shown in Figure 1.52, Gate G3 will be enabled with both
high inputs resulting in a logic low output. Gate G1 will have only one
logic high input, resulting in a high output. We know Q will follow the D
input, which is a logic low. We can trace the Q logic 0 back to the upper
input of Gate G5. Gate G5 will have both inputs as logic 0s, resulting in a
logic 1 output. The Q′ output can be traced back to the lower input of Gate
G4, confirming both inputs of Gate G4 as logic 1s, resulting in the logic 0
output. So Q = 0 and Q′ = 1.
U1
0 U3
0 2 1
D
G1 1 2 0
3 G4 1 Q=0
3
1 1
NAND2
OR2
1 Edge 1
CLK
Detector
0
U4
U2
CLK U5 1 0 2 1
2 0 1
G5 Q’ = 1
NGT 1 3
2 1 3
G3
PULSE G2
1 OR2
NAND2
NOT
Figure 1.52. CLEAR state for negative edge triggered D flip flop
When D = 0 and CLK = low input (transitioning to a logic 0) as

shown in Figure 1.53, Gate G1 will have both low inputs resulting in a
logic high output. Gate G3 will have only one logic high input, resulting
in a high output. We know Q will follow the D input and we can assume
Q to be a logic low. We can trace the Q logic 0 back to the upper input of
Gate G5. Gate G5 will have only one logic high input, resulting in a logic
1 output. The Q′ output can be traced back to the lower input of Gate G4,
confirming both inputs of Gate G4 as logic 1s, resulting in the logic 0 out-
put. The circuit will be in the No Change state, storing the retained data.
So Q = 0 and Q′ = 1.
U1
0 U3
0 2 1
D
G1 1 2 0
3 G4 1 Q=0
3
0 1
NAND2
OR2
0 Edge 0
CLK
Detector
0
U4
U2
CLK U5 0 0 2 1
2 1 1
G5 Q’ = 1
NGT 1 3
2 1 3
G3
PULSE G2
1 OR2
NAND2
NOT
Figure 1.53. NO CHANGE state for negative edge triggered D flip flop (D = 0)
When D = 1 and CLK = low input (transitioning to a logic 0) as

shown in Figure 1.54, Gate G3 will have both low inputs resulting in a
logic high output. Gate G1 will have only one logic high input resulting in
a high output. We know Q will follow the D input and we can assume Q to
be a logic high. We can trace the Q logic 1 back to the upper input of Gate
G5. Gate G5 will have both logic high inputs resulting in a logic 0 output.
The Q′ output can be traced back to the lower input of Gate G4, confirm-
ing only one logic high input to Gate G4 resulting in a logic 1 output. The
circuit will be in the No Change state, storing the retained data. So Q = 1
and Q′ = 0.
U1
1 U3
1 2 1
D
G1 1 2 1
3 G4 1 Q=1
3
0 0
NAND2
OR2
0 Edge 0
CLK
Detector
1
U4
U2
CLK U5 0 1 2 0
2 1 1
G5 Q’ = 0
NGT 1 3
2 1 3
G3
PULSE G2
0 OR2
NAND2
NOT
The negative going transition (NGT) for a negative edge detector can
be developed from a circuit such as the one shown in Figure 1.55. When
ANDing the two inputs together will create the negative going transition
pulse. One input is a positive clock pulse input while the other is a negative
clock pulse input. The negative clock be will delayed by 20 to 25ns due to
the invertor on this input. Figure 1.56 shows the waveform for the negative
edge detector.
Figure 1.55. Negative edge detector circuit
Figure 1.56. Negative edge detector waveform
Given Figure 1. 57 we construct the waveform for the D-type flip flop.
Figure 1.57. CLK and D inputs

Using the CLK and D inputs we can determine the Q and Q′ outputs
for time increment from the aforementioned information in this section.
Once we know the output for each time increment we can construct the
waveform shown in Figure 1.58.
Figure 1.58. Negative going transition D-type flip flop waveform
1.8. JK-TYPE FLIP FLOP: POSITIVE EDGE

TRIGGERED JK FLIP FLOP
The positive edge triggered JK flip flop has three inputs, identified as J,
K, and CLK. The JK flip flop outputs are Q and Q′. Figure 1.59 shows the
gated J, K, and CLK inputs and how the top OR gate output feeds back to
the bottom NAND gate while the bottom OR gate output feeds back to the
top NAND gate; additionally, the top OR gate feeds back to the bottom OR
gate with inverse polarity while the bottom OR gate feeds back to the top
OR gate with inverse polarity. The figure also shows the state of each input
combination, the logic symbol for the positive edge triggered JK flip flop,
and the positive edge triggered JK flip flop waveform.
U6
U3
2
J 3 1 2
4 1 Q
3
NAND3
OR2
Edge
CLK
Detector
U4
U7
2
2 1 Q’
K 3 1 3
4
OR2
NAND3
a. JK-Type Flip Flop Diagram

and state table
PRE’
J Q
CLK
K Q’
CLR’
b. JK Flip Flop State Table c. PGT JK Flip Flop

Logic Diagram
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9
CLK
CLR’
PRE’
J
K
Q
Q’
d. Positive Edge Triggered JK Flip Flop Waveform

and state table (Continued )
The JK flip flop is the most versatile of the flip flops we have discussed
so far. It takes on one of the same characteristics as the D-type flip flop
in that its output will follow the D input. However, the JK flip flop has
two data inputs instead of one that the D-type flip flop possesses. When
J=K=1 and the clock = 1, an uncontrolled toggling situation would
occur. The toggling rate would be determined by the propagation delay of
the circuit. This situation is also known as race around condition.
We have not discussed time constants, propagation delay, or racing
previously, and these might be helpful in understanding further informa-
tion. We define these terms as follows:
Time constant: It is a time that represents the speed with which a particu-
lar system can respond to change, typically equal to the time taken for a
specified parameter to vary by a factor of 1-1/ e (approximately 0.6321).
Propagation delay: Also known as gate delay, it is the length of time

that starts when the input to a logic gate becomes stable and valid
to change, to the time that the output of that logic gate is stable and
valid to change.
Racing: A race condition may occur in a system of logic gates where
inputs vary. If a given output depends on the state of the inputs, it may
only be defined for steady-state signals. As the inputs change state, a
small delay will occur before the output changes due to the physical
nature of the electronic system. The output may, for a brief period,
change to an unwanted state before settling back to the designed
state. Certain systems can tolerate such glitches but if this output
functions as a clock signal for further systems that contain memory,
for example, the system can rapidly depart from its designed behav-
ior (in effect, the temporary glitch becomes a permanent glitch).
The design characteristics of the JK flip flop are similar to those of the
S-C latch as shown in Figure 1.60. In addition, the JK flip flop provides a
feedback network from the output back to the steering gates.
U1
U3
2
SET 1 2
G1
3
3 G3
1 Q
NAND2
OR2
U4
U2
2
2 G4 1
1 3
Q’
3 G2
CLR
OR2
NAND2
U6
U3
2
J 3 1 2
4 1 Q
3
NAND3
OR2
Edge
CLK
Detector
U4
U7
2
2 1 Q’
K 3 1 3
4
OR2
NAND3
Figure 1.60. S-C latch similarity to JK flip flop

We also notice a similarity in the S-C latch truth table versus the JK
flip flop truth table as shown in Figure 1.61.
Figure 1.61. Similarity of S-C latch and JK flip flop truth tables
When CLK = 0, J = 1, and K = 1, the flip flop is in the store or

memory state. We can see when CLK = 1, J = 0, and K = 0, the flip flop
is again in the store or memory state. When CLK = 1, J = 1, and K = 0,
Q = 1 and Q′ = 0. When CLK = 1, J = 0, and K = 1, Q = 0 and Q′ = 1.
These inputs and outputs are similar to those of other latches and flip
flops. However, when we have CLK = 1, J = 1, and K = 1, the JK flip flop
goes into a state of toggling. Figure 1.62 shows this condition.
1
– 0 U6
U3
2
1 3 1 0 2
J G1
4 G3 1 Q=1
1 3 1
0
NAND3
OR2
Edge 1
CLK
Detector
U4
U7
1 2 0
1 2 1
1 G4 Q’ = 0
K 3 1 1 3
4 G2
OR2
– 1
0 NAND3
Figure 1.62. Toggling (racing) of JK flip flop (first cycle of toggling)
During the first cycle of toggling we assume that Q = 1 and Q′ = 0.

We know the high output at Q can be traced back to the upper input of Gate
G4. Also, the low output at Q′ can be traced by the lower input of Gate G3.
Gate G1 has all high inputs, with a low output confirming the output at
Gate G3. Gate G2 inputs are not all high, so its output will be high, con-
firming the output at Gate G4.
1
– 0 U6
U3
2
1 3 1 – 1
0 2
J G1
4 G3 1 Q = 1– 0
1 3 0
1
NAND3
OR2
Edge 1
CLK
Detector
U4
U7
0 2 1
1 2 1
1 1
– 0 G4 Q’ = 0
–1
K 3 1 3
4 G2
OR2
– 1
0 NAND3
Figure 1.63. Toggling (racing) of JK flip flop (second cycle of toggling)
The low output from Q′ output is feedback to one of the inputs of

Gate G1. With CLK = 1, J = 1, and the low feedback, Gate G1 output
will be high. With the high output from Q output feedback to Gate G2, and
CLK = 1, and K = 1, Gate G2 will have a low output. The Gate G2 output
is applied to one of the inputs of Gate G4, providing a high Q′ output. The
high Q′ output is feedback to the lower input of Gate G3. Since both inputs
of Gate G3 are high, Gate G3 will have a low Q output. Both Q and Q′
outputs are feedback to inputs at Gates G1 and G2 (Figure 1.63).
1
––01 U6
U3
2
1 3 1 –
01–0 2
J G1
4 G3 1 Q = 1– 0– 1
1 3 1
0
NAND3
OR2
Edge 1
CLK
Detector
U4
U7
1 2 0
1 2 1
1 1
––01 G4 Q’ = 0
–1–0
K 3 1 3
4 G2
OR2
–
01–0
NAND3
Figure 1.64. Toggling (racing) of JK flip flop (third cycle of toggling)
The high output from Q′ output is feedback to one of the inputs of

Gate G1. With CLK = 1, J = 1, and the high feedback, Gate G1 output
will be low. With the low output from Q output feedback to Gate G2,
CLK = 1, and K = 1, Gate G2 will have a high output. The Gate G1 out-
put is applied to one of the inputs of Gate G3, providing a high Q output.
The high Q output is feedback to the upper input of Gate G4. Since both
inputs of Gate G4 are high, Gate G4 will have a low Q output. Both Q and
Q′ outputs are feedback to inputs at Gates G1 and G2 (Figure 1.64).
This toggling (racing) situation will continue until CLK = 0. The de-
lay time is determined by the delay timing of the JK flip flop. So Q = 1,
0, 1, 0, . . . and Q′ = 0, 1, 0, 1, . . . will toggle with its complement un-
til the clock is down-clocked. Figure 1.65 shows the clock, J, K, and Q
waveforms.
Figure 1.65. Waveform of JK flip flop toggling (racing)
The following are conditions to overcome racing:
• The positive half cycle must be less than the propagation delay of
the flip flop.
• Implement edge triggering of the flip flop.
• Implement master–slave JK flip flop.
1.9. MASTER–SLAVE JK-TYPE FLIP FLOP
The JK master–slave (MS) flip flop has three inputs, identified as J, K, and
CLK. The JK MS flip flop outputs are Q and Q′. Figure 1.66 shows the
gated J, K, and CLK inputs and how the top NAND gate input feeds back
to the bottom output OR gate while the bottom NAND gate input feeds
back to the top output OR gate. It also shows two sets of NAND gate (in-
verted OR gates) latches where the top OR gate feeds back to the bottom
OR gate with inverse polarity while the bottom OR gate feeds back to the
top OR gate with inverse polarity, the state of each input combination, the
logic symbol for the JK MS flip flop, and the JK MS flip flop waveform.
U6
U3 U10
2 U8
J 3 1 2 QM 2 QS
4 1 2 1 Q
3 1 3
3
NAND3
OR2 OR2
NAND2
CLK’
CLK
U9
U4 U11
U7 2
2 1 2
2 1 3 1
Q’
K 3 1 3 3 QS’
4 QM’
NAND2
OR2 OR2
NAND3 U5
2 1
NOT
MASTER INHIBITED SLAVE ENABLED

MASTER ENABLED SLAVE INHIBITED
a. JK Master–Slave (MS) Flip Flop Diagram
PRE’
J Q
CLK
K Q’
CLR’
b. JK Master Flip Flop State Table c. PGT JK Master

Flip Flop Logic
Diagram
#1 #2 #3 #4 #5 #6 #7 #8 #9 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20
CLK
CLR’
PRE’
QM
QS
d. JK MS Flip Flop Waveform

Figure 1.66. JK MS flip flop logic diagrams and state table
Prior to the aforementioned JK MS waveform initiating clock cy-

cle #1, the flip flop will be in the cleared state. An analysis is given in
Figure 1.67 showing the status of each clock cycle.
46
Figure 1.67. JK MS flip flop clock cycles
Figure 1.68. JK MS latches first-half clock cycle, CLK= 1, J = 1, and K = 0
Figure 1.68 shows the master and slave latches of the JK flip flops.
Additionally, the master portion of the flip flop identifies the positive edge
inputs for the first half of the current clock cycle when CLK = 1, J = 1,
and K = 0. We assumed during the last full clock cycle Q = 1 and Q′ = 0.
The Q and Q′ outputs have been traced back to the master steering gates.
Both G1 and G2 steering gates have high outputs. When J = 1 and K = 0,
Q = 1 and Q′ = 0, so QM = 1 and QM′ = 0. This is confirmed with both
Gate G4 inputs as high, resulting in a low output (QM′ = 0). This low
output can be traced back to the bottom input of Gate G3, confirming that
G3 has a high output. On the negative edge of the current clock cycle the
master portion of the MS JK flip flop will be inactive and the slave portion
will be activated for operation. The QM and QM′ outputs will be inputs to
Gates G5 and G6 of the slave circuit during the negative edge of the clock.
Figure 1.69. JK MS latches second-half clock cycle, CLK′ = 1, QM = 1,

and QM′ = 0
Figure 1.69 shows the inactive master and active slave portions of the
MS JK flip flop. During the second half of the clock cycle, the figure iden-
tifies the negative edge inputs when CLK′ = 1, QM = 1, and QM′ = 0.
Both G1 and G2 steering gates have high outputs. When J = 1 and K = 0,
Q = 1 and Q′ = 0, so QM = 1 and QM′ = 0. The QM and QM′ outputs
will be inputs to Gates G5 and G6 of the slave during the negative edge
of the clock. Both inputs for Gate G5 are high inputs, resulting in a low
output. Since QM′ = 0, the resulting output of Gate G6 is a high. Q will
follow the QM output, so Q = 1. This output can be traced back to the
upper input of Gate G8. Since there are two high inputs to the Gate G8,
the resulting output is low. The low output at Q′ can be traced back to the
bottom input of Gate G7. Two low inputs at Gate G7 will result in a high
output at Q. The Q and Q′ outputs have been traced back to the master
steering gates until CLK =1.
We will show the remaining truth table combinations for the MS JK
flip flop as questions for this section.
1.10. CHAPTER 1 REVIEW QUESTIONS
1. For the active low latch provide the following information:

a. Diagrams for NAND gate latch and inverted OR gate latch
b. Truth table
c. Logic symbol
d. Waveform
2. Given the following active low latch table provide a diagram with
logic levels for inputs and outputs.
3. Given the following table construct the waveform for the active
low latch.
4. Provide the state of active low latch for each time increment.
5. For the active high latch provide the following information:

a. Diagrams for NOR gate latch and inverted AND gate latch
b. Truth table
c. Logic symbol
d. Waveform
6. Given the following active high latch table provide a diagram with
high latch.
8. Provide the state of active high latch for each time increment.
9. For the active low gated S-C Latch provide the following informa-
tion:
a. Diagram
b. Truth table
c. Logic symbol
d. Waveform
10. Provide the diagram and logic levels for inputs and outputs for the
following:
a. Set state of the active low gated S-C latch
b. Clear state of the active low gated S-C latch
c. Remain state of the active low gated S-C latch
d. Invalid state of the active low gated S-C latch
11. Using the following table provide the Q and Q′ outputs for the
active low gated S-C latch.
12. From the results of Question 11 construct a waveform.

13. Provide the state of active low gated S-C latch for each time
increment.
14. For the active low gated D latch provide the following information:
a. Diagram
b. Truth table
c. Logic symbol
d. Waveform
15. Given the following table construct the waveform for the active low
gated D latch.
16. Provide the state of active low gated D latch for each time increment.
17. For the SN74LS75 four-bit bistable latch provide the following
information:
a. Diagram
b. Truth table
c. Logic symbol
d. Waveform
18. Given the following table construct the waveform for the SN74LS75
four-bit bistable latch.
19. Provide the state of the SN74LS75 four-bit bistable latch for each
time increment.
20. What is the difference in the diagrams of the SN74LS75 four-bit bistable
latch and the SN74LS77 four-bit bistable latch? Draw the diagrams.
21. For the positive edge triggered D-type flip flop provide the follow-
ing information:
a. Diagram
b. Truth table
c. Logic symbol
d. Waveform
22. For the negative edge triggered D-type flip flop provide the follow-
ing information:
a. Diagram
b. Truth table
c. Logic symbol
d. Waveform
23. For the positive edge triggered JK flip flop provide the following
information:
a. Diagram
b. Truth table
c. Logic symbol
d. Waveform
24. 24. Provide the definition for the following:
a. Time constant
b. Propagation delay
c. Racing
25. Explain the differences between the S-C latch truth table and the JK
flip flop truth table. Show tables and differences.
26. Explain what happens to the JK flip flop when Clk = 1, J =1, and
K = 1. Show diagrams with logic levels throughout the diagram for
at least the first few transitions.
27. How can the problem in Question 26 be resolved?
28. For the master–slave (MS) JK flip flop provide the following infor-
mation:
a. Diagram
b. Truth table
c. Logic symbol
d. Waveform
29. Show what happens to logic levels throughout the MS JK flip flop half
clock cycles. Provide explanation along with diagrams with logic levels.
1.11. CHAPTER 1 REVIEW ANSWERS
1. For the active low latch provide the following information:

a. Diagrams for NAND gate latch and inverted OR gate latch
b. Truth table
c. Logic symbol
d. Waveform
a. NAND Gate Latch and Inverted OR Gate Latch Diagrams
b. Active Low Latch State Table
t0 t1 t2 t3 t4 t5
Set’
S’ Q
Clr’
Q’
Q
C’ Q’
c. Logic Symbol d. Active Low Latch Waveform

2. Given the following active low latch table provide a diagram with
logic levels for inputs and outputs:
a:
U1
0
SET’ 2
1
3
G1 Q=1
OR2
U2
2
1
G2 1
1 3 Q’= 0
CLR’
OR2

0 1 1 0 SET
b:
U1
0
SET’ 2
1 0
G1 Q=0
3
OR2
U2
0 2
1 1
0 3 G2 Q’ = 1
CLR’
OR2

0 1 0 1 CLEAR
c:
U1
1
SET’ 2
1
1
3
G1 Q=1
OR2
U2
2
1 0
G2 1
1 3 Q’ = 0
CLR’
OR2

1 1 1/0 0/1 RETAIN
d:
U1
0
SET’ 2
1
1
3
G1 Q=1
1
OR2
U2
2
1 1
G2 1
0 3 Q’ = 1
CLR’
OR2

0 0 1 1 INVALID
low latch:
4. Provide the state of the active low latch for each time increment.
5. For the active high latch provide the following information:

a. Diagrams for NOR gate latch and inverted AND gate latch
b. Truth table
c. Logic symbol
d. Waveform
U3 U5
SET 2
1 SET 2
3 Q’ 1
Q’
3
NOR2 AND2
U4
U6
2 2
1
3 Q 1
Q
CLR CLR 3
NOR2 AND2
a. NOR Gate Latch and Inverted AND Gate Latch Diagrams

b. Active High Latch State Table
t0 t1 t2 t3 t4 t5
S Q Set
Clr
C Q’ Q’
c. Logic Symbol
d. Active High Latch Waveform
6. Given the following active high latch table provide a diagram with
a:
U3
1
SET 2
1
0
3 Q’= 0
1
NOR2
U4
0 2 1
1
0 3 Q=1
CLR
NOR2
SET CLR Q Q' STATE

1 0 1 0 SET
b:
U3
0
SET 2
1
1
3 Q’= 1
0
NOR2
U4
1 2 0
1
1 3 Q=0
CLR
NOR2
SET CLR Q Q' STATE

1 0 0 1 CLEAR
c:
U3
0
SET 2
1 1
3 Q’= 1
0
NOR2
U4
2
1 0
1
0 3 Q=0
CLR
NOR2

0 0 1/0 0/1 RETAIN
d:
U3
1
SET 2
1
0
3 Q’= 0
0
NOR2
U4
2
0 0
1
1 3 Q=0
CLR
NOR2

1 1 0 0 INVALID
high latch.
8. Provide the state of the active high latch for each time increment.
9. For the active low gated S-C latch provide the following informa-
tion:
a. Diagram
b. Truth table
c. Logic symbol
d. Waveform
U1
U3
2
SET 1 2
3
3
1 Q
NAND2
OR2
U4
U2
2
2 1
1 3
Q’
3
CLR
OR2
NAND2
a. Active Low S-C Latch Diagram
S Q
C Q’
c. Gated S-C Latch

b. Gated S-C Latch State Table Logic Diagram
t0 t1 t2 t3 t4 t5 t6 t7 t8
Q’
d. Gated S-C Latch Waveform
10. Provide the diagram and logic levels for inputs and outputs for the
following:
a. Set state of the active low gated S-C latch
U1
U3
1 2
SET 0
G1 1 2
1
3
3 G3
1 Q=1
0
NAND2
OR2
G 1
U4
U2
1 2
2 1 G4 1
1 3
Q’ = 0
0 G2 0
3
CLR
OR2
NAND2
b. Clear state of the active low gated S-C latch

U1
U3
0 2 1
SET 1 2
G1 0
3
3 G3
1 Q=0
1
NAND2
OR2
G 1
U4
U2
0 2
2 0 G4 1
1 3
Q’ = 1
1 G2 1
3
CLR
OR2
NAND2

c. Remain state of the active low gated S-C latch

U1
U3
0 2 1
SET 1 2
G1 0
3
3 G3
1 Q=0
1
NAND2
OR2
G 1
U4
U2
0 2
2 1 G4 1
1 3
Q’ = 1
0 G2 1
3
CLR
OR2
NAND2
d. Invalid state of the active low gated S-C latch

U1
U3
1 2
SET 0
G1 1 2
1
3
3 G3
1 Q=1
1
NAND2
OR2
G 1
U4
U2
0 2
2 0 G4 1
1 3
Q’ = 1
1 G2 1
3
CLR
OR2
NAND2
11. Using the following table provide the Q and Q′ outputs for the act-
ive low gated S-C latch.
12. From the results of Question 11 construct a waveform.
13. Provide the state of the active low gated S-C latch for each time
increment.
14. For the active low gated D latch provide the following information:
a. Diagram
b. Truth table
c. Logic symbol
d. Waveform
U1
U3
D 2
1 2
3 1
Q
3
NAND2
OR2
U4
U2
U5 2
2 1 Q’
1 3
2 1 3
OR2
NAND2
NOT
a. Active Low D Latch Diagram
D Q
G Q’
b. Gated D Latch State

c. Gated D Latch
Table Diagram
Logic Diagram
t0 t1 t2 t3 t4 t5
Q’
d. Gated D Latch Waveform

15. Given the following table construct the waveform for the active low
gated D latch.
16. Provide the state of the active low gated D latch for each time incre-
ment.
17. For the SN74LS75 four-bit bistable latch provide the following
information:
a. Diagram
b. Truth table
c. Logic symbol
U2
Q
2
D 1
3 U4 U5
2
U1 AND2 1 2 1 Q’
U3 3
Enable 2 1 2
C 1 NOR2 NOT
3
NOT
AND2
1Q
1D
1Q’
1C,2C
2Q
2D
2Q’
3Q
3D
3Q’
3C,4C
4Q
4D
4Q’
b. SN74LS75 Four-Bit c. SN74LS75 Four-Bit Bistable

Bistable Latch State Table Latch Logic Diagram
18. Given the following table construct the waveform for the SN74LS75
four-bit bistable latch.
SN74LS75 Four-Bit Bistable Latch Waveform

19. Provide the state of the SN74LS75 four-bit bistable latch for each
time increment.
20. What is the difference in the diagrams of the SN74LS75 four-bit

bistable latch and the SN74LS77 four-bit bistable latch? Draw the
diagrams.
U2
Q
2
D 1
3 U4 U5
2
U1 AND2 1 2 1 Q’
U3 3
Enable 2 1 2
C 1 NOR2 NOT
3
NOT
AND2
a. SN74LS75 four-Bit Bistable Latch Diagram

U7
2
D
1
3 U9
2
U6 AND2 1 Q
U8 3
Enable 2 1 2
C 1 OR2
3
NOT
AND2
b. SN74LS77 four-Bit Bistable Latch Diagram

Difference: As can be seen, the SN74LS75 four-bit bistable
latch and the SN74LS77 four-bit bistable latch are identical cir-
cuits with the exception of the inverter at the output of the OR
gate of the SN74LS75 four-bit bistable latch.
21. For the positive edge triggered D-type flip flop provide the follow-
ing information:
a. Diagram
b. Truth table
c. Logic symbol
d. Waveform
U1
U3
D 2
1 2
3 1 Q
3
NAND2
OR2
Edge
CLK
Detector
U4
U2
CLK U5 2
2 1
Q’
PGT 1 3
PULSE 2 1 3
OR2
NAND2
NOT
a. Positive Going Transition (PGT) Pulse D-Type Flip Flop Diagram
D Q
CLK Q’
b. PGT D Flip Flop State

c. PGT D Flip Flop
Table
Logic Diagram
t0 t1 t2 t3
CLK
D
Q
Q’
d. Positive Edge Triggered D Flip Flop Waveform

22. For the negative edge triggered D-type flip flop provide the follow-
ing information:
a. Diagram
b. Truth table
c. Logic symbol
d. Waveform
U1
U3
D 2
1 2
3 1 Q
3
NAND2
OR2
Edge
CLK
Detector
U4
U2
CLK U5 2
2 1
Q’
NGT 1 3
PULSE 2 1 3
OR2
NAND2
NOT
a. Negative Going Transition (NGT) Pulse D-Type Flip Flop Diagram
D Q
CLK Q’
b. NGT D Flip Flop State

c. NGT D Flip Flop
Table
Logic Diagram
t0 t1 t2 t3
CLK
D
Q
Q’
d. Negative Edge Triggered D Flip Flop Waveform

23. For the positive edge triggered JK flip flop provide the following
information:
a. Diagram
b. Truth table
c. Logic symbol
d. Waveform
U6
U3
2
J 3 1 2
4 1 Q
3
NAND3
OR2
Edge
CLK
Detector
U4
U7
2
2 1 Q’
K 3 1 3
4
OR2
NAND3
a. JK-Type Flip Flop Diagram
PRE’
J Q
CLK
K Q’
CLR’
c. PGT JK Flip
Flop Logic
b. JK Flip Flop State Table
Diagram
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9
CLK
CLR’
PRE’
J
K
Q
Q’
d. Positive Edge Triggered JK Flip Flop Waveform

24. Provide the definition for the following:
a. Time constant
b. Propagation delay
c. Racing
a. Time constant: It is a time that represents the speed with which a
particular system can respond to change, typically equal to the
time taken for a specified parameter to vary by a factor of 1–1/e
(approximately 0.6321).
b. Propagation delay: Also known as gate delay, it is the length of time
that starts when the input to a logic gate becomes stable and valid to
change, to the time that the output of that logic gate is stable and valid
to change.
c. Racing: A race condition may occur in a system of logic gates where
inputs vary. If a given output depends on the state of the inputs, it may
only be defined for steady-state signals. As the inputs change state a
small delay will occur before the output changes due to the physical
nature of the electronic system. The output may, for a brief period,
change to an unwanted state before settling back to the designed state.
Certain systems can tolerate such glitches but if this output functions
as a clock signal for further systems that contain memory, for example,
the system can rapidly depart from its designed behavior (in effect, the
temporary glitch becomes a permanent glitch).
25. Explain the differences between the S-C latch truth table and the JK
flip flop truth table. Show tables and differences.
Both tables are the same with the exception of the state when
Clk = 1, J = 1, and K = 1. In the action low S-C latch truth table
this state is not used while in the JK truth table this state is used and
is known as toggle or racing state.
26. Explain what happens to the JK flip flop when Clk = 1, J =1, and
K = 1. Show diagrams with logic levels throughout the diagram for
at least the first few transitions.
When CLK = 0, J = 1, and K = 1, the flip flop is in the store or

memory state. We can also see when CLK = 1, J = 0, and K = 0,
the flip flop is again in the store or memory state. When CLK = 1,
J = 1, and K = 0, Q = 1 and Q′ = 0. When CLK = 1, J = 0, and
K = 1, Q = 0 and Q′ = 1. These inputs and outputs are similar
to those of other latches and flip flops. However, when we have
CLK = 1, J = 1, and K = 1, the JK flip flop goes into a state of
toggling. Figure 1.70 shows this condition.
1
– 0 U6
U3
2
1 3 1 0 2
J G1
4 G3 1 Q=1
1 3 1
0
NAND3
OR2
Edge 1
CLK
Detector
U4
U7
1 2 0
1 2 1
1 G4 Q’ = 0
K 3 1 1 3
4 G2
OR2
– 1
0 NAND3
Figure 1.70. Toggling (racing) of JK flip flop (first cycle of toggling)
During the first cycle of toggling we assume that Q = 1 and

Q′ = 0. We know the high output at Q can be traced back to the
upper input of Gate G4. Also, the low output at Q′ can be traced by
the lower input of Gate G3. Gate G1 has all high inputs, with a low
output confirming the output at Gate G3. Gate G2 inputs are not all
high so its output will be high, confirming the output at Gate G4.
1
– 0 U6
U3
2
1 3 1 – 1
0 2
J G1
4 G3 1 Q = 1– 0
1 3 0
1
NAND3
OR2
Edge 1
CLK
Detector
U4
U7
0 2 1
1 2 1
1 1
– 0 G4 Q’ = 0
–1
K 3 1 3
4 G2
OR2
– 1
0 NAND3
Figure 1.71. Toggling (racing) of JK flip flop (second cycle of toggling)
The low output from Q′ output is feedback to one of the inputs

of Gate G1. With Clk = 1, J = 1, and the low feedback, Gate G1
output will be high. With the high output from Q output feedback to
Gate G2, CLK = 1, and K = 1, Gate G2 will have a low output. The
Gate G2 output is applied to one of the inputs of Gate G4, providing
a high Q′ output. The high Q′ output is feedback to the lower input
of Gate G3. Since both inputs of Gate G3 are high, Gate G3 will
have a low Q output. Both Q and Q′ outputs are feedback to inputs
at Gates G1 and G2 (Figure 1.71).
1
––01 U6
U3
2
1 3 1 –
01–0 2
J G1
4 G3 1 Q = 1– 0– 1
1 3 1
0
NAND3
OR2
Edge 1
CLK
Detector
U4
U7
1 2 0
1 2 1
1 1
––01 G4 Q’ = 0
–1–0
K 3 1 3
4 G2
OR2
–
01–0
NAND3
Figure 1.72. Toggling (racing) of JK flip flop (third cycle of toggling)

The high output from Q′ output is feedback to one of the inputs

of Gate G1. With CLK = 1, J = 1, and the high feedback, Gate G1
output will be low. With the low output from Q output feedback
to Gate G2, and CLK = 1, and K = 1, Gate G2 will have a high
output. The Gate G1 output is applied to one of the inputs of Gate
G3, providing a high Q output. The high Q output is feedback to the
upper input of Gate G4. Since both inputs of Gate G4 are high, Gate
G4 will have a low Q output. Both Q and Q′ outputs are feedback to
inputs at Gates G1 and G2 (Figure 1.72).
This toggling (racing) situation will continue until CLK = 0.
The delay time is determined by the delay timing of the JK flip flop.
So Q = 1, 0, 1, 0, . . . and Q′ = 0, 1, 0, 1, . . . will toggle with their
complement until the clock is down-clocked. Figure 1.73 shows the
clock, J, K, and Q waveforms.
Figure 1.73. Waveform of JK flip flop toggling (racing)
27. How can the problem in Question 26 be resolved?

The following are conditions to overcome racing:
• The positive half cycle must be less than the propagation
delay of the flip flop.
• Implement edge triggering of the flip flop.
• Implement MS JK flip flop
28. For the MS JK flip flop provide the following information:
a. Diagram
b. Truth table
c. Logic symbol
d. Waveform
U6
76
U3 U10
2 U8
J 3 1 2 QM 2 QS
4 1 2 1 Q
3 1 3
3
NAND3
OR2 OR2
NAND2
CLK’
CLK
U9
U4 U11
U7 2
2 1 2
2 1 3 1
Q’
K 3 1 3 3 QS’
4 QM’
NAND2
OR2 OR2
NAND3 U5
2 1
NOT
MASTER INHIBITED SLAVE ENABLED

MASTER ENABLED SLAVE INHIBITED
a. JK Master–Slave (MS) Flip Flop Diagram

PRE’
J Q
CLK
K Q’
CLR’
b. JK Master Flip Flop State Table c. PGT JK Master
Flip Flop Logic
Diagram
#1 #2 #3 #4 #5 #6 #7 #8 #9 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20
CLK
CLR’
PRE’
QM
QS
d. JK MS Flip Flop Waveform
29. Show what happens to logic levels throughout the master–slave JK

flip flop half clock cycles. Provide explanation along with diagrams
with logic levels.
Figure 1.74. JK MS latches first half-clock cycle, CLK = 1, J = 1, and K = 0

Figure 1.74 shows the master and slave latches of the JK flip flops.
Additionally, the master portion of the flip flop identifies the pos-
itive edge inputs for the first half of the current clock cycle when
CLK = 1, J = 1, and K = 0. We assumed during the last full clock
cycle Q = 1 and Q′ = 0. The Q and Q′ outputs have been traced back
to the master steering gates. Both G1 and G2 steering gates have high
outputs. When J = 1 and K = 0, Q = 1 and Q′ = 0, so QM = 1 and
QM′ = 0. This is confirmed with both Gate G4 inputs as high, result-
ing in a low output (QM′ = 0). This low output can be traced back to
the bottom input of Gate G3, confirming that G3 has a high output.
On the negative edge of the current clock cycle the master portion
of the MS JK flip flop will be inactive and the slave portion will be
activated for operation. The QM and QM′ outputs will be inputs to
Gates G5 and G6 of the slave during the negative edge of the clock.
Figure 1.75. JK MS latches second-half clock cycle, Clk′ = 1, QM = 1,

and QM′ = 0
Figure 1.75 shows the inactive master and active slave portions
of the MS JK flip flop. During the second half of the clock cycle, the
diagram shows the negative edge inputs when Clk′ = 1, QM = 1, and
QM′ = 0. Both G1 and G2 steering gates have high outputs. When
J = 1 and K = 0, Q = 1 and Q′ = 0, so QM = 1 and QM′ = 0. The
QM and QM′ outputs will be inputs to Gate G5 and G6 of the slave
during the negative edge of the clock. Both inputs for Gate G5 are high
inputs, resulting in a low output. Since QM′ = 0 the resulting output of
Gate G6 is a high. Q will follow the QM output so Q = 1. This output
can be traced back to the upper input of Gate G8. Since there are two
high inputs to the Gate G8 the resulting output is low. The low output
at Q′ can be traced back to the bottom input of Gate G7. Two low in-
puts at Gate G7 will result in a high output at Q. The Q and Q′ outputs
have been traced back to the master steering gates until CLK =1.
Index
A Complementary Medal-Oxide
Active high latch—NOR gate Semiconductor (CMOS), 1
latch, 7–12 Current spikes, 112
Active low gated D latch, 18–23
Active low gated S-C latch, 12–18 D
Active low latch—NAND gate D latch, active low gated, 18–23
latch, 1–7 D-type flip flop, 29–34
Alternating current (AC) load, 116 Data sheets, and specifications,
Asynchronous active pulse width, 87–92
128–129 Data storage and transfer
flip flops form registers,
B 129–130
Bidirectional shift register, parallel input parallel output,
135–136 134–136
parallel input serial output,
C 133–134
Capacitive load, 116 serial input parallel
Circuit loads, circuit behavior output, 133
with, 103–107 serial input serial output,
CLEAR state 130–132
active high latch, 9 Decoupling capacitors, 112
active low gated D latch, 21 Digital circuits, characteristics of
active low gated S-C latch, 14 data storage and transfer
for negative edge triggered D flip flip flops form registers,
flop, 36 129–130
for positive edge triggered D flip parallel input parallel output,
flop, 31 134–136
Clock pulse, high and low times, parallel input serial output,
128 133–134
Clock transition times, 129 serial input parallel
CMOS devices output, 133
destruction of, 112–113 serial input serial output,
inverter Thevenin circuit, 106 130–132
174 • Index
Digital circuits, characteristics of E

(Continued ) Electrical behavior, of circuits
dynamic electrical behavior, circuit behavior with circuit
113–114 loads, 103–107
gate delays and timing dia- current spikes and decoupling
grams, 114–115 capacitors, 112
power consumption, data sheets and specifications,
124–126 87–92
propagation delay, 122–124 destruction of CMOS devices,
transition time, 116–122 112–113
electrical behavior, 87 fan-outs, 107–110
circuit behavior with circuit loading, effects of, 110
loads, 103–107 logic levels and noise margins,
current spikes and decoupling 93–103
capacitors, 112 unused inputs, 110–112
data sheets and specifications, Electrostatic discharge (ESD),
87–92 112–113
destruction of CMOS devices,
112–113 F
fan-outs, 107–110 Fall time, 116
loading, effects of, 110 Fan-outs, 107–110
logic levels and noise margins, Flip flop circuits
93–103 D-type, 29–34
unused inputs, 110–112 JK master–slave (MS), 44–48
introduction, 79 JK-type, 39–44
RC time constant, 80 negative edge triggered
charging, 80–84 D-type, 34–39
discharging, 84–86 positive edge triggered
timing considerations, 126 D-type, 29–34
asynchronous active pulse JK type, 39–44
width, 128–129 Flip flops form registers,
clock pulse high and low 129–130
times, 128 Four-bit bistable latches,
clock transition times, 129 23–24
maximum clocking frequency SN74LS75, 24–27
(fMAX), 127–128 SN74LS77, 27–29
setup and hold times,
126–127 G
Dynamic electrical behavior, Gate delays, 114–115
113–114
gate delays and timing diagrams, H
114–115 Hold times, 126–127
power consumption, 124–126
propagation delay, 122–124 I
transition time, 116–122 In Zero time transition, 116
Index • 175
INVALID state NOR gate latch, active high

of active high latch, 10 latch, 7–12
of active low gated
S-C latch, 15 P
of active low latch, 5 P-type metal-oxide-semiconductor
(PMOS) transistors, 93
J Parallel input parallel output
JK master–slave (MS) flip flop, (PIPO), 134–135
44–48 bidirectional shift register,
JK-type flip flop, 39–44 135–136
universal shift register, 136
L Parallel input serial output (PISO),
Latch 133–134
active high latch—NOR gate shift mode, 134
latch, 7–12 PIPO. See Parallel input parallel
active low gated D latch, 18–23 output
active low gated S-C latch, PISO. See Parallel input serial
12–18 output
active low latch—NAND gate Positive edge triggered flip flop
latch, 1–7 D-type, 29–34
four-bit bistable latches, 23–24 JK type, 39–44
SN74LS75, 24–27 Positive going transition (PGT)
SN74LS77, 27–29 pulse D-type flip flop, 30
Loading, effects of, 110 Power consumption, 124–126
Logic level, 93–99 Propagation delay, 41, 122–124
M Q
Maximum clocking frequency Quiescent power dissipation, 124
(fMAX), 127–128
R
N Racing, 41
N-type metal-oxide-semiconductor RC time constant, 80
(NMOS) transistors, 93 charging, 80–84
NAND gate latch, active low latch, discharging, 84–86
1–7 Register, 130
Negative edge triggered D-type RETAIN state
flip flop, 34–39 active high latch, 10
Negative going transition (NGT) active low gated S-C latch, 15
pulse D-type flip flop, 34 active low gated S-C latch, 16
NO CHANGE (NC) Rise time, 116
state, 19, 21 Roth, Charles H., 129
for negative edge triggered
D flip flop, 37 S
for positive edge triggered D flip S-C latch, active low gated, 12–18
flop, 32 SCR. See Silicon-controlled
Noise margins, 99–103 rectifier
176 • Index
Serial input parallel output (SIPO), SN74LS77, four-bit bistable

133–134 latches, 27–29
Serial input serial output (SISO), Static power dissipation, 124
130–132
SET state T
active high latch, 8 Thevenin
active low gated D latch, 20 resistance, 106
active low gated S-C voltage, 105
latch, 13 Time constant, 40
for negative edge triggered D Timing considerations, 126
flip flop, 36 asynchronous active pulse width,
for positive edge triggered D 128–129
flip flop, 31 clock pulse high and low
Setup times, 126–127 times, 128
Shift mode, 134 clock transition times, 129
Short circuit current, 105 maximum clocking frequency
Signal path, 122 (fMAX), 127–128
Silicon-controlled rectifier setup and hold times, 126–127
(SCR), 113 Timing diagrams, 114–115
SIPO. See Serial input parallel Transistor-Transistor Logic (TTL), 1
output Transition time, 116–122
SISO. See Serial input
serial output U
SN74LS75, four-bit bistable Universal shift register, 136
latches, 24–27 Unused inputs, 110–112
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DIGITAL SYSTEMS

DESIGN, VOLUME III

Copyright © Momentum Press®, LLC, 2019.

All rights reserved. No part of this publication may be reproduced, stored

First published in 2019 by

ISBN-13: 978-1-94944-915-0 (print)

Momentum Press Engineering Technology Collection

Cover and interior design by S4Carlisle Publishing Services Private Ltd.,

First edition: 2019

Printed in the United States of America

Working as an engineer with advanced weapon systems for more than

circuit behavior; data storage; flip flop; latch; RC time constant

Chapter 1 Latch and Flip Flop Circuits 1

2.3.2.1. Logic Level 93

Figure 1.30. Active low gated D latch waveform 23

Figure 2.15. Ideal CMOS inverter input/output characteristics 100

Figure 2.48. FF-3 set for SISO register 131

Table 1.1. SET′ and CLR′ inputs over time 6

Table 2.11. Percentage of voltage and current of RC

I thank my wife for providing me with the inspiration and motivation

Latch and Flip Flop

In Volume II Chapter 3 we discussed combinational logic circuits whose

1.2. ACTIVE LOW LATCH—NAND GATE LATCH

a. NAND Gate Latch

b. Inverted OR Gate Latch

c. Active Low Latch State Table

e. Active Low Latch Waveform

SET' CLR' Q Q' STATE

Figure 1.2. SET state of the active low latch

SET' CLR' Q Q' STATE

Figure 1.3. CLEAR state of the active low latch

Next we show SET′ = 1 and CLR′ = 1. In Figure 1.4, we assume

SET' CLR' Q Q' STATE

Figure 1.4. RETAIN state of the active low latch

Finally we show SET′= 0 and CLR′ = 0 in Figure 1.5. When either

SET' CLR' Q Q' STATE

Figure 1.5. INVALID state of the active low latch

Table 1.1. SET′ and CLR′ inputs over time

Figure 1.6. Active low latch used to determine

Figure 1.7. Active low latch waveform

Additionally, we construct a state table providing each time incre-

Table 1.2. State table for time increments of latch waveform

1.3. ACTIVE HIGH LATCH—NOR GATE LATCH

c. Active High Latch State Table

e. Active High Latch Waveform

SET CLR Q Q' STATE

Figure 1.9. SET state of the active high latch

SET CLR Q Q' STATE

Figure 1.10. CLEAR state of the active high latch

Next we show SET = 0 and CLR = 0 in Figure 1.11. We assume that

SET' CLR' Q Q' STATE

Figure 1.11. RETAIN state of the active high latch

Finally, we show SET = 1 and CLR = 1 in Figure 1.12. When either

SET' CLR' Q Q' STATE

Figure 1.12. INVALID state of the active high latch

Table 1.3. SET and CLR inputs over time

Figure 1.13. Active high latch used to determine

Figure 1.14. Active high latch waveform

Additionally, we construct a state table providing each time incre-

Table 1.4. State table for time increments of latch waveform

1.4. ACTIVE LOW GATED SET-CLEAR (S-C) LATCH

Steering Gates Active Low Latch

a. Active Low S-C Latch Diagram

b. Gated S-C Latch State Table

c. Gated S-C Latch Q’

Steering Gates Active Low Latch

Next SET = 0, CLR = 1, and gated input = 1, as shown in

Chapter 1 Latch and Flip Flop Circuits 1

Additionally, we construct a state table providing each time increment’s

Additionally, we construct a state table providing each time increment’s