29

CHAPTER 3

STATIC SYNCHRONOUS SERIES COMPENSATOR

3.1 INTRODUCTION

Series compensation is a means of controlling the power

transmitted across transmission lines by altering or changing the characteristic
impedance of the line. The power flow problem may be related to the length
of the transmission line. The transmission line may be compensated by a
fixed capacitor or inductor to meet the requirements of the transmission
system. When the structure of the transmission network is considered, power
flow imbalance problems arise. Inadvertent interchange occurs when the
power system tie line becomes corrupted. This is because of unexpected
change in load on a distribution feeder due to which the demand for power on
that feeder increases or decreases. The generators are to be turned on or off to
compensate for this change in load. If the generators are not activated very
quickly, voltage sags or surges can occur. In such cases, controlled series
compensation helps effectively.

3.2 SERIES COMPENSATOR

Series compensation, if properly controlled, provides voltage

stability and transient stability improvements significantly for post-fault
systems. It is also very effective in damping out power oscillations and
mitigation of sub-synchronous resonance (Hingorani 2000).
 30

3.2.1 Voltage Stability

Series capacitive compensation reduces the series reactive

impedance to minimize the receiving end voltage variation and the possibility
of voltage collapse. Figure 3.1 (a) shows a simple radial system with feeder
line reactance X, series compensating reactance Xc and load impedance Z.
The corresponding normalized terminal voltage Vr versus power P plots, with
unity power factor load and 0, 50, and 75% series capacitive compensation,
are shown in Figure 3.1(b). The “nose point” at each plot for a specific
compensation level represents the corresponding voltage instability. So by
cancelling a portion of the line reactance, a “stiff” voltage source for the load
is given by the compensator.

(a) (b)

Figure 3.1 Transmittable power and voltage stability limit of a radial

transmission line as a function of series capacitive
compensation

3.2.2 Transient Stability Enhancement

The transient stability limit is increased with series compensation.

The equal area criterion is used to investigate the capability of the ideal series
compensator to improve the transient stability.
 31

Figure 3.2 Two machine system with series capacitive compensation

Figure 3.2 shows the simple system with the series compensated
line. Assumptions that are made here are as follows:

The pre-fault and post-fault systems remain the same for the
series compensated system.

The system, with and without series capacitive compensation,

transmits the same power Pm.

Both the uncompensated and the series compensated systems

are subjected to the same fault for the same period of time.

Figures 3.3 (a) and (b) show the equal area criterion for a simple
two machine system without and with series compensator for a three phase to
ground fault in the transmission line. From the figures, the dynamic
behaviour of these systems are discussed.

Prior to the fault, both of them transmit power Pm at angles 1 and

s1 respectively. During the fault, the transmitted electric power becomes
zero, while the mechanical input power to the generators remains constant
(Pm). Hence, the sending end generator accelerates from the steady-state
angles 1 and s1 to 2 and s2 respectively, when the fault clears. In the
figures, the accelerating energies are represented by areas A1 and As1. After
fault clearing, the transmitted electric power exceeds the mechanical input
 32

power and therefore the sending end machine decelerates. However, the
accumulated kinetic energy further increases until a balance between the
accelerating and decelerating energies, represented by the areas A1, As1 and
A2, As2, respectively, are reached at the maximum angular swings, 3 and s3

respectively. The areas between the P versus curve and the constant Pm line
over the intervals defined by angles 3 and crit, and s1 and scrit, respectively,
determine the margin of transient stability represented by areas Amargin and
Asmargin for the system without and with compensation.

(a) (b)

Figure 3.3 Equal area criterion to illustrate the transient stability

margin for a simple two-machine system (a) without
compensation and (b) with a series capacitor

Comparing figures 3.3(a) and (b), it is clear that there is an increase

in the transient stability margin with the series capacitive compensation by
partial cancellation of the series impedance of the transmission line. The
increase of transient stability margin is proportional to the degree of series
compensation.
 33

3.2.3 Power Oscillation Damping

Power oscillations are damped out effectively with controlled series

compensation. The degree of compensation is varied to counteract the
accelerating and decelerating swings of the disturbed machine(s) for damping
out power oscillations. When the rotationally oscillating generator accelerates
and angle increases (d /dt > 0), the electric power transmitted must be
increased to compensate for the excess mechanical input power and
conversely, when the generator decelerates and angle decreases (d /dt < 0),
the electric power must be decreased to balance the insufficient mechanical
input power.

Figure 3.4 Waveforms illustrating power oscillation damping by

controllable series compensation (a) generator angle (b)
transmitted power and (c) degree of series compensation

Figure 3.4 shows the waveforms describing the power oscillation

damping by controllable series compensation. Waveforms in figure 3.4(a)
show the undamped and damped oscillations of angle around the steady
 34

state value 0. The corresponding undamped and damped oscillations of the

electric power P around the steady state value P0, following an assumed fault
(sudden drop in P) that initiated the oscillation are shown by the waveforms in
figure 3.4(b). Waveform 3.4 (c) shows the applied variation of the degree of
series compensation, k applied. ‘k’ is maximum when d /dt > 0, and it is
zero when d /dt < 0.

3.2.4 Immunity to Sub-synchronous Resonance

The sub-synchronous resonance is known as an electric power

system condition where the electric network exchanges energy with a turbine
generator at one or more of the natural frequencies of the combined system
below the synchronous frequency of the system. With controlled series
compensation, the resonance zone is prohibited for operation and the control
system is designed in such a way that the compensator does not enter that
area. Also, an SSSC is an ac voltage source operating only at the fundamental
output frequency and its output impedance at any other frequency should be
zero. The SSSC is unable to form a series resonant circuit with the inductive
line impedance to initiate sub-synchronous system oscillations.

3.2.5 Types of Series Compensators

Series compensation is accomplished either using a variable

impedance type series compensators or a switching converter type series
compensator.

3.2.5.1 Variable impedance type series compensators

The thyristor controlled series compensators are the variable type of

compensators. The type of thyristor used for the variable type series
compensators has an impact on their performance. The types of thyristors
 35

used in FACTS devices are Silicon Controller Rectifier (SCR), Gate Turn-Off
Thyristor (GTO), MOS Turn-Off Thyristor (MTO), Integrated Gate
Commutated Thyristor (GCT or IGCT), MOS Controlled Thyristor (MCT)
and Emitter Turn-Off Thyristor (ETO). Each of these types of thyristors has
several important device parameters that are needed for the design of FACT
devices. These parameters are di/dt capability, dv/dt capability, turn-on time
and turn-off time, Safe Operating Area (SOA), forward drop voltage,
switching speed, switching losses, and gate drive power.

The variable impedance type series compensators are GTO

thyristor controlled series compensator (GCSC), Thyristor Switched Series
Capacitor (TSSC) and Thyristor Controlled Series Capacitor (TCSC).

GTO Thyristor Controlled Series Capacitor (GCSC)

A GCSC consists of a fixed capacitor in parallel with a GTO

Thyristor as in figure 3.5which has the ability to be turned on or off. The
GCSC controls the voltage across the capacitor (Vc) for a given line current.
In other words, when the GTO is closed the voltage across the capacitor is
zero and when the GTO is open the voltage across the capacitor is at its
maximum value. The magnitude of the capacitor voltage can be varied
continuously by the method of delayed angle control (max = 0, zero =
/2). For practical applications, the GCSC compensates either the voltage or
reactance.

Figure 3.5 GTO Controlled Series Capacitor

 36

Thyristor Switched Series Capacitor (TSSC)

Thyristor Switched Series Capacitor (TSSC) is another type of

variable impedance type series compensators shown in Figure 3.6. The TSSC
consists of several capacitors shunted by a reverse connected thyristor bypass
switch.

Figure 3.6 Thyristor Switched Series Capacitor

In TSSC, the amount of series compensation is controlled in a step-

like manner by increasing or decreasing the number of series capacitors
inserted into the line. The thyristor turns off when the line current crosses the
zero point. As a result, capacitors can only be inserted or deleted from the
string at the zero crossing. Due to this, a dc offset voltage arises which is
equal to the amplitude of the ac capacitor voltage. In order to keep the initial
surge current at a minimum, the thyristor is turned on when the capacitor
voltage is zero.

The TSSC controls the degree of compensating voltage by either

inserting or bypassing series capacitors. There are several limitations to the
TSSC. A high degree of TSSC compensation can cause sub-synchronous
resonance in the transmission line just like a traditional series capacitor. The
TSSC is most commonly used for power flow control and for damping power
 37

flow oscillations where the response time required is moderate. There are two
modes of operation for the TSSC-voltage compensating mode and impedance
compensating mode.

Thyristor Controlled Series Capacitor (TCSC)

Figure 3.7 shows the basic Thyristor Controlled Series Capacitor

(TCSC) scheme. The TCSC is composed of a series-compensating capacitor
in parallel with a thyristor-controlled reactor. The TCSC provides a
continuously variable capacitive or inductive reactance by means of thyristor
firing angle control. The parallel LC circuit determines the steady-state
impedance of the TCSC.

Figure 3.7 Thyristor Controlled Series Capacitor

The impedance of the controllable reactor is varied from its

maximum (infinity) to its minimum ( L). The TCSC has two operating
ranges; one is when Clim /2, where the TCSC is in capacitive mode.
The other range of operation is 0 Llim, where the TCSC is in inductive
mode. TCSC can be operated in impedance compensation mode or voltage
compensation mode.
 38

3.2.5.2 Switching converter type compensator

With the high power forced-commutated valves such as the GTO

and ETO, the converter-based FACTS controllers have become true. The
advantages of converter-based FACTS controllers are continuous and precise
power control, cost reduction of the associated relative components and a
reduction in size and weight of the overall system.

An SSSC is an example of a FACTS device that has its primary

function to change the characteristic impedance of the transmission line and
thus change the power flow. The impedance of the transmission line is
changed by injecting a voltage which leads or lags the transmission line
current by 90º.

Figure 3.8 Schematic diagram of SSSC

If the SSSC is equipped with an energy storage system, the SSSC

gets an added advantage of real and reactive power compensation in the
 39

power system. By controlling the angular position of the injected voltage

with respect to the line current, the real power is provided by the SSSC with
energy storage element. Figure 3.8 shows a schematic diagram of SSSC with
energy storage system for real and reactive power exchange.

The applications for an SSSC are the same as for traditional

controllable series capacitors. The SSSC is used for power flow control,
voltage stability and phase angle stability. The benefit of the SSSC over the
conventional controllable series capacitor is that the SSSC induces both
capacitive and inductive series compensating voltages on a line. Hence, the
SSSC has a wider range of operation compared with the traditional series
capacitors.

The primary objective of this thesis is to examine the possible uses

of the SSSC with energy storage system with state-of-the-art power
semiconductor devices in order to provide a more cost effective solution.

3.2.5.3 Comparison of Series Compensator Types

Figure 3.9 shows a comparison of VI and loss characteristics of

variable type series compensators and the converter based series compensator.

Figure 3.9 Comparison of Variable Type Series Compensators to

Converter Type Series Compensator
 40

From the figure the following conclusions can be made.

The SSSC is capable of internally generating a controllable

compensating voltage over any capacitive or inductive range
independent of the magnitude of the line current. The GCSC
and the TSSC generate a compensating voltage that is
proportional to the line current. The TCSC maintains the
maximum compensating voltage with decreasing line current
but the control range of the compensating voltage is
determined by the current boosting capability of the thyristor
controlled reactor.
The SSSC has the ability to be interfaced with an external dc
power supply. The external dc power supply is used to provide
compensation for the line resistance. This is accomplished by
the injection of real power as well as for the line reactance by
the injection of reactive power. The variable impedance type
series compensators cannot inject real power into the
transmission line. They can only provide reactive power
compensation.
The SSSC with energy storage can increase the effectiveness
of the power oscillation damping by modulating the amount of
series compensation in order to increase or decrease the
transmitted power. The SSSC increases or decreases the
amount of transmitted power by injecting positive and
negative real impedances into the transmission line. The
variable-type series compensators can damp the power
oscillations by modulating the reactive compensation.

3.3 STATIC SYNCHRONOUS SERIES COMPENSATOR (SSSC)

The Voltage Sourced Converter (VSC) based series compensators -

Static Synchronous Series Compensator (SSSC) was proposed by Gyugyi in
1989. The single line diagram of a two machine system with SSSC is shown
in Figure 3.10. The SSSC injects a compensating voltage in series with the
 41

line irrespective of the line current. From the phasor diagram, it can be stated
that at a given line current, the voltage injected by the SSSC forces the
opposite polarity voltage across the series line reactance. It works by
increasing the voltage across the transmission line and thus increases the
corresponding line current and transmitted power.

Figure 3.10 Simplified diagram of series compensation with the phasor

diagram.

The compensating reactance is defined to be negative when the

SSSC is operated in an inductive mode and positive when operated in
capacitive mode. The voltage source converter can be controlled in such a
way that the output voltage can either lead or lag the line current by 90o.
During normal capacitive compensation, the output voltage lags the line
current by 90o. The SSSC can increase or decrease the power flow to the
same degree in either direction simply by changing the polarity of the injected
ac voltage. The reversed (180o) phase shifted voltage adds directly to the
reactive voltage drop of the line. The reactive line impedance appears as if it
were increased. If the amplitude of the reversed polarity voltage is large
enough, the power flow will be reversed. The transmitted power verses
transmitted phase angle relationship is shown in Equation (3.1) and the
transmitted power verses transmitted angle as a function of the degree of
series compensation is shown in Figure 3.11.

P= sin + V cos (3.1)

 42

Figure 3.11 Transmitted power verses transmitted angle as a function of

series compensation

3.4 CONVERTERS

3.4.1 Basic Concept

The conventional thyristor device has only the turn on control and
its turn off depends on the natural current zero. Devices such as the Gate
Turn Off Thyristor (GTO), Integrated Gate Bipolar Transistor (IGBT), MOS
Turn Off Thyristor (MTO) and Integrated Gate Commutated Thyristor
(IGCT) and similar devices have turn on and turn off capability. These
devices are more expensive and have higher losses than the thyristors without
turn off capability; however, turn off devices enable converter concepts that
can have significant overall system cost and performance advantages. These
advantages in principle result from the converter, which are self commutating
as against the line commutating converters. The line commutating converter
consumes reactive power and suffers from occasional commutation failures in
the inverter mode of operation. Hence, the converters applicable for FACTS
controllers are of self commutating type (Hingorani and Gyugyi, 2000).
There are two basic categories of self commutating converters:
 43

Current sourced converters in which direct current always

has one polarity and the power reversal takes place through
reversal of dc voltage polarity.
Voltage sourced converters in which the dc voltage always
has one polarity and the power reversal takes place through
reversal of dc current polarity.

For reasons of economics and performance, voltage sourced

converters are often preferred over current sourced converters for FACTS
applications.

3.4.2 Voltage Source Inverters for SSSC

SSSC is a Voltage Sourced Converter based series compensator.

The compensation works by increasing the voltage across the impedance of
the given physical line, which in turn increases the corresponding line current
and the transmitted power. For normal capacitive compensation, the output
voltage lags the line current by 90 o. With Voltage Source Inverters the output
voltage can be reversed by simple control action to make it lead or lag the line
current by 90o.

In the present work, 48-pulse VSI is designed and ideal switches

and zig-zag phase shifting transformers are used to build a GTO-type VSI.
Figure 3.12 shows the Matlab/Simulink model of 48 pulse VSI. This type of
converter is used in high-power Flexible AC Transmission Systems which are
used to control power flow on transmission grids.

The inverter described is harmonic neutralized. It consists of four 3-

phase, 3-level inverters and four phase-shifting transformers. The DC bus is
connected to the four 3-phase inverters. The four voltages generated by the
inverters are applied to secondary windings of four zig-zag phase-shifting
transformers connected in Wye (Y) or Delta (D). The four transformer
 44

primary windings are connected in series and the converter pulse patterns are
phase shifted so that the four voltage fundamental components sum in phase
on the primary side.

Pulses
emux 1
+
-
v Van_Tr1Yse

Voltage Measurement Goto g

+

1 A+ a3 A
A1 2 B+ N
b3 B
B1 3 C+
C1 A-
c3 C -
B-
+
C- n Three-Level Bridge 7

Zigzag +
-
v Vab_Tr1Dse
Phase-Shifting Transformer g
Voltage Measurement1 Goto1 +
A+
a3 A
B+
N
C+
b3 B
A-
A
B
C

B-
-
c3 C
Three-Phase Breaker C- N

Zigzag +
v Van_Tr2Yse Three-Level Bridge1 8
-
a
b
c

Phase-Shifting Transformer1
Voltage Measurement2 Goto2 g
+
A+ a3 A
B+ N
b3 B
C+
A- -
c3 C
B-
-
C- n
Three-Level Bridge2 9
+
Zigzag -
v Vab_Tr2Dse
Phase-Shifting Transformer2 Voltage Measurement3 Goto3 g
+
A+
a3 A
B+
N
C+
b3 B
4 AA A-
A2 5 BB B-
-
c3 C
B2 6 CC C-
C2 Imes_SE Zigzag Three-Level Bridge3
Phase-Shifting Transformer3

Figure 3.12 Matlab/Simulink model of 48 pulse Voltage Source Inverter

Each 3-level inverter generates three square-wave voltages which

can be +Vdc, 0, -Vdc. The duration of the +Vdc or -Vdc level (Sigma) can be
adjusted between 0 and 180 degrees from the sigma input of the firing pulse
generator block. Each inverter uses a 3-level bridge block where specified
power electronic devices are ideal switches. In this model, each leg of the
inverter uses 3 ideal switches to obtain the 3 voltage levels (+Vdc, 0, - Vdc).

The phase shifts produced by the secondary delta connections (-30

degrees) and by the primary zig-zag connections (+7.5 degrees for
 45

transformers 1Y and 1D, and -7.5 degrees for transformers 2Y and 2D) allow
to neutralize harmonics up to 45th harmonic, as explained below:

The 30-degree phase-shift between the Y and D secondaries cancels

harmonics 5+12n (5, 17, 29, 41, ...) and 7+12n (7, 19, 31, 43, ...). In addition,
the 15-degree phase shift between the two groups of transformers (1Y and 1D
leading by 7.5 degrees, 2Y and 2D lagging by +7.5 degrees) allows
cancellation of harmonics 11+24n (11, 35, ...) and 13+24n (13, 37, ...).
Considering the fact that all 3n the harmonics are not transmitted by the Y and
D secondaries, the first harmonics which are not cancelled by the transformers
are 23rd, 25th, 47th and 49th. By choosing an appropriate conduction angle
for the 3-level inverters (sigma = 180 - 7.5 = 172.5 degrees), the 23rd and
25th can be minimized. The first significant harmonics are therefore the 47th
and 49th. This type of inverter generates an almost sinusoidal waveform
consisting of 48-steps. Also with 48 - pulse VSI, AC filters are not required.

The instantaneous values of the phase-to-phase voltage and the

phase to neutral voltage of the 48 pulse inverter are expressed as in equations
3.2 and 3.3.

V ( t) = 8 V sin( m t + 18.75 m + 11.25 t) (3.2)

V ( t) = V sin( m t + 18.75 11.25 t) (3.3)

where,

V = V cos m (3.4)

V = V ( 1 + cos m) (3.5)

m=48r±i, i=0,1,2,…

+ for positive sequence harmonics and

- for negative sequence harmonics.

 46

The voltages Vbc48 and Vca48 exhibit a similar pattern except the
phase shifted by 120o and 240o respectively. Similarly, the phase voltages
Vbn48 and Vcn48 are also phase shifted by 120o and 240o respectively. For the
input voltage of 20kV at the dc side, the waveform at the ac side of the 48
pulse VSI is shown in Figure 3.13. The THD of the voltage is 1.31% and it is
shown in Figure 3.14.

0.1

0.05
voltage (pu)

-0.05

-0.1

0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
time (sec)

Figure 3.13 Voltage at the ac side of the 48 pulse VSI

Figure 3.14 THD of the voltage at the ac side of the 48 pulse VSI
 47

3.5 INTERNAL CONTROL SCHEME FOR SSSC

There are two ways in which the voltage source converter can be
internally controlled (Hingorani 2000). They are:

Indirect control scheme and

Direct control scheme

3.5.1 Indirect Control Scheme

In order to maintain a quadrature relationship between the converter

voltage and the line current, to provide series compensation, and to handle the
sub-synchronous resonance, the converter can be internally controlled. Figure
3.15 shows the block diagram of an indirect control scheme.

Figure 3.15 Block diagram of an indirect control scheme

The inputs to the internal control are the line current, the injected
compensating voltage, and the reference voltage. The control is synchronized
to the line current through the PLL which, after a + /2 or – /2 phase shift,
provides the basic synchronising signal . The output polarity detector
determines the positive capacitive or negative inductive reference voltage
 48

through which the + /2 or – /2 phase shift is determined. A simple closed

loop controller controls the compensating voltage. The absolute value of the
reference voltage is compared with the measured magnitude of the injected
voltage and the amplified difference is added as a correction angle to the
synchronizing signal . The gate signals will be changed accordingly and the
compensating voltage will be phase shifted with respect to the line current.

3.5.2 Direct Control Scheme

To maintain synchronism with the fundamental frequency, the

converter must be directly controlled. Control scheme for directly controlled
converter is shown in figure 3.16. The direct control scheme is for providing
both real and reactive power compensation if the converter is equipped with a
suitable dc power supply. The control is operated from three reference
signals - the desired magnitude of the series reactive compensating voltage,
the series and real compensating and the operating voltage of the dc capacitor.
The references are compared to the corresponding components of the
measured voltages. From these error signals, the magnitude of the injected
voltage and the phase angles are computed and the gate signals for the
converter are generated accordingly.

Figure 3.16 Block diagram of direct control scheme

 49

3.5.3 Control Scheme Proposed

The main function of the SSSC is to dynamically control the power

flow over the transmission line. The control scheme proposed by Anil.
Pradhan and Lehn (2006) is based on the line impedance control mode in
which the SSSC compensating voltage is derived by multiplying the current
amplitude with the desired compensating reactance Xqref. Since it is difficult
to predict Xqref under varying network contingencies, in the proposed scheme,
this controller is modified with power references instead of reactance
reference to operate the Static Synchronous Series Compensator in the
automatic power flow control mode (Geethalakshmi and Dhananjayan 2007).

The phase locked loop determines the frequency and t of the bus1
voltage. Bus2 voltage is converted to d-q components as Vd and Vq.
Similarly, current flowing from bus1 to bus2 is also converted to d-q
components as Id and Iq using d-q transformations as below. The abc to dq0
transformation computes the direct axis, quadrature axis and zero sequence
quantities in a two axis rotating reference frame for a three phase sinusoidal
signal. For the three phase voltage, the following equations are used to
compute the two axis rotating reference voltages.

V = ( V sin ( t ) + V sin( 3) + V sin( t + 2 3)) (3.6)

V = ( V cos( t ) + V cos( 3) + V cos( t + 2 3)) (3.7)

V = (V + V + V ) (3.8)

For obtaining the dq currents from three phase currents, the voltage
is replaced with current.
 50

The reference inputs to the controller are Pref and Qref, which are to
be maintained in the transmission line. The instantaneous power is obtained in
terms of d-q quantities of voltages and currents as below:

P= V I + V I (3.9)
Q= V I + V I (3.10)

From equations 3.9 and 3.10, the required current references are
calculated as follows:

I = P V + Q V / V + V (3.11)
I = P V + Q V / V + V (3.12)

Series Controller

Scope
Scope1

PQ
Idqref

Fre q f requency
PQ
PQref PQref
1 1/z Va b c( p u ) wt wt
Idqref Idqref
Vb1 Vdq Vdq
Sin _C o s 2 1/z Vabc Vdq
Vabc_B2 Reference Computation
PLL
Idq Idq
3 1/z Iabc
Iabc
--
Terminator Subsystem

Vdq Sigma Sigma

0 D _Alpha
Pulses 1
4 1/z Vdc angle Alpha
Pulses
VdcPM_SE
wt
Mag and angle
Firi ng Pul ses
Generator

Scope2

Figure 3.17 Matlab / Simulink model for the generation of firing pulses
for the 48 pulse VSI

Figure 3.17 shows the Matlab / Simulink model for the generation
of firing pulses for the 48 pulse VSI. The desired current references namely
Idref and Iqref are compared with actual current components Id and Iq
respectively and the error signals are processed in the PI controller. The PI
 51

controller parameters are designed by Ziegler Nichols’s PI tuning method.

The PI controller parameters set for this process are 0.045 and 16.5 for the
proportional and integral gains respectively. Based on these controller
parameters set, the required small displacement angle has been derived to
control the angle of the injected voltage with respect to the line current. A
Phase Locked Loop (PLL) is used to determine the instantaneous angle of
the three-phase line voltage V1abc. The current components Id and Iq of the
three phase line currents are used to determine the angle r relative to the
voltage V1abc. Depending upon the instantaneous reactive power with respect
to the desired value either /2 is added (inductive) or subtracted (capacitive)
with Thus, the required phase angle is derived as in the equation 3.13.

ref = r ±( /2) (3.13)

3.6 SIMULATION RESULTS

The details of the test system are given in appendix-1. It is a three

area four bus system. Two parallel lines are connected between the two areas
with 200 and 280km in length. The SSSC is connected in the second line of
280km in length. The line is divided into two parts of 100km and 180km.
SSSC is connected between bus 1 and bus 2 in the 100 km length line.

The simulation carried out is as follows: Initially, power flow

control of the line is tested. Hence, the real power reference is varied and the
results are discussed. Qref is kept constant. SSSC is connected at 0.01sec.
Before the insertion of SSSC, the real power flow through the line is 8.85 pu.
In case (a) the Pref is set to 8.5 pu and at 0.25 sec, Pref is increased to 10 pu.
Figure 3.18 shows the corresponding waveforms for power flow through
transmission line 2. It is clear from the figure that the commanded power
references are achieved. In case (b) the Pref is increased to a higher value of
 52

13 pu. But the final power flow achieved is 12.8 pu which is shown in
Figure 3.19.
12

11
Line power flow (pu)

10

8
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Time (sec)

Figure 3.18 Real power flow through line 2 for case (a)

13

12
Line power flow (pu)

11

10

8
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Time (sec)

Figure 3.19 Real power flow through line 2 for case (b)

The next command is given to Qref. Pref is fixed to a value of

11pu. Before the insertion of SSSC, the reactive power flow is -0.62 pu.
Qref is initially commanded to -0.5 pu and at 0.25 sec it is changed to -0.8 pu.
Figure 3.20 shows the corresponding waveform. Both the set values are
obtained finally.
 53

-0.2
Reactive power flow (pu)
-0.4

-0.6

-0.8

-1

-1.2

-1.4
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Time (sec)

Figure 3.20 Reactive power flow through line 2

Figure 3.21 shows the quadrature relationship between the line

current and the injected voltage. To have a clear waveform, the magnitude of
the line current is reduced to 0.25 of the original value.

3
i
2
0.25 of line current (pu)
Injected voltage (pu)

1
v
0

-1

-2

-3
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Time (sec)

Figure 3.21 Wave forms for 0.25 of line current and injected voltage

For analysing transient stability, a three phase to ground fault is

simulated at 0.2 sec in line 2. The fault is cleared at 0.3 sec. The reference
real and reactive power values set are 11 pu and -0.67 pu respectively and the
results are analysed. Figure 3.22 and 3.23 show the real and reactive power
flow through transmission line 2.
 54

25

20
Line power flow (pu)

15

10

0
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Time (sec)

Figure 3.22 Real power flow through line 2

25

20
Reactive power flow (pu)

15

10

-5
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Time (sec)

Figure 3.23 Reactive power flow through line 2

150

100
Line Current (pu)

50

-50

-100

-150
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Time (s)

Figure 3.24 Current flowing through line 2

 55

Figure 3.24 represents the current flow through line 2 and the value
is 10 pu during normal operating condition and the peak value goes to 147 pu
during fault. Figure 3.25 shows the injected voltage from SSSC and it is 0.06
pu during steady state condition and the oscillations are more during fault
period.

0.8

0.6

0.4
Injected voltage (pu)

0.2

-0.2

-0.4

-0.6

-0.8
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Time (sec)

Figure 3.25 Injected voltage from SSSC

4
x 10
6
Voltage across the capacitor (Volts)

-1
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Time (sec)

Figure 3.26 Voltage across the dc capacitor

 56

Figure 3.26 shows the waveform of voltage across the capacitor.

During faulted period, the value overshoots to 53kV and settles to 21.5 kV in
the post fault period.

Figure 3.27 and 3.28 show the waveforms of the electrical power
output from generator 1 for the cases without and with SSSC respectively.
Figures 3.29 and 3.30 show the waveforms of the load angle for the machine
and from the figures it is clear that the oscillations are reduced for the system
with SSSC. The overshoot and settling time are also less for the system with
SSSC.

2.5
Output active power (pu)

1.5

0.5

-0.5

-1
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Time (sec)

Figure 3.27 Electrical power output from generator 1 for the case
without SSSC

2.5

2
Output active power

1.5

0.5

-0.5

-1
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Time (sec)

Figure 3.28 Electrical power output from generator 1 for the case with
SSSC
 57

60

50

40
Load angle (degrees)

30

20

10

-10

-20
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Time (sec)

Figure 3.29 Load angle of machine 1 for the case without SSSC

50

40
Load angle (degrees)

30

20

10

-10

-20
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
Time (sec)

Figure 3.30 Load angle of machine 1 for the case with SSSC

Table 3.1 Comparative results for the system without and with SSSC

Without SSSC With SSSC

Electrical power Peak value (pu) 2.54 2.14
output from
generator 1
Load angle Peak value (degrees) 52.5 51
 58

3.7 CONCLUSION

The objectives of series compensators have been discussed.

Variable impedance type series compensators and a switching converter type
series compensator have been discussed. A comparative study has been made.
The modelling of SSSC has been discussed. The harmonic neutralised 48
pulse voltage source inverter has been realised. The output waveform and the
THD of the 48 pulse voltage source inverter have been analysed. The various
control schemes used for the control of SSSC have been discussed in detail
and the proposed control scheme with PI controller is given. Simulation
results have been carried out for real and reactive power commands and three
phase fault in line 2 of the proposed system. From the results, the comparison
is tabulated for the system without and with SSSC and the results show a
good improvement in the transient stability of the system with SSSC.