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Impact of process variation on electrical characteristics of 22nm FinFET

Abstract: This paper illustrates about the impact of process variation on electrical

characteristics of 22nm FinFET with height of fin (H​fin​) as


​ 7nm. Electrical characteristics are

simulated using silvaco TCAD including quantum effects. Scaling of thickness of fin,

thickness gate oxide and doping variation in source and drain are ​explore​d. Results illustrate

about the agreeable range of thickness of fin, thickness of gate oxide and doping

concentration.

INTRODUCTION

Scaling of classical MOS devices down to nanometre regime causes severe problems in

device operations. ​To overcome this non classical MOS structure like Tri gate FinFET are

proposed, as reaching nanometer regime device properties change from classical physics to

non classical physics is called quantum mechanics. When device size is comparable to

de-Broglie wavelength, charges in device behaves as particle nature so these are governed by

quantum mechanics and it effects, this effect comes into picture in sub 45nm regime.

Because of better control of channel over the gate in FinFET short channel effects are reduce

over classical MOSFET. These FETs have good threshold voltage (V​th​), sub-threshold slope

(SS), high on current (I​on​) and high I​on​/I​off​ ratio.

DEVICE STRUCTURE AND SIMULATION

Fig.1 shows the FinFET structure, Silicon fin acts as the device channel and source and drain

are on either side of channel, this devices have gate length (L​g​) of 22nm, Fin height (H​fin​) of
7nm, T​fin​ as 3nm, uniform gate dielectric thickness (t​ox​) of 1.5 nm over channel, charge

distribution of these type of structures will be contributed by lateral gates than top gate this is

due to small aspect ​W​/​H​ ratio. The device has a n​+​ source region, an undoped channel region,

and n​+​ drain region, with uniform doping concentration and sources to channel, channel to

drain junctions are assumed to be abrupt.

Figure 1 Schematic view of FinFET device structure.

The electrical characteristics are performed by considering drift diffusion model (quantum

mechanical model) and Schrodinger–Poisson parameters are used in simulation. Threshold

voltage and subthreshold slope are extracted and (I​on​) and I​on​/I​off ratio are calculated from I​D

vs V​DS and I​D vs V​GS cures for different process variations of FinFET .The device simulation

was performed using SILVACO ATLAS TCAD.

SIMULATION RESULTS

Process variation experimented in this paper are i. T​fin variation ii. T​ox variation iii. Doping

variation.

Fin Thickness (T​fin​) variation:

Considering the H​fin as7nm T​ox as 1.5nm fin thickness is varied from 6nm to 2nm. Results
obtained in this expermentation prove that silicon thickness scaling down to 2nm have some

degradation in overall performance of device, this is due limited charges in channel. Fig 2

shows, as the thickness of fin scaled down to 2nm, threshold voltage improved to 0.422volts,

V​th is increased as charge carriers have to increase a higher energy bands. Fig 3 shows, as the

thickness of fin decreases the subthreshold voltage decreases, as sub threshold depends on

potential distribution in the entire BOX. This is slightly below than an optimum value

60 mV/dec at room temperature.

Fig .2 Threshold variation with fin thickness variation


Fig .3 Sub threshold variation with fin thickness variation

Another important electrical characteristics are on current and off current, Fig 4 illustrate

about I​on and I​off​. Off current decreases as the thickness of fin decreases,fin has good control

over the gate voltage . I​on increases with decrease in fin thickness and reach max value at fin

length of 3nm by forthere scaling the fin thickness I​on degrades this is due to minimum

charges per area. So reasonable value of T​fin is 3nm for gate length of 22nm H​fin as 7nm and

obtained on current is ​4.72E-05 amp.


Fig 4 I​on​ and I​off​ variation with T​fin​ variation

Gate Oxide Thickness (tox):

Considering the value of T​fin as 3nm, H​fin as 7nm L​g as 22nm gate oxide is varied from 1nm to

3nm. Fig 5 shows threshold voltage variation with respective gate oxide variation, it is clear

from graph as gate oxide decreases, threshold voltage increases.

Fig .5 Threshold variation with gate oxide thickness variation.


Fig .6 Sub threshold variation with gate oxide thickness variation.

Fig 6 illustrate about subthreshold swing with gate oxide variation, as gate oxide decreases

,sub threshold voltage decreases. Small subthreshold swing is highly desired since it

improves the ratio between the on- and off-currents this is due to better gate control. Fig 7

illustrate about I​on and I​on​/I​off variation on gate oxide variation. On current increases with gate

oxide decreases this is due to gate controllability. Large I​on​/I​off determines good gate

controllability.

Fig 7 I​on​ and I​off​ variation with T​ox​ variation

Doping Variation in source and drain:

Simulations were carried out with T​fin as 3nm , H​fin as 7nm , T​ox as 1.5nm and doping

concentrations are varied. From fig 8 it is observed that threshold voltage is decreasing as

concentration of source and drain are decreasing.


Fig 8 Threshold voltage variation with doping variation in source and drain.

From fig 9 it is clear sub threshold voltage swing is decreasing as concentration of source
and drain are decreasing.

Fig 9 Sub threshold voltage variation with doping variation in source and drain.