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Microprocessor Lecture note

February 2, 2010

Chapter one Introduction to Intel 8085 microprocessor

Definition

A microprocessor is a multipurpose, programmable, clock driven, register based electronics

device that reads binary instructions from a storage device called memory, accepts binary data as

input and processes data according to those instructions, and provides results as output.

Application area Microprocessor is a general purpose electronic device. It is used for monitoring and controlling electronic devises. Some of the application areas are listed below:

Measuring instruments such as the oscilloscope, multi-meter, and spectrum analyzer

Controlling household items such as the microwave oven, door bell, washing machine, and television.

Monitoring defense equipments such as missiles and radar

Computers

Controlling traffic light

Controlling speed and direction of stepper motor

Monitoring medical equipment such as blood pressure and blood analyzer

Important factors used to compare microprocessor

In general, each microprocessor has some strong and weak points compared to the other because

the manufacturers design their microprocessors for certain application areas or specific segment

of the industrial market. It is difficult to comment that one microprocessor is better than the other

because many factors have to be considered before making such comments. Important among these factors are:

1. Number and type of registers

2. Addressable memory range

3. Control bus functions

Speed

Cost

Power consumption

Instruction set

Internal Architecture of 8085 Microprocessor

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Microprocessor Lecture note

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of Technology Microprocessor Lecture note February 2, 2010 Fig 1.1 Inte rnal architecture of 8085 microprocessor

Fig 1.1 Internal architecture of 8085 microprocessor

Control Unit

Generates signals within microprocessor to carry out the instruction, which has been decoded. In reality causes certain connections between blocks of the uP to be opened or closed, so that data goes where it is required, and so that ALU operations occur.

Arithmetic Logic Unit

An arithmetic logic unit functionally consists of an adder, an accumulator, a shift register, temporary register and status or flag register.

The shift register may transfer data from the accumulator to the bus by either shifting it right or left, or transfer it directly.

The temporary register is used to hold bus data to or from the ALU and the status register.

Accumulator is an 8-bit register used for arithmetic, logic, I/O and load/store operations. This register is used to store 8-bit data and to perform arithmetic and logical operations. The result of an operation is stored in the accumulator. The accumulator is also identified as register A.

N.B Most operations in the ALU involve the accumulator.

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Basic function of the ALU is to perform the following arithmetic and logic operations:

Arithmetic operations

Addition

Subtraction

Increment

Decrement

Compare

Status register

Logic operations

And

Or

Ex-or

Not

Compare

Shift/rotate

The status (condition) of contents of the accumulator is indicated by 5 flip-flops. The five flags that indicate the status of the accumulator are shown in the fig. below.

S

Z

X

AC

X

P

X

C

Fig 1.2 Status Register

The letter X in the status flags indicates “do n’t “care conditions and these bits are used internally. These status flags are named as:

- Zero (Z)

- Sign (S)

- Parity (P)

- Carry (C)

- Auxiliary carry (AC)

N.B. The flags and accumulator together is called program status word (PSW). The flags are SET (ON=1) or RESET (OFF=0) as a result of operations such as addition, subtraction etc.

Sing flag (S) The flag is set or reset according to the condition of the MSB or the 7 th bit of the accumulator after arithmetic and logic operations. If any one of the operations make the 7 th (D7) bit of the accumulator high (1), the flag is set otherwise reset. This is useful when singed binary operations are performed. Example: subtract C5H from 60H

60H

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+ 2BH (2’s complement of C5H)

---------------

8BH

Microprocessor Lecture note

February 2, 2010

The result of this operation sets the sign flag of the accumulator to signify the content of the accumulator is negative in signed value operation.

Zero flag This flag indicates that the result of any operation in the accumulator is zero. If the contents in the accumulator is zero, this flag is SET (ON=1) otherwise RESET (OFF=0). Example: Add FFH and 01H FFH

+01H

-----------------

1 00H The result in the accumulator is zero. Therefore, Z=1.

Auxiliary Carry Flag The flag indicates that the operation in the accumulator had a carry from the third bit to the 4 th bit and this flag would be SET (ON=1) otherwise RESET (OFF=0).

Example: Add 0FH and 3AH

0FH

+3AH

---------------

49H

0 0 0 0 1 1 1 1 0 0 1 1 1 0 1
0
0
0
0
1
1
1
1
0
0
1
1
1 0
1
0
0
1
0
0
1 0
0
1

Parity Flag (P) This flag indicates whether the total number of 1’s in the accumulator after execution of any program is odd or even. If the total number of 1’s in the accumulator after execution is even, P=1 and if the number of 1’s is odd, P=0. Example: Add 60H and 3AH

60H

01100000

+3AH

00111010

------------------ ---------------------

9AH

10011010

The total number of 1’s present in this operation is 4. Hence parity is even. i.e. parity flag will be SET (ON = 1).

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Carry Flag (C) This flag is SET if there is any over flow from the seventh bit of the accumulator otherwise RESET after some arithmetic or logic operations. Example: Add 83H and D2H

83H

+D2H

--------------

55H

1

1
1

0 0

0 0

0

1

1

 

1

1 0

 

1 0

 

0

1

0

0

1 0

 

1 0

 

1

0

1

Instruction Register and Decoder

Temporary stores the current instruction of a program. Latest instruction sent here from memory prior to execution. Decoder then takes instruction and ‘decodes’ or interprets the instruction. Decoded instruction then passed to next stage.

Timing and control unit

This unit controls and synchronizes all the operations inside the and outside microprocessor in any microprocessor systems.

Register section of 8085 microprocessor

The registers available inside the microprocessor are broadly divided into 2-groups:

1. Registers accessible to the programmer

2. Registers not accessible to the programmer

A

(8)

Flag Register

B

(8)

C

(8)

D

(8)

E

(8)

E

(8)

L

(8)

SP (Stack Pointer) PC (Program Counter)

Fig. 1.3 Registers of 8085

Registers accessible to the programmer are further sub-divided into 2 sub-groups.

1. General purpose registers (GPRs), and

2. Special purpose registers (SPRs)

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General Purpose Registers (GPRs)

As the name suggests the GPRs can be used for both storing the data as well as the address. The 8085 microprocessor has 6 general purpose registers, namely B, C, D, E, H and L. In 8085 microprocessor, the data size is 8-bit wide and the address size is 16-bit wide. Hence they can be used in pairs as follows:

8-bit B and 8-bit C registers can be used as one 16-bit BC register pair. Some instructions may use BC register as a data pointer.

8-bit D and 8-bit E registers can be used as one 16-bit DE register pair. Some instructions may use DE register as a data pointer.

8-bit H and 8-bit L registers can be used as one 16-bit HL register pair. HL register usually contains a data pointer used to reference memory addresses.

Special Purpose Registers (SPRs)

These are used for some specific applications designated by the manufacturers. The special purpose registers of 8085 microprocessor are:

1. Accumulator (A)

2. Program Counter

3. Stack pointer

4. Status Flag Register

Program Counter

This 16-bit register deals with sequencing the execution of instructions. This register is a memory pointer. Memory locations have 16-bit addresses, and that is why this is a 16-bit register. The function of the program counter is to point to the memory address from which the next byte is to be fetched. When a byte (machine code) is being fetched, the program counter is incremented by one to point to the next memory location. Branching is implemented by making changes to the program counter (for example, Jump instruction).

Stack Pointer (SP)

The stack pointer is also a 16-bit register used as a memory pointer. It points to a memory location in R/W memory, called the stack. The beginning of the stack is defined by loading 16- bit address in the stack pointer.

8085 System Buses

The system bus is a communication path between the microprocessor and peripherals; It is nothing but a group of wires to carry data or address.

Address Bus Address bus carries address. The address bus consists of 16 wires. That is its width is 16 bit - wide. Address bus is unidirectional, the numbers are only sent from microprocessor to memory

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or ports not the other way. Using this address, 8085 microprocessor can access 64K byte of memory.

Data Bus Data Bus carries data in binary form between microprocessor and other external units, such as memory. The data bus typically consists of 8 wires and is bidirectional. The data bus also carries instructions from memory to the microprocessor. Therefore, the size of the bus limits the number of possible instructions to 256.

Control Bus Control Bus is various lines which have specific functions for coordinating and controlling uP operations. Eg: Read/Not Write line, single binary digit. Control whether memory is being ‘written to’ (data stored in mem) or ‘read from’ (data taken out of mem) 1 = Read, 0 = Write. May also include clock line(s) for timing/synchronizing, ‘interrupts’, ‘reset’ etc.

The Control Bus carries control signals partly unidirectional, partly bi-directional. Control signals are things like "read or write". This tells memory that we are either reading from a location or writing to a location specified.

Memory

Program, data and stack memories occupy the same memory space. The total addressable memory size in Intel 8085 microprocessor is 64 KB.

Program memory - program can be located anywhere in memory. Jump, branch and call instructions can be used to jump/branch anywhere within 64 KB.

Data memory - the processor always uses 16-bit addresses so that data can be placed anywhere.

Stack memory is limited only by the size of memory. Stack grows downward.

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8085 Pin description

The 8085 is an 8-bit general-purpose microprocessor capable of addressing 64K of memory. The device has forty pins, requires a +5V single power supply, and can operate with a 3-MHz single phase clock.

supply, and can operate with a 3-MHz single phase clock. Fig.1.4. Pin configuration of Intel 8085

Fig.1.4. Pin configuration of Intel 8085 Microprocessor

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Pin Description The following describes the function of each pin:

Address Bus: A15-A8, AD7-AD0 (Output 3 States) The 8085 has 16 signal lines (pins) that are used as the address bus; however, these lines are split into segments: A15-A8 and AD7-AD0. The eight signal lines, A15-A8, are unidirectional and used for the most significant bits, called the high order address, a 16 bit address. The AD7-AD0 lines are used for dual purpose.

AD0 - AD7 (Input/output 3state) Multiplexed Address/Data Bus; Lower 8 bits of the memory address (or I/0 addresses) appear on the bus during the first clock cycle of a machine state. It then becomes the data bus during the second and third clock cycles. These lines enter into tri-stated during Hold and Halt modes. AD0 - AD7 are a bidirectional: they serve as a dual purpose. They are used as the lower-order address bus and data bus.

ALE (Output) Address Latch Enable: It occurs during the first clock cycle of a machine state and enables the address to get latched into the on chip latch of peripherals. The falling edge of ALE is set to guarantee setup and hold times for the address information.

Data Bus Status (SO, S1 Output) S0 and S1 are status signals to specify the kind of operation being performed.

Encoded status of the bus cycle S1 S0

O

O HALT

0

1 Memory/IO WRITE

1

0 Memory/IO READ

1

1 Opcode FETCH

RD (Output tri-state) READ; indicates the selected memory or I/O device is to be read and that the Data Bus is available for the data transfer.

WR (Output tri-state) WRITE; indicates the data on the Data Bus is to be written into the selected memory or I/0 locations. Data is set up at the trailing edge of WR. 3 stated during Hold and Halt modes.

READY (Input)

If Ready is high during a read or write cycle, it indicates that the memory or peripheral is ready

to send or receive data. If Ready is low, the CPU will wait for Ready to go high before completing the read or write cycle.

HOLD (Input)

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HOLD; indicates that another Master is requesting the use of the Address and Data Buses. The CPU, upon receiving the Hold request, will relinquish the use of buses as soon as the completion of the current machine cycle. Internal processing can continue.

The processor can regain the buses only after the Hold is removed. When the Hold is acknowledged, the Address, Data, RD, WR, and IO/M lines are 3stated.

HLDA (Output) HOLD ACKNOWLEDGE; indicates that the CPU has received the Hold request and that it will relinquish the buses in the next clock cycle. HLDA goes low after the Hold request is removed. The CPU takes the buses one half clock cycles after HLDA goes low.

Interrupts

The processor has 5 interrupts. They are presented below in the order of their priority (from lowest to highest):

INTR (Input) INTERRUPT REQUEST; is used as a general purpose interrupt. It is sampled only during the next to the last clock cycle of the instruction. If it is active, the Program Counter (PC) will be inhibited from incrementing and an INTA will be issued. INTR is maskable interrupt. When the interrupt occurs, the processor usually fetches one of these instructions:

8 RST instructions (RST0 - RST7). The processor saves current program counter into and branches to memory location N * 8 (where N is a 3-bit number from 0 to 7 supplied with the instruction).

CALL instruction (3 byte instruction). The processor calls the subroutine, address of which is specified the second and third bytes of the instruction.

INTA (Output) INTERRUPT ACKNOWLEDGE; is used instead of (and has the same timing as) RD during the Instruction cycle after an INTR is accepted. It can be used to activate the 8259 Interrupt chip or some other interrupt port.

RST5.5 (Input) is a maskable interrupt. When this interrupt is received the processor saves the contents of the register into stack and branches to 2Ch (hexadecimal) address.

RST6.5 (Input) is a maskable interrupt. When this interrupt is received the processor saves the contents of the register into stack and branches to 34h (hexadecimal) address.

RST7.5 (Input) is a maskable interrupt. When this interrupt is received the processor saves the contents of the register into stack and branches to 3Ch (hexadecimal) address.

Trap is a non-maskable interrupt. When this interrupt is received the processor saves the contents of the register into stack and branches to 24h (hexadecimal) address. Related links

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All maskable interrupts can be enabled or disabled using EI and DI instructions. RST 5.5, RST6.5 and RST7.5 interrupts can be enabled or disabled individually using SIM instruction.

RESET IN (Input) Reset sets the Program Counter to zero and resets the Interrupt Enable, HLDA flip flops flags and registers (except the instruction register) are affected. The CPU is held in the reset condition as long as Reset is applied.

RESET OUT (Output) Indicates CPU is being reset. It can be used as a system RESET. The signal is synchronized to the processor clock.

X1, X2 (Input) X0 and X1 are inputs from the crystal or clock generating circuit. The frequency is internally divided by 2. So, to run the microprocessor at 3 MHz, a clock running at 6 MHz should be connected to the X0 and X1 pins.

CLK (Output) CLK pin is an output clock line to drive the clock of the rest of the system.

IO/M (Output) IO/M indicates whether the Read/Write is to memory or I/O during Hold and Halt modes.

SID (Input) Serial input data line. The data on this line is loaded into accumulator bit 7 whenever a RIM instruction is executed.

SOD (output) Serial output data line. The output SOD is set or reset as specified by the SIM instruction.

Vss: Ground reference. Vcc: +5V power supply.

Instruction and Computer Languages

An instruction is a binary pattern entered through an input device in memory to command the microprocessor to perform that specific function.

An instruction can be written in a variety of forms. We write instructions using their mnemonic codes and symbolic address. However a microprocessor can decode and execute only binary coded instruction. Therefore, for each operation that can be executed by a microprocessor, there is a binary code.

8085 instruction set consists of the following instructions:

Data transfer instructions: This group of instructions copy data from a location called a source to another location called a destination, without modifying the contents of the source. Input/output instructions are data transfer instructions.

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Arithmetic instructions - These instructions perform arithmetic operations such as addition, subtraction, increment, and decrement. Addition - Any 8-bit number, or the contents of a register or the contents of a memory location can be added to the contents of the accumulator and the sum is stored in the accumulator. No two other 8- bit registers can be added directly.

Logic instruction-These instructions perform various logical operations with the contents of the accumulator such as AND, OR, Exclusive-OR. Any 8-bit number, or the contents of a register, or a memory location can be logically ANDed, Ored, or Exclusive-ORed with the contents of the accumulator.

Rotate- Each bit in the accumulator can be shifted either left or right to the next position.

Compare- Any 8-bit number or the contents of a register, or a memory can be compared for equality, greater than, or less than, with the contents of the accumulator.

Complement - The contents of the accumulator can be complemented. All 0s

are replaced by 1s and all 1s are replaced by 0s.

Control transfer -This group of instructions alters the sequence of program execution either conditionally or unconditionally. Jump - Conditional jumps are an important aspect of the decision-making process in the programming. These instructions test for a certain conditions (e.g., Zero or Carry flag) and alter the program sequence when the condition is met. In addition, the instruction set includes an instruction called unconditional jump, Call, Return, and Restart.

Other - setting/clearing flag bits, enabling/disabling interrupts, stack operations, etc.

Machine Language

A machine language program is written using binary codes and addresses. A microprocessor

only understands machine language programs. Machine language coding is time-consuming and error-prone. Usually machine language programmers are concerned with hardware details. Every computer or family of computers has its own machine language; each is machine-dependent

Assembly Language is a symbolic representation of machine language of a specific processor or

is a symbolic, non-binary format instruction (human-readable version of machine language) that

allows mnemonic names to be used for instructions and data. Assembly language is converted to machine code by an assembler. Usually, each line of assembly code produces one machine instruction. It is easier to write an assembly language program for a microprocessor than to write a machine language program.

In short assembly languages:

Represent a string of ‘0s’ and ‘1s’ for machine language instruction

More English-like; codes shorter than machine languages

Assembler translates into machine language

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Advantages of machine or assembly languages

Programmer in control of hardware

– Programs written in low-level languages run more efficiently

High level languages High level languages are designed to be easier to understand than assembly languages and allow

a program to run on multiple different kinds of computers. The source code written in high level languages need to be translated into object code. The two basic approaches are compilers and interpreters.

ASSEMBLY LANGUAGE OR MACHINE LANGUAGE To word this simply, you can say that assembly language is a human-readable text, and machine language is machine-readable binary code. When you program in assembly language, you are programming on the machine language level. To program directly in machine language is tedious, so you use assembly language instead, and use an assembler to produce the actual machine code.

Advantages of higher level programming:

Ease of learning the language

Significantly shorter code

Ease of debugging

Ease of maintenance

Disadvantages of higher level programming:

Less control over hardware

Less efficient memory use

Program runs more slowly

Compilers convert a finished program (or section of a program) into object code. This is often done in steps. Some compilers convert high level language instructions into assembly language instructions and then an assembler is used to create the finished object code.

Interpreters convert each high level instruction into a series of machine instructions and then immediately run (or execute) those instructions. In some cases, the interpreter has a library of routines and looks up the correct routine from the library to handle each high level instruction.

Assembler is a program that translates an assembly language program from mnemonics to the binary machine code. i.e. Converts assembly language programs into object files.

• Object files contain a combination of machine instructions, data, and information needed to place instructions properly in memory

• Assemblers need to

– translate assembly instructions and pseudo-instructions into machine instructions

– Convert decimal numbers, etc. specified by programmer into binary

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Typically, assemblers make two passes over the assembly file

First pass: reads each line and records labels in a symbol table

Second pass: use info in symbol table to produce actual machine code for each line

Linker Tool that merges the object files produced by separate compilation or assembly and creates an executable file.

Loader Part of the OS that brings an executable file residing on disk into memory and starts it running

Steps

– Read executable file’s header to determine the size of text and data segments

– Create a new address space for the program

– Copies instructions and data into address space

– Copies arguments passed to the program on the stack

– Initializes the machine registers including the stack ptr

– Jumps to a startup routine that copies the program’s arguments from the stack to registers and calls the program’s main routine.

from the stack to registers and calls the program’s main routine. Compiled by Solomon Teklehaimanot Page

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Mekelle Institute of Technology Microprocessor Lecture note February 2, 2010 Compiled by Solomon Teklehaimanot Page 15

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Chapter Two 8085 INSTRUCTION SET

DATA TRANSFER INSTRUCTIONS

One of the primary functions of the microprocessor is copying data from a register (or IO or memory) called the source to another register (or IO or memory) called the destination.

Sources and Destination can be Registers, Memory and Devices. I.e. data transfer can take place

between:

1. Registers [from one Register to another]

2. Specific data byte to a register or a memory location

3. Memory a memory location and a register

4. An IO device and the accumulator

Move immediate 8-bit

MVI instruction is a two byte instruction

Table 1 MVI Instruction

Opcode

Operand

Flag

Description

affected

MVI

Rd, data

None

The 8-bit data is stored in the destination register or memory. If the operand is a memory location, its location is specified by the contents of the HL registers.

M, data

Example:

MVI B, 57H; copies the byte 57H into register B MVI M, 57H; copies 57H to the memory location pointed by HL

Copy from source to destination

MOV instruction is a one byte instruction

Table 2: MOV Instruction

Opcode

Operand

Flag affected

Description

MOV

Rd,

Rs

None

This instruction copies the contents of the source register into the destination register; the contents of the source register are not altered. If one of the operands is memory location, its location is specified by the contents of the HL registers.

M,

Rs

Rd,

M

Example: MOV B, C; copies the byte value stored in register C to register B MOV B, M; the byte value pointed by HL is copied to register B Possible register combination:

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MOV A, B; AB MOV D, L; DL MOV H, E; HE MOV A, C; AC

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MOV L, H; LH Specify the content of registers and the flags as the following instructions are executed.

 

A

B

C

D

S

P

Z

C

 

MVI

A, FFH

 

MVI

B, 58H

MOV C, A

MOV D, B

HLT

Answer

 

Mnemonics

 

A

B

 

C

D

S-Flag

P-Flag

Z-Flag

C-Flag

MVI

A,

FFH

XX

XX

XX

X

X

X

X

FFH

MVI

B, 58H

FFH

58H

XX

XX

X

X

X

X

MOV C, A

 

FFH

58H

FFH

XX

X

X

X

X

MOV D, B

 

FFH

58H

FFH

58H

X

X

X

X

 

HLT

               

Load Accumulator

Table 3 LDA Instruction

LDA (Load Accumulator Direct) instruction is a 3 byte instruction

Opcode

Operand

Flag

affected

Description

LDA

16-bit address

None

The contents of a memory location, specified by a 16-bit address in the operand, are copied to the accumulator. The contents of the source are not altered.

Example: LDA 2034H; the byte value found in 2034H is copied to register A. Assume the value at the memory address 2034H is B6H. When the processor executes the above instruction, B6H

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will be loaded into Accumulator register. I.e. A<= B6H. The content of the memory location is not altered.

Table 4 : Memory Values

Memory

Byte

Location

value

2035H

XX

2034H

B6H

2033H

XX

Example-2: Specify the content of register A after the following instruction is being executed. Assume the byte value at memory location 33FEH is 90H.

MVI B, BDH

MOV A, B

LDA

33FEH

HLT

Table 5: Memory values

Memory

Byte

location

value

3401H

10H

3400H

32A

33FFH

5AH

33FEH

90H

33FDH

00H

Answer

Mnemonics

A

B

MVI B, BDH

XX

BDH

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MOV A, B

BDH

BDH

LDA 33FEH

90H

BDH

HLT

Load Accumulator Indirect

Table 6: LDAX Instruction

LDAX (Load Accumulator Indirect) instruction is a 1 byte instruction

Opcode

Operand

Flag

affected

Description

LDAX

B/D register pair

None

The contents of the designated register pair point to a memory location. This instruction copies the contents of that memory location into the accumulator. The contents of either the register pair or the memory location are not altered.

Example-1: LDAX B; byte value pointed by register pair BC is copied to register A. BC holds the 16-bit address. Assume BH holds 4567H. The processor will load accumulator with the value in this memory location.

Table 7: Memory Value

Memory

Byte

location

value

4569H

01H

4568H

23A

4567H

66H

4566H

4FH

4565h

CCH

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After the microprocessor executes the instruction register A will contain 66H.

Example-2: Specify the content of register A after the following instruction is being executed. Assume the byte value at memory location F000H is 44H. BC=F000H.

MVI B, F0H MVI C, 00H MOV A, B LDAX B HLT

Table 8: Memory values

Memory

Byte

location

value

F002H

10H

F001H

32A

F000H

5AH

EFFFH

90H

EFFEH

00H

Answer

Mnemonics

A

B

MVI B, F0H

XX

F0H

MVI C, 00H

XX

F0H

MOV A, B

F0H

F0H

LDAX B

5AH

44H

HLT

   

Load register pair immediate

Table 8: LXI Instruction

LXI (Load Register Pair) instruction is a 3 byte instruction.

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Opcode

Operand

Flag

Description

affected

LXI

Reg. Pair, 16 bit data

None

The instruction loads 16-bit data in the register pair designated in the operand.

The second byte is loaded in the higher order register example register B or D and the third byte is loaded in the lower order register. Example-1: LXI H, 2034H; loads 20 in register H and 34 in register L LXI B, 8B0FH; loads 8B in register B and 0F in register C

Example-2: Write a program that loads the value pointed by the 16-bit address value in the register pair HL to the accumulator register. Assume the value in the register pair HL is 5468H.

LXI H, 5468H;

LDAX H

HLT

Load H and L registers direct

LHLD instruction is a three byte instruction.

Table 9: LHLD Instruction

Opcode

Operand

Flag

Description

affected

LHLD

16-bit address

None

The instruction copies the contents of the memory location pointed out by the 16-bit address into register L and copies the contents of the next memory location into register H. The contents of source memory locations are not altered.

Example-1: LHLD 2040H; loads the byte value pointed by 2040H into register L and the byte value found in 2041H into register H. Answer

L<= [2040H]

H<= [2041H] Example-2: Assume memory location 8000H contains 20H and 8001 contains FEH. Write a program that transfers content of memory location 8000H to L and 8001H to H.

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Answer

LHLD 8000H

Address

Memory

Content

7FFFH

xx

8000H

20H

8001H

FEH

8002H

YY

Content of register pair HL after the above instruction is being

executing

Register H

Register L

FEH

20H

Store Accumulator Direct

STA (Store Accumulator Direct) is a 3 byte instruction.

Table 10: STA Instruction

Opcode

Operand

Flag

Description

affected

STA

16-bit address

None

The contents of the accumulator are copied into the memory location specified by the operand. The second byte specifies the Higher-order address and the third byte specifies the lower-order address.

Example-1: MVI A, 33 STA 8050H; stores the byte value of the accumulator in memory location pointed by

4050H.

Before execution of the STA 8050H instruction

After execution of the above instruction

Address

Value

Address

Value

804FH

XX

804FH

XX

8050H

XX

8050H

33H

8051H

XX

8051H

XX

Accumulator

33H

Accumulator 33H
Accumulator 33H

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Store Accumulator Indirect

Microprocessor Lecture note

February 2, 2010

STAX (Store Accumulator Indirect) instruction is a 1 byte instruction.

Table 11 : STAX Instruction

Opcode

Operand

Flag

affected

Description

STAX

Reg. pair

None

The contents of the accumulator are copied into the memory location specified by the contents of the operand (register pair). The contents of the accumulator are not altered.

Example-1: LXI B, 800FH, STAX B; stores the byte value of the accumulator in memory location pointed by content of the register pair BC.

Before execution of the STAX B instruction

After execution of the above instruction

Address

Value

Address

Value

800EH

XX

800EH

XX

800FH

XX

800FH

A7H

8010H

XX

8010H

XX

Store H and L registers direct

Accumulator

A7H

Table 12 : SHLD Instruction

SHLD (Store HL Register pair Direct) is a 3 byte instruction.

Opcode

Operand

Flag

affected

Description

SHLD

16-bit address

None

The contents of register L are stored into the memory location specified by the 16-bit address in the operand and the contents of H register are stored into the next memory location by incrementing the operand. The contents of registers HL are not altered. This is a 3-byte instruction, the second byte specifies the low-order

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Microprocessor Lecture note

February 2, 2010

address

and

the

third

byte

specifies

the

high-order

address.

Example-1: LXI H, 1122H, SHLD 2470H; stores the byte in register L in memory location 2470H and content of register H in 2471H.

Exchange H and L with D and E

XCHG instruction is a 1 byte instruction.

Table 13: XCHG Instruction

Opcode

Operand

Flag

Description

affected

XCHG

None

None

The contents of register H are exchanged with the contents of register D, and the contents of register L are exchanged with the contents of register E.

Example: LXI H, 2020H LXI D, 0202H XCHG; 2020H will be loaded into register pair DE and 0202H into register HL HLT Copy H and L registers to the stack pointer

SPHL instruction is a one byte instruction.

Table 14: SPHL Instruction

Opcode

Operand

Flag

Description

affected

SPHL

None

None

The instruction loads the contents of the H and L registers into the stack pointer register, the contents of the H register provide the high-order address and the contents of the L register provide the low-order address. The contents of the H and L registers are not altered.

Example-1: LXI SP, 8088H LXI H, 9099H SPHL; 16 bit value of the register pair HL will be loaded into 16-bit stack pointer register

SPL<=99

SPH<=90

The content of register pair HL is not altered.

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Microprocessor Lecture note

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Push onto/Pop of the stack

Stack

A stack is a group of memory locations in the R/W memory which is used to store information

temporarily during the execution of a program. Also the stack is used in subroutine calls to store

the return address.

As an example, data generated at a certain point in a program may be needed later in the program. This data is stored in the stack and retrieved when needed. Because the number of general purpose registers (GPRs) in a microprocessor is limited–hence not all the temporary data can be stored in them and this is where the stack plays its part.

The stack is initialized by a 16-bit register, called the stack pointer (SP) register. But initialization

is not a must. If for programs for which any temporary data that are generated can be stored in

GPRs and which don’t require subroutine calls, there is no need to initialize the stack by the SP.

The stack is used by programmer and a system. Programmer uses the stack for storage/retrieval

of data by using the PUSH/POP instructions respectively. On the other hand, the system uses the

stack to store return address whenever subroutine CALL is used.

Stack Initialization

There are two ways to initialize the stack:

(a)

Direct way

(b)

Indirect way

Example of method (a)

LXI SP, 4400 H; loads the stack pointer with 4400 H so that it points at the memory address 4400 H.

Example of method (b)

LXI H, 16-bit data; load 16-bit data into HL register pair

SPHL; contents of HL register pair is loaded into SP.

In most of the cases the stack pointer is initialized by direct way, but method (b) is sometimes

used when one wants to set the stack pointer by means of programming.

Structure of a stack in 8085 Microprocessor

Stack is a ‘last-in first-out’ or LIFO type of memory. This means that data which is pushed last into stack is popped out of it first.

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Push register-pair onto stack

Microprocessor Lecture note

PUSH instruction is a 1 byte instruction.

February 2, 2010

Table 15: PUSH Instruction

Opcode

Operand

Flag

Description

affected

PUSH

Reg. pair

None

The contents of the register pair designated in the operand are copied onto the stack in the following sequence. The stack pointer register is decremented and the contents of the higher order register (B, D, H, A) are copied into that location. The stack pointer register is decremented again and the contents of the low-order register (C, E, L, flags) are copied to that location.

Example-1: PUSH B PUSH PSW Example-2: Assuming the stack pointer SP=1234H, A=55H, Flag Register= 88H, BC= A04FH, DE= B0A2H and HL = 5089H. Show the contents of the stack as each of the following instructions is executed.

PUSH PSW

PUSH B

PUSH D

PUSH H

Pop off stack to register pair POP instruction is a 1 byte instruction.

Opcode

Operand

Flag

Description

affected

POP

Reg. pair

None

The contents of the memory location pointed out by the stack pointer register are copied to the low-order register (C, E, L, status flags) of the operand. The stack pointer is incremented by 1 and the contents of that memory location are copied to the high-order register (B, D, H, A) of the operand. The stack pointer register is again incremented by 1.

Example-1: POP H POP PSW

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Example-2: Assuming the stack pointer SP=122DH and Content of a stack is as shown below. Show the contents of the stack and registers as each of the following instructions is executed.

LXI

SP, 122DH

POP

H

POP

D

POP

B

POB PSW

HLT

122D

88H

122E

55H

122FH

4FH

1230H

A0H

1231H

A2H

1232H

B0H

1233H

89H

1234H

50H

Fig: Stack memory

Exchange H and L with top of stack

Table 16: XTHL Instruction

Opcode

Operand

Flag

Description

affected

XTHL

None

None

The contents of the L register are exchanged with the stack location pointed out by the contents of the stack pointer register. The contents of the H register are exchanged with the next stack location (SP+1); however, the contents of the stack pointer register are not altered.

Example-1: Assuming stack value at A09CH is 44H and at A09BH is A0H; specify the content of register pair HL and stack values at memory locations A09CH and A09BH after the following instruction is being executed.

LXI

SP, A09CH

LXI

H, F0FEH

XTHL

HLT

Answer HL<= 44A0H [A09CH] <=F0H [A09BH] <=FEH

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Output data from accumulator to a port with 8-bit address

Opcode

Operand

Flag

Description

affected

OUT

8-bit port address

None

The contents of the accumulator are copied into the I/O port specified by the operand.

Example-1: MVI A, 66H OUT F8H HLT Example-2: Load the hexadecimal number FFH in register D and display the number at output port with the address 20H. Answer

MVI D, FFH

MOVA, D

OUT 20H

HLT

Input data to accumulator from a port with 8-bit address

Opcode

Operand

Flag

Description

affected

OUT

8-bit port address

None

The contents of the input port designated in the operand are read and loaded into the accumulator.

Example-1: MVI A, 00H IN 8CH HLT Example-2: If the switch S3 of the input port (in the figure below) connected to the data line D3 is at logic 1 and other switches are at logic 0:

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of Technology Microprocessor Lecture note February 2, 2010 a) Specify the contents of the accumulator when

a) Specify the contents of the accumulator when the instruction IN 4FH is executed.

b) Specify the output at port 03H and the contents of register D after executing the instructions.

MVI

B, 00H

MVI

A, 99H

IN 4FH

MOV D, A

OUT 03H

HLT

Answer:

a) 08H

b) 08H

Arithmetic Operations The 8085 microprocessor performs various arithmetic operations, such as addition, subtraction, increment and decrement. Addition and subtraction operations are performed in relation to the contents of the accumulator. However, the increment and decrement operations can be performed in any operand (register or memory).

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Addition The 8085 microprocessor performs addition with 8-bit binary numbers and stores the sum in the accumulator. Addition can be performed either by adding the contents of a source register or memory to the contents of the accumulator or a byte value directly to the contents of the accumulator.

Add register or memory value to accumulator

 

Operand

Flag affected

 

Description

ADD

M

All

flags

are

The content of the operand (register or memory) is

R

modified to reflect

added to the contents of the accumulator and the result is stored in the accumulator. If the operand is a memory location, its location is specified by the contents of the HL registers.

the result

of

the

addition.

 

Example -1: Write a program that performs the following functions:

1. the number 8BH in register D

Load

2. the number located in the memory location 9095H to register C

Load

3. Increment the contents of register C

4. Add the content of registers C and D and display the sum at port 89H

Answer

MVI

D, 8BH

MVI

D, 8BH

LDA

9095H

LXI H, 9095H MOV C, M MVI A, 01H ADD C ADD D

MOV C, A

MVI

A, 01H

ADD C

ADD D

OUT

89H

OUT

89H

HLT

HLT

Add register to accumulator with carry

Opcode

operand

Flag affected

Description

ADC

M

All flags

are

The contents of the operand (register or memory) and

R

modified to reflect

the Carry flag are added to the contents of the

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the

result

of

the

accumulator and the result is stored in the accumulator. If the operand is a memory location, its location is specified by the contents of the HL registers. All flags are modified to reflect the result of the addition.

addition.

 

Example-1: MVI A, 8DH

 
 

MVI

B, F0H

MVI

C, 01H

ADD B

 

ADC C

HLT

Add immediate to accumulator

 

Opcode

Operand

Flag Affected

 

Description

ADI

8-bit

All

flags

are

The 8-bit data (operand) is added to the contents of the accumulator and the result is stored in the accumulator. All flags are modified to reflect the result of the addition.

data

modified to reflect

the result

of

the

addition.

 

Example: Assume the byte value at memory location 8099H is CFH:

LXI D, 8099H

LDAX D

ADI 45H

HLT

Add immediate to accumulator with carry

Opcode

Operand

Flag Affected

Description

ACI

8-bit data

All flags are modified to reflect the result of the addition.

The 8-bit data (operand) and the Carry flag are added to the contents of the accumulator and the result is stored in the accumulator. All flags are modified to reflect the result of the addition.

Example: Assume the byte values A4H and 39H are found in memory locations 997E, 997FH respectively. Write a program that adds these values with an immediate value 45H.

Answer:

LDA 997EH

LXI H, 997FH

ADD M

ACI 45H

HLT

Add register pair to H and L registers

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Opcode

Operand

Flag Affected

Description

DAD

Reg. pair

If the

result is

The 16-bit contents of the specified register pair are added to the contents of the HL register and the sum is stored in the HL register. The contents of the source register pair are not altered.

larger than 16 bits, the CY flag

is set. No other flags are affected.

Example-1: Specify the contents of the registers H, L, D and E when the following program is being executed.

Answer

 

Mnemonics

D

E

H

L

LXI

H, 5066H

XX

XX

50H

66H

LXI

D, 4031H

40H

31H

50H

66H

DAD D

40H

31H

90H

97H

HLT

       

Example-2: Write an 8085 assembly language program that multiply content of register pair HL by 2. Answer: LXI H, 16 bit value DAD H HLT

Subtraction

The 8085 microprocessor performs subtraction by using the method of 2’s complement. The

value in accumulator register is regarded as the minuend (the number from which to subtract). The 8085 microprocessor performs the following steps internally to execute subtraction instruction.

1. Converts subtrahend (the number to be subtracted) into its 1’s complement

2. Add 1 to 1’s complemented to obtain 2’s complement of the subtrahend.

3. Add 2’s complement to the minuend (the contents of the accumulator)

4. Complements the carry flag

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Subtract register or memory from accumulator

Opcode

Operand

Flag Affected

Description

SUB

R

All

flags are

The contents of the operand (register or memory) are

M

modified

to

subtracted from the contents of the accumulator, and the result is stored in the accumulator. If the operand is a memory location, its location is specified by the contents of the HL registers.

reflect the result

of

the

subtraction.

Example-1: Register D has 89H and the accumulator has F2H. Write a program that subtracts the contents of register D from the contents of the accumulator.

Answer

MVI

D, 89H

MVI

A, F2H

SUB

D

HLT

Example-2: Write an 8085 assembly language program that performs the following functions:

1. Load the number 72H in register C and 96H in register B

2. Subtract 96H from 72H

3. Display the answer at port address 8FH

Answer:

MVI

C, 72H

MVI

B, 96H

MOV A, C

SUB

B

OUT

8FH

HLT

Example-3: Write instructions to add the contents of the memory location 8090H to accumulator, and subtract the contents of the memory location 8091H from the sum. Assume the accumulator has 40H, the memory location 8090h has 4AH and the location 8091H has F7H. Answer

MVI A, 40H

LXI H, 8090H ADD M MOV B, A

LDA 8091H

MOV C, A MOV A, B

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SUB C

HLT

Microprocessor Lecture note

February 2, 2010

Subtract source and borrow from accumulator

Opcode

Operand

Flag Affected

Description

SBB

R

All

flags are

The contents of the operand (register or memory) and

M

modified

to

the Borrow flag are subtracted from the contents of the accumulator and the result is placed in the accumulator. If the operand is a memory location, its location is specified by the contents of the HL registers.

reflect the result

of

the

subtraction.

Example: SBB B or SBB M

Subtract immediate from accumulator

Opcode

Operand

Flag Affected

Description

SUI

8-bit data

All

flags are

The 8-bit data (operand) is subtracted from the contents of the accumulator and the result is stored in the accumulator.

modified

to

reflect the result

of

the

 

subtraction.

Example:

LXI B, F000H

LDAX

SUI 45H

HLT

Subtract immediate from accumulator with borrow

Opcode

Operand

Flag Affected

 

Description

SBI

8-bit data

All

flags

are

The 8-bit data (operand) and the Borrow flag are subtracted from the contents of the accumulator and the result is stored in the accumulator.

modified

to

reflect

the

result

of

the

subtraction.

   

Example-1:

MVI A, 30H

SUI 45H

SBI 01H

HLT

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Increment register or memory by 1

February 2, 2010

Opcode

Operand

Flag Affected

Description

INR

R

All flags except a

The contents of the designated register or memory) are incremented by 1 and the result is stored in the same place. If the operand is a memory location, its location is specified by the contents of the HL registers.

M

carry flag is affected

Example-1: MVI D, 44H MOV B, D INR B HLT Example-2 Assume the value at memory location F07AH is 7FH. Specify the value of memory location after INR M instruction is being executed. Answer

 

H

L

Value of memory location F07AH

LXIH, F07AH

F0H

7AH

7FH

INR M

F0H

7AH

80H

HLT

     

Increment Register pair by 1

Opcode

Operand

Flag Affected

Description

INX

R

None

The contents of the designated register pair are incremented by 1 and the result is stored in the same place.

Example-1: Assume byte value at memory location 909FH is 00H and at memory location 90A0H is FFH. What is the content of register B when MOV B, M instruction is being executed?

LXI

H, 909FH

INX

H

MOV B, M HLT Answer: B=FFH

Example-2: Write the instruction to load the number 5020H in the register pair BC. Increment the number using the instruction INX B and illustrate whether the INX B is equivalent to the instructions INR B and INR C.

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Answer

LXI

INX

HLT

After

B, 5020H

B

the above instruction has been executed register pair BC will contain 5021H.

LXI

B, 5020H

INR

B

INR

C

HLT

Register pair BC will hold 5121H.

Decrement register or memory by 1

Opcode

Operand

Flag Affected

Description

DCR

R

All flags except a

The contents of the designated register or memory are decremented by 1 and the result is stored in the same place. If the operand is a memory location, its location is specified by the contents of the HL registers.

M

carry flag is affected

Example-1:

 

MVI

C, 00H

MOV B, C

DCR B

MOV C, B

HLT

Example-2: Write instructions that load 40H in memory location 8091H, and decrement the

contents of the memory location 8091H.

Answer:

LXI

MVI

STAX B

LXI

DCR

HLT

B 8091H

A, 40H

H, 8091H

M

Decrement Register pair by 1

Opcode

Operand

Flag Affected

Description

DCX

R

None

The contents of the designated register pair are decremented by 1 and the result is stored in the same place.

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Example:

Microprocessor Lecture note

February 2, 2010

LXI H, 9A70H DCX H HLT Contents of register pair HL after the above instructions have been executed is 9A6FH.

Decimal Adjust Accumulator

Opcode

Operand

Flag Affected

 

Description

DAA

None

S,

Z,

AC,

P,

CY

The contents of the accumulator are changed from a binary value to two 4-bit binary coded decimal (BCD) digits. This is the only instruction that uses the auxiliary flag to perform the binary to BCD

flags are altered to reflect

the

results

of

the

operation

 

conversion, and the conversion procedure is described below.

 

If the value of the low-order 4-bits in the accumulator is greater than 9 or if AC flag is set, the instruction adds 6 to the low- order four bits.

If the value of the high-order 4-bits in the accumulator is greater than 9 or if the Carry flag is set, the instruction adds 6to the high-order four bits.

Example: obtain the value after DAA instruction is executed on the following additions.

a) A, 03H

MVI

b) MVI A, 09H

c) MVI A, 08H

MVI

C, 05H

MVI B, 06H

MVI D, 05H

ADD C

ADD B

ADD D

DAA

DAA

DAA

HLT

HLT

HLT

Answer

a) 08 in decimal

b) 15 in binary coded decimal

c) 13 in binary coded decimal

BCD Subtraction

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When subtracting two BCD numbers, the instruction DAA cannot be used to decimal adjust the result of two packed BCD numbers. The DAA instruction applies only to addition. Therefore, it is necessary to device a procedure to subtract two BCD numbers. Two BCD numbers can be subtracted using the procedure of 100’s complements.

To subtract two BCD numbers, in short add 100’s complement of the subtrahend to a minuend and then adjust it using DAA instruction.

Example: 82-48 (= 34) can be performed as follows:

100’s complement of 48 is 52 i.e. 100-48=52

Then add it with the minuend (82)

82 + 52 = D4H, the higher nibble is greater than 9, so add 60H.

D4H + 60H = 1/34, discard the carry => 34H

However, in 8-bit microprocessor, it is not possible to find 100’s complement of a subtrahend (100 BCD requires twelve bits). Therefore, in writing a program, 100’s complement is obtained by finding 99’s complement and adding 01.

Example: Subtract 01 from 90 in BCD

MOV B, 90H MOV C, 01H

MVI

A, 99H

SUB

C, Find 99’s complement of Subtrahend

INR A, Find 100’s complement of subtrahend ADD B, Add minuend to 100’s complement of subtrahend DAA, Adjust for BCD HLT

BRANCHING INSTRUCTIONS

Jump instructions

Jumps are of two types namely; unconditional and conditional.

Jump Unconditionally

The unconditional jump instruction is a 3-byte instruction with the first byte containing the Opcode and the second and the third bytes containing the address. When the unconditional jump instruction is executed, the second and the third address bytes are loaded in the PC counter. The microprocessor will fetch next instruction from the memory at the new address.

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JMP instruction is three byte instruction.

February 2, 2010

Opcode

Operand

Flag

Description

Affected

JMP

16-bit address

None

The program sequence is transferred to the memory location specified by the 16-bit address given in the operand.

Example-1: Identify the memory locations that are cleared by the following instructions:

MVI B, 00H LXI H, 9005H JMP XXXX MOV M, B XXXX: INX H MOV M, B INX H INX H MOV M, B HLT

Jump conditionally

All conditional jump instructions are three byte instructions. The program sequence is transferred to the memory location specified by the 16-bit address given in the operand based on the specified flag of the PSW as described below. I.e. conditional jump instructions are executed if the specified condition is satisfied or otherwise control proceeds in the sequence.

Opcode

Operand

Flag status

Flag Affected

Description

JC

 

CY = 1

None

Jump if Carry

JNC

 

CY = 0

None

Jump if no Carry

JP

 

S

= 0

None

Jump if positive

JM

 

S

= 1

None

Jump if minus

JZ

 

Z

= 1

None

Jump if zero

JNZ

 

Z

= 0

None

Jump if no zero

JPE

 

P

= 1

None

Jump if parity is even

JPO

 

P

= 0

None

Jump if parity is odd

Example-1 Write an assembly language program to add N byte binary numbers stored from location X+1, where N is stored at location X. Store the result in location Y and Y+1. Store the program starting from F000H Store the count at location F100H

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