//The switch has one input port from which the packet enters.

It has two output

ports where the packet is driven out.
//Packet Format - Packet contains 3 parts: Header, payload and Parity Sequence.
//Packet width is 8 bits and the length of the packet can be between 4 bytes to 259
bytes.
//Packet Header - Packet header contains three fields DA, SA and length.
//DA - Destination address of the packet. 8 bits length.
//The switch drives the packet to respective ports based on the destination address
of the packets. Each output port has 8-bit unique port address. If the destination
address of the packet matches the output port address, then the switch drives the
packet to that output port. The output ports are numbered 0 and 1.
//SA - Source address of the packet from where it originates. 8 bits length. Will
be a constant – FFh.

module switch (
input clk,
input reset,
input [7:0] data,
input valid,
output logic [7:0] port0,
output logic [7:0] port1,
output logic ready_0,
output logic ready_1,
output logic packet_error_0,
output logic packet_error_1
);

logic [8:0] counter;

logic [8:0] next_counter;
input [7:0] length;

logic is_da = valid && (next_counter == 9'd1);

logic in_length = valid && (next_counter == 9'd3);
logic in_payload = valid && (next_counter == 9'd4);
logic in_ps = valid && (!next_ready_0||!next_ready_1);

logic next_counter = (valid)?counter + 'd1:'d0;

logic da_is_0 = is_da && (data == 8'd0);
logic da_is_1 = is_da && (data == 8'd1);
logic next_port0 = (da_is_0||ready_0)? data: 8'd0;
logic next_port1 = (da_is_1||ready_1)? data: 8'd0;
logic next_ready_0 = (da_is_0)? 1'd1:(valid && ready_0);
logic next_ready_1 = (da_is_1)?1'd1:(valid && ready_1);

logic error1 = ((counter < 4)&&(counter > 0) && !valid);

logic error2 = (in_ps && (next_counter != length + 4);

//logic next_error_0 =
//logic next_error_1 =

//need to add that if there is an error, the ready flag should be down.
(atleast 2 cycles between ready goes down and another ready comes up)
//Create a wire that calculate PS, Than, compare it to the PS in the packet
logic ps;

always@(posedge reset, posedge clk)

if (reset)
begin
 port0 <= 8'd0;
port1 <= 8'd0;
ready_0 <= 1'd0;
ready_1 <= 1'd0;
packet_error_0 <= 1'd0;
packet_error_1 <= 1'd0;
counter <= 9'd0;
length <= 8'd0;
end
else
begin
counter<=next_counter;
end

if (is_da)
begin
if (data == 8'd0)
begin
ready_0 <= 1'd1;
port_0 <= data;
end
if (data == 8'd1)
begin
ready_1 <= 1'd1;
port_1 <= data;
end
end
if (in_length)
begin
length <= data;
end

if (valid && ready_1)

port1 <= data;
else
if (valid && ready_0)
port0 <= data;